EMBEDDED-PPT

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A SEMINAR on Industrial Training:

A SEMINAR on Industrial Training Electronics Department Marudhar Engineering College , Raisar Bikaner ( Rajasthan ) GEETANJALI CHELLANI ECE-IV year

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SUMMER TRAINING (18 th May To 17 th June) EMBEDDED SYSTEMS At E-Force, Chandigarh

What is Embedded system ? :

What is Embedded system ? An embedded system is a computer system that is integrated into a larger system which is not, itself, a general purpose computer.

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Aspects of a Embedded System  Hardware : Interface to the real world  Software : order how to deal with inputs

Classification of Embedded Systems :

Classification of Embedded Systems  Microprocessor Based : A microprocessor is a simple processor intended for general computing tasks. Must be accompanied by separate memory and peripherals chips.  Micro controller Based : A micro controller is a microprocessor with memory, I/O, peripherals and connecting buses all fabricated on single silicon piece. Optimized for control applications

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Why do we need to learn Microprocessors/controllers?  The microprocessor/controller is the core of computer systems.  Nowadays many communication, digital entertainment, portable devices, are controlled by them.  A designer should know what type of components are needed, which reduce production costs and product reliable.

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Microprocessor 8085

Microprocessor:

CPU General-Purpose Micro-processor RAM ROM I/O Port Timer Serial COM Port Data Bus Address Bus Microprocessor * CPU for Computers * No RAM, ROM, I/O on CPU chip itself * Example : Intel’s x86, Motorola’s 680x0 Many chips on mother’s board  General-purpose microprocessor

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Microcontroller 8051

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RAM ROM I/O Port Timer Serial COM Port Microcontroller CPU * A smaller computer * On-chip RAM, ROM, I/O ports... * Example : Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X A single chip Microcontroller

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 The necessary tools for a microcontroller * CPU: Central Processing Unit * I/O: Input /Output * Bus: Address bus & Data bus * Memory: RAM & ROM * Timer * Interrupt * Serial Port * Parallel Port

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Pin Description of the 8051 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (T0)P3.4 (T1)P3.5 XTAL2 XTAL1 GND (INT0)P3.2 (INT1)P3.3 (RD)P3.7 (WR)P3.6 Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8) 8051 (8031)

Block Diagram of Microcontroller:

ALU Register (s) Timer/Counter Accumulator Internal RAM Stack Pointer Program Counter Internal ROM I/O Port I/O Port Interrupt Circuits Clock Circuit Block Diagram of Microcontroller

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ALU A B PC DPTR DPH DPL PSW Special Function Registers RAM ROM System Timing System Interrupts Timers Data Buffers Memory Ctrl Byte/Bit Addresses Register Bank 3 Register Bank 2 Register Bank 1 Register Bank 0 SFRS IE IP PCON SBUF SCON TCON TMOD TL0 TH0 TL1 TH1 L A T C H L A T C H L A T C H L A T C H P O R T 0 P O R T 1 P O R T 2 P O R T 3 EA ALE PSEN XTAL1 XTAL2 RESET VCC GND I/O A0-A7 D0-D7 I/O I/O A8-A15 I/O INTERRUPT COUNTER SERIAL DATA RD/WR INTERNAL RAM STRUCTURE 8 BIT Data and Address Bus 16 bit address bus

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A and B CPU Registers :  Hold results of many instructions,particularly math and logical operations Addition,Subtraction , Division,AND,OR .

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Program Counter PC:  16-bit register  PC points to the memory location from where instruction bytes needs to be fetched  PC gets incremented automatically after every instruction byte fetch, could be altered by certain instructions  PC only register not having internal address  Can address up to FFFFh as 16 bit.

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Data Pointer DPTR :  16-bit register  Made up of DPH ,DPL 8 –BIT registers  Used to furnish memory addresses for internal and external code access and data access

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INTERNAL RAM: 128 bytes of internal RAM is divided as following 00 to 7Fh:  32-Bytes from address 00h to 1fh , which makes 32 working registers organized as four banks of eight registers each. * Each register can be addressed by name(when that bank selected) or by its RAM address. * Bits RS0 ,RS1 in PSW selects Register Bank.On RESET Bank 0 selected. 16-Bytes from address 20h to 2Fh .Bit addressable,total of 128 addressable bits.Bit and Byte addressable  General purpose byte addressable from 30h to 7Fh .

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Internal RAM Organization : R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 1F 18 17 10 0F 08 07 00 B A N K 3 B A N K 2 B A N K 1 B A N K 0 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 7 0 BIT ADDRESSABLE 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 GENERAL PURPOSE 7F 30

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Internal ROM:  In 8051data memory and program code memory are two different entities.Each has the same address ranges.8051 has Harvard architecture.  VON NEUMANN architecture:Has single memory address for either program code or data but not for both .  HARVARD architecture:Has same address in different memories for code and data.  ROM – 4K. Address range from 0000h to 0FFFh 4k=2^2*2^10 =2^12 Min address range 0000 0000 0000 0000 = 0000 Max address range 0000 1111 1111 1111 = 0FFF

Slide 21:

Flags and PSW:  Flag:1 –bit storage register.Stores results of certain program instructions.  Other instructions test the condition of flags and make decision accordingly  Four math flag,which responds automatically to outcomes of math operations.C,AC,OV,P  Three general purpose user flags,could be set to 1 or cleared to 0 by programmer.GF0,GF1,F0.  GF0,GF1 stored in PCON

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PSW.7 CY Carry flag. PSW.6 AC Auxiliary Carry flag. (For BCD operations.) PSW.5 F0 Flag 0. (Available to the user for general purposes.) PSW.4 RS1 Register bank select control bit 1. Set/cleared by software to determine working register bank. PSW.3 RS0 Register bank select control bit 0. Set/cleared by software to determine working register bank. PSW.2 OV Overflow flag. PSW.1 User-definable flag. PSW.0 P Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of “one” bits in the Accumulator, i.e., even parity. The contents of (RS1, RS0) enable the working register banks as follows: (0,0)— Bank 0 (00H–07H) (0,1)— Bank 1 (08H–0fH) (1,0)— Bank 2 (10H–17H) (1,1)— Bank 3 (18H–17H) PSW

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Special Function Registers SFRs:  Located from 80h to FFh  Bit and byte addressable Not all of the addresses from 80h to FFh are used for SFRs .  Could be accessed by their name as A,P0 or by their addresses as 0E0,80 respectively

Slide 25:

Microprocessor * CPU is stand-alone, RAM, ROM, I/O, timer are separate * Designer can decide on the amount of ROM, RAM and I/O ports. * General purpose & digital computer Microcontroller * CPU , RAM, ROM, I/O and timer are all on a single chip * Fix amount of on-chip ROM, RAM, I/O ports * Special purpose & digital controller Microprocessor vs. Microcontroller

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Thanks

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