Ngôn Ngữ Thiết Kế

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trình bày về code VHDL của mạch cộng carry ripple adder theo hai cách : map truyền thống và dùng for.

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DESIGN LANGUGE : TRAN XUAN TANAUTHOR: NGUYEN PHUOC LOC : 

DESIGN LANGUGE : TRAN XUAN TANAUTHOR: NGUYEN PHUOC LOC

FULL CARRY ADDER 16BIT : 

FULL CARRY ADDER 16BIT Báo Cáo Đề Tài Cuối Kì

OUTLINE : 

OUTLINE INTRODUCTION. FULL CARRY ADDER 16BIT. SIMULATION. 3 DESIGN LANGUAGE

INTRUDUCTION : 

INTRUDUCTION ADDER BINARY. CARRY ADDER & CARRY LOOK AHEAD ADDER. 4 DESIGN LANGUAGE

OUTLINE : 

OUTLINE INTRODUCTION. FULL CARRY ADDER 16BIT. SIMULATION. 5 DESIGN LANGUAGE

FULL CARRY ADDER 16BIT : 

FULL CARRY ADDER 16BIT TRUST TABLE ADDER 1 BIT. 6 DESIGN LANGUAGE

FULL CARRY ADDER 16BIT : 

FULL CARRY ADDER 16BIT OPTIMIZATION USE K-NAUGHT. DESIGN LANGUAGE 7 S = A ^ B ^ Cin Cout = A.B + B.Cin + A.Cin = A.B + (A^B).Cin

FA : 

FA DESIGN LANGUAGE 8 A B Cin Cout S library ieee; use ieee.std_logic_1164.all; entity and2 is port (a ,b : in std_logic ; x : out std_logic ); end and2; architecture and2behave of and2 is begin x <= a and b ; end; library ieee; use ieee.std_logic_1164.all; entity xor2 is port (a ,b : in std_logic ; x : out std_logic ); end xor2; architecture xor2behave of xor2 is begin x <= ((not a) and b) or ((not b) and a) ; end; library ieee; use ieee.std_logic_1164.all; entity or2 is port (a ,b : in std_logic ; x : out std_logic ); end or2; architecture or2behave of or2 is begin x <= a or b ; end;

OUTLINE : 

OUTLINE INTRODUCTION. FULL CARRY ADDER 16BIT. SIMULATION. 9 DESIGN LANGUAGE

SIMULATION : 

SIMULATION CODE FA1BIT: DESIGN LANGUAGE 10 library ieee; use ieee.std_logic_1164.all; entity fulladder1bit is port (a,b,cin : in std_logic ; x ,cout : out std_logic ); end fulladder1bit; architecture fulladder1bit_behave of fulladder1bit is component and2 port (a,b : in std_logic ; x : out std_logic ); end component; component xor2 port (a,b : in std_logic ; x : out std_logic ); end component; component or2 port (a,b : in std_logic ; x : out std_logic); end component; signal axorb : std_logic ; signal aandb : std_logic ; signal c1 :std_logic ; begin U1 : xor2 port map (a => a, b => b, x => axorb); U2 : xor2 port map (a => cin, b => axorb, x => x); U3 : and2 port map (a => a, b => b, x => aandb); U4 : and2 port map (a => cin, b => axorb, x => c1); U5 : or2 port map (a => aandb, b => c1, x => cout); end;

SCHEMATIC FA : 

FA1 FA1 FA1 Cin Cout S0 S14 S15 A0 B0 A14 B14 A15 B15 SCHEMATIC FA DESIGN LANGUAGE 11

SIMULATION : 

SIMULATION CODE FA16BIT PORT MAP 16 FA1BIT: U3 : fulladder1bit port map (a => a(3) , b => b(3) , cin => cout2 , x => x(3) , cout => cout3 ); U4 : fulladder1bit port map (a => a(4) , b => b(4) , cin => cout3 , x => x(4) , cout => cout4 ); U5 : fulladder1bit port map (a => a(5) , b => b(5) , cin => cout4 , x => x(5) , cout => cout5 ); U6 : fulladder1bit port map (a => a(6) , b => b(6) , cin => cout5 , x => x(6) , cout => cout6 ); U7 : fulladder1bit port map (a => a(7) , b => b(7) , cin => cout6 , x => x(7) , cout => cout7 ); U8 : fulladder1bit port map (a => a(8) , b => b(8) , cin => cout7 , x => x(8) , cout => cout8 ); U9 : fulladder1bit port map (a => a(9) , b => b(9) , cin => cout8 , x => x(9) , cout => cout9 ); U10 : fulladder1bit port map (a => a(10) , b => b(10) , cin => cout9 , x => x(10) , cout => cout10 ); U11 : fulladder1bit port map (a => a(11) , b => b(11) , cin => cout10 , x => x(11) , cout => cout11 ); U12 : fulladder1bit port map (a => a(12) , b => b(12) , cin => cout11 , x => x(12) , cout => cout12 ); U13 : fulladder1bit port map (a => a(13) , b => b(13) , cin => cout12 , x => x(13) , cout => cout13 ); U14 : fulladder1bit port map (a => a(14) , b => b(14) , cin => cout13 , x => x(14) , cout => cout14 ); U15 : fulladder1bit port map (a => a(15) , b => b(15) , cin => cout14 , x => x(15) , cout => cout ); end; DESIGN LANGUAGE 12 library ieee; use ieee.std_logic_1164.all; use work.datatype.all; entity fulladder16bitport is port (a : in data16bit ; b : in data16bit ; cin : in std_logic ; x : out data16bit ; cout : out std_logic ); end fulladder16bitport ; architecture fulladder16bitport_behave of fulladder16bitport is component fulladder1bit port (a,b,cin : in std_logic ; x,cout : out std_logic ); end component ; signal cout0,cout1,cout2,cout3 : std_logic ; signal cout4,cout5,cout6,cout7 : std_logic ; signal cout8,cout9,cout10,cout11 : std_logic ; signal cout12,cout13,cout14 : std_logic ; begin U0 : fulladder1bit port map (a => a(0) , b => b(0) , cin => cin , x => x(0) , cout => cout0); U1 : fulladder1bit port map (a => a(1) , b => b(1) , cin => cout0 , x => x(1) , cout => cout1); U2 : fulladder1bit port map (a => a(2) , b => b(2) , cin => cout1 , x => x(2) , cout => cout2);

Testbench_FA_PORT_MAP : 

Testbench_FA_PORT_MAP DESIGN LANGUAGE 13 library ieee; use ieee.std_logic_1164.all; use work.datatype.all; entity tb_adder_port_map_truyen_thong is end tb_adder_port_map_truyen_thong; architecture tb_adder_port_map_truyen_thong_behave of tb_adder_port_map_truyen_thong is component fulladder16bitport port (a : in data16bit ; b : in data16bit ; cin : in std_logic ; x : out data16bit ; cout : out std_logic ); end component ; signal a : data16bit := "1111111111111111" ; signal b : data16bit := "0000000000000001" ; signal cin : std_logic := '0' ; signal x : data16bit ; signal cout: std_logic ; begin behave : fulladder16bitport port map(a=>a,b=>b,cin=>cin,x=>x,cout=>cout); process (a,b,cin) begin a(2) <= not a(3) after 100 ns; end process; end;

WAREFORM_PORT_MAP : 

WAREFORM_PORT_MAP DESIGN LANGUAGE 14

SIMULATION : 

SIMULATION FA16BIT_FOR_PORT_MAP: DESIGN LANGUAGE 15 library ieee; use ieee.std_logic_1164.all; use work.datatype.all; entity fulladder16bit_for is port (a : in data16bit ;b: in data16bit ; cin: in std_logic ; x : out data16bit ; cout : out std_logic ); end fulladder16bit_for ; architecture fulladder16bit_for_behave of fulladder16bit_for is component fulladder1bit port (a,b,cin : in std_logic ; x ,cout : out std_logic ); end component ; signal cout0 : data17bit ; begin cout0(0) <= cin; G1 : for i in 0 to 3 generate U0 : fulladder1bit port map (a => a(4*i) , b => b(4*i) , cin => cout0(4*i) , x => x(4*i ) , cout => cout0(4*i+1) ); U1 : fulladder1bit port map (a => a(4*i+1) , b => b(4*i+1) , cin => cout0(4*i+1) , x => x(4*i+1) , cout => cout0(4*i+2) ); U2 : fulladder1bit port map (a => a(4*i+2) , b => b(4*i+2) , cin => cout0(4*i+2) , x => x(4*i+2) , cout => cout0(4*i+3) ); U3 : fulladder1bit port map (a => a(4*i+3) , b => b(4*i+3) , cin => cout0(4*i+3) , x => x(4*i+3) , cout => cout0(4*i+4) ); end generate; cout <= cout0(16); end;

Testbench_FA_FOR : 

Testbench_FA_FOR DESIGN LANGUAGE 16 library ieee; use ieee.std_logic_1164.all; use work.datatype.all; entity tb_adder is end tb_adder; architecture tb_adder_behave of tb_adder is component fulladder16bit_for port (a : in data16bit ;b: in data16bit ; cin: in std_logic ; x : out data16bit ; cout : out std_logic ); end component ; signal a : data16bit := "1111111111111111" ; signal b : data16bit := "0000000000000001" ; signal cin : std_logic := '0' ; signal x : data16bit ; signal cout: std_logic ; begin behave : fulladder16bit_for port map(a,b,cin,x,cout); process (a,b,cin) begin a(3) <= not a(3) after 300 ns; end process; end;

WAREFORM_FA_FOR : 

WAREFORM_FA_FOR DESIGN LANGUAGE 17