flip flop

Views:
 
Category: Education
     
 

Presentation Description

bistable

Comments

Presentation Transcript

FLIP FLOPS AND TIMING CIRCUITS:

FLIP FLOPS AND TIMING CIRCUITS By: Isha Dhawan

INTRODUCTION:

INTRODUCTION Switching circuits can be combinational or sequential switching circuits Combinational switching circuits : Output only depends on the levels of input present at that time No memory EX: AND gate, OR gate, NAND gate ,ADDER, SUBTRACTOR etc

SEQUENTIAL CIRCUITS:

SEQUENTIAL CIRCUITS Sequential switching circuits : Output depends not only on the present input but also on the previous input level conditions Made of combinational switching circuits and memory Ex: Flip flop, Shift Register, Counter etc

FLIP FLOP:

FLIP FLOP Flip flop is a bistable multivibrator that has two stable states 0 and 1 It can remain in either of these two stated indefinitely General Flip Flop symbol

FLIP FLOP SYMBOL:

FLIP FLOP SYMBOL Q output is the normal output of flip flop and Q’ output is the inverted output The state of the flip flop refers to the state of the normal output A flip flop is said to be in HIGH STATE or LOGIC1 STATE or SET STATE when Q=1 LOW STATE or LOGIC 0 STATE or RESET STATE or CLEAR STATE when Q=0

FLIP FLOP:

FLIP FLOP Flip flop is a storage device Flip flop stores 1 when Q=1 Flip flop stores 0 when Q=0

WHAT IS A LATCH:

WHAT IS A LATCH There are two types of latches: Asynchronous latches Output can change the state any time the input conditions are changed Synchronous latches/Gated latches/clocked latches Requires an Enable input. Enable can be a clock The input controls the state of flip flop only when Enable input is high The input becomes ineffective when clock is low These flip flops are called level triggered flip flops .

SR LATCH:

SR LATCH The simplest type of latch is SR latch AN SR Latch can be constructed using two cross coupled NOR gates or NAND GATES LOGIC SYMBOL

NOR GATE S-R LATCH:

NOR GATE S-R LATCH S (set) R (reset) Q Q Logic diagram of ACTIVE-HIGH SR LATCH using NOR gates

NOR GATE S-R LATCH:

NOR GATE S-R LATCH A B Y 0 0 1 0 1 0 1 0 0 1 1 0 NOR GATE TRUTH TABLE 0 0 Suppose Q0 represents the state of the flip flop before applying the inputs. Let Q0=0 and Q0’=1 we have Q=0 and Q’=1 Let Q0=1 and Q0’=0 we have Q=1 and Q’=0 Logic diagram of ACTIVE-HIGH SR LATCH using NOR gates

NOR GATE S-R LATCH:

NOR GATE S-R LATCH A B Y 0 0 1 0 1 0 1 0 0 1 1 0 NOR GATE TRUTH TABLE 0 1 Logic diagram of ACTIVE-HIGH SR LATCH using NOR gates Suppose Q0 represents the state of the flip flop before applying the inputs. Let Q0=0 and Q0’=1 we have Q=1 and Q’=0 Let Q0=1 and Q0’=0 we have Q=1 and Q’=0

NOR GATE S-R LATCH:

NOR GATE S-R LATCH A B Y 0 0 1 0 1 0 1 0 0 1 1 0 NOR GATE TRUTH TABLE 1 0 Logic diagram of ACTIVE-HIGH SR LATCH using NOR gates Suppose Q0 represents the state of the flip flop before applying the inputs. Let Q0=0 and Q0’=1 we have Q=0 and Q’=1 Let Q0=1 and Q0’=0 we have Q=0 and Q’=1

NOR GATE S-R LATCH:

NOR GATE S-R LATCH A B Y 0 0 1 0 1 0 1 0 0 1 1 0 NOR GATE TRUTH TABLE 1 1 Logic diagram of ACTIVE-HIGH SR LATCH using NOR gates Suppose Q0 represents the state of the flip flop before applying the inputs. Let Q0=0 and Q0’=1, Output will be invalid or undefined state Let Q0=1 and Q0’=0, Output will be invalid or undefined state

TRUTH TABLE OF ACTIVE HIGH SR LATCH:

TRUTH TABLE OF ACTIVE HIGH SR LATCH S R Q Comments 0 0 Q0 No change 0 1 0 RESET 1 0 1 SET 1 1 ? Not allowed

ACTIVE LOW NAND GATE SR LATCH:

ACTIVE LOW NAND GATE SR LATCH Logic diagram of ACTIVE-LOW SR LATCH using NAND gates

TRUTH TABLE OF ACTIVE LOW SR LATCH:

TRUTH TABLE OF ACTIVE LOW SR LATCH S R Q Comments 0 0 ? Not allowed 0 1 1 SET 1 0 0 RESET 1 1 Q0 No change

ACTIVE HIGH NAND GATE SR LATCH:

ACTIVE HIGH NAND GATE SR LATCH Logic diagram of ACTIVE-HIGH SR LATCH using NAND gates

TRUTH TABLE OF ACTIVE HIGH SR LATCH:

TRUTH TABLE OF ACTIVE HIGH SR LATCH S R Q Comments 0 0 Q0 No change 0 1 0 RESET 1 0 1 SET 1 1 ? No t allowed

GATED SR LATCH:

GATED SR LATCH LOGIC DIAGRAM Gated SR latch is an example of synchronous latch. Gated SR latch is sensitive to changes in input as long as EN=1

TRUTH TABLE OF GATED SR LATCH:

TRUTH TABLE OF GATED SR LATCH S R ENABLE (EN) Q Comments 0 0 HIGH Q0 No change 0 1 HIGH 0 RESET 1 0 HIGH 1 SET 1 1 HIGH ? No t allowed LOGIC SYMBOL

GATED D LATCH:

GATED D LATCH D Latch is constructed from the SR latch using a single input S and R is obtained by inverting the S input or R=S’ The single input is labeled as D

GATED D LATCH:

GATED D LATCH WHEN D=1, we have S=1 and R=0, thus LATCH is SET when ENABLED WHEN D=0, we have S=0 and R=1, thus LATCH is RESET when enabled

TRUTH TABLE OF GATED D LATCH:

TRUTH TABLE OF GATED D LATCH LOGIC SYMBOL Output Q follows the D input when ENABLE is high

EDGE TRIGGERED FLIP FLOP:

EDGE TRIGGERED FLIP FLOP There are two