Lecture 6 Logic gates : Power and Other Logic Family: Lecture 6 Logic gates : Power and Other Logic Family ENG.AMGAD YOUNIS
[email protected] Department of Electronics Faculty of Engineering Helwan University
Acknowledgement: April 29, 2013 204424 Digital Design Automation 2 Acknowledgement This lecture note has been summarized from lecture note on Introduction to VLSI Design, VLSI Circuit Design all over the world. I can’t remember where those slide come from. However, I’d like to thank all professors who create such a good work on those lecture notes. Without those lectures, this slide can’t be finished.
Parasitics and Performance: April 29, 2013 204424 Digital Design Automation 3 Parasitics and Performance Consider the following layout: What is the impact on performance of parasitics At point a (VDD rail)? At point b (input)? At Point c (output)? b a c
Parasitics and Performance: April 29, 2013 204424 Digital Design Automation 4 Parasitics and Performance a - power supply connections capacitance - no effect on delay resistance - increases delay (see p. 135) minimize by reducing difffusion length minimize using parallel vias b a c
Parasitics and Performance: April 29, 2013 204424 Digital Design Automation 5 Parasitics and Performance b - gate input capacitance increases delay on previous stage (often transistor gates dominate) resistance increases delay on previous stage b a c
Parasitics and Performance: April 29, 2013 204424 Digital Design Automation 6 Parasitics and Performance c - gate output resistance, capacitance increase delay Resistance & capacitance "near" to output causes additional delay b a c
Driving Large Loads: April 29, 2013 204424 Digital Design Automation 7 Driving Large Loads Off-chip loads, long wires, etc. have high capacitance Increasing transistor size increases driving ability (and speed), but in turn increases gate capacitance Solution: stages of progressively larger transistors Use n opt = ln(C big /C g ). Scale by a factor of a = e
Summary: Static CMOS: April 29, 2013 204424 Digital Design Automation 8 Summary: Static CMOS Advantages High Noise Margins (V OH =V DD , V OL =Gnd) No static power consumption (except for leakage) Comparable rise and fall times (with proper sizing) Robust and easy to use Disadvantages Large transistor counts (2N transistors for N inputs) Larger area More parasitic loading (2 transistor gates on each input) Pullup issues Lower driving capability of P transistors Series connections especially problematic Sizing helps, but increases loading on gate inputs
Alternatives to Static CMOS: April 29, 2013 204424 Digital Design Automation 9 Alternatives to Static CMOS Switch Logic nmos Pseudo-nmos Dynamic Logic Low-Power Gates
Switch Logic: April 29, 2013 204424 Digital Design Automation 10 Switch Logic Key idea: use transistors as switches Concern: switches are bidirectional AND OR
Switch Logic - Pass Transistors: April 29, 2013 204424 Digital Design Automation 11 Switch Logic - Pass Transistors Use n-transistor as “switches” “Threshold problem” Transistor switches off when V gs < V t V DD input -> V DD -V t output Special gate needed to “restore” values IN: V DD A: V DD OUT: V DD -V tn
Switch Logic - Transmission Gates: April 29, 2013 204424 Digital Design Automation 12 Switch Logic - Transmission Gates Complementary transistors - n and p No threshold problem Cost: extra transistor, extra control input Not a perfect conductor! A A’ A A’
Switch Logic Example - 2-1 MUX: April 29, 2013 204424 Digital Design Automation 13 Switch Logic Example - 2-1 MUX IN
Charge Sharing: April 29, 2013 204424 Digital Design Automation 14 Charge Sharing Consider transmission gates in series Each node has parasitic capacitances Problems occur when inputs change to redistribute charge Solution: design network so there is always a path from V DD or Gnd to output
Aside: Transmission Gates in Analog: April 29, 2013 204424 Digital Design Automation 15 Aside: Transmission Gates in Analog Transmission Gates work with analog values, too! Example: Voltage-Scaling D/A Converter
NMOS Logic: April 29, 2013 204424 Digital Design Automation 16 NMOS Logic Used before CMOS was widely available Uses only n transistors Normal n transistors in pull-down network depletion-mode n transistor (V t < 0) used for pull-up "ratioed logic" required Tradeoffs: Simpler processing Smaller gates higher power! Additional design considerations for ratioed logic Passive Pullup Device: depletion Mode n-transistor (V t < 0) OUT Pulldown Network
Pseudo-nmos Logic: April 29, 2013 204424 Digital Design Automation 17 Pseudo-nmos Logic Same idea, as nmos, but use p-transistor for pullup "ratioed logic" required for proper design (more about this next) Tradeoffs: Fewer transistors -> smaller gates, esp. for large number of inputs less capacitative load on gates that drive inputs larger power consumption less noise margin (V OL > 0) additional design considerations due to ratioed logic Passive Pullup Device: P-Transistor OUT Pulldown Network
Ratioed Logic for Pseudo-nmos: April 29, 2013 204424 Digital Design Automation 18 Ratioed Logic for Pseudo-nmos Approach: Assume V OUT =V OL =0.25*V DD Assume 1 pulldown transistor is on Equate currents in p, n transistors Solve for ratio between sizes of p, n transistors to get these conditions Further calculations necessary for series connections I dp OUT Pulldown Network I dn
DCVS Logic: April 29, 2013 204424 Digital Design Automation 19 DCVS Logic DCVS - Differential Cascode Voltage Switch Differential inputs, outputs Two pulldown networks Tradeoffs Lower capacitative loading than static CMOS No ratioed logic needed Low static power consumption More transistors More signals to route between gates Example: Fig. 3.29 p. 148 OUT Pulldown Network OUT’ OUT’ Pulldown Network OUT A B C A’ B’ C’
Dynamic Logic: April 29, 2013 204424 Digital Design Automation 20 Pulldown Network C S f f A B C Dynamic Logic Key idea: Two-step operation precharge - charge C S to logic high evaluate - conditionally discharge C S Control - precharge clock f Storage Node Storage Capacitance Precharge Signal Precharge Evaluate Precharge
Domino Logic: April 29, 2013 204424 Digital Design Automation 21 Domino Logic Key idea: dynamic gate + inverter Cascaded gates - “monotonically increasing” Pulldown Network C S f f B C f in4 x1 x2 x3
Domino Logic Tradeoffs: April 29, 2013 204424 Digital Design Automation 22 Domino Logic Tradeoffs Fewer transistors -> smaller gates Lower power consumption than pseudo-nmos Clocking required Logic not complete (AND, OR, but no NOT)
More Techniques for Saving Power: April 29, 2013 204424 Digital Design Automation 23 More Techniques for Saving Power Reduce VDD (tradeoff: delay) Multiple Power Supplies High VDD for “fast” logic Low VDD for “slow” logic (level translation an issue) DCSL - Fig. 3-35, p. 155 cross-coupled outputs partially disconnected pulldown network Dealing with leakage currents (p. 158) Multiple-Threshold CMOS (MTCMOS) - Fig 3-37 Variable-Threshold CMOS (VTCMOS) - Fig 3-38
Delay in Long Wires - Lumped RC Model: April 29, 2013 204424 Digital Design Automation 24 Delay in Long Wires - Lumped RC Model What is the delay in a long wire? Lumped RC Model: Delay time constant (ignoring driving gate) t = R * C = (R s * L / W) * (L * W * C plate ) = r * c * L 2 Problem: Overly Pessimistic R = R s * L / W = r*L (r = R s / W - resistance per unit length ) C = L * W * C plate = c*L (c = W * C plate - capacitance per unit length)
Delay in Long Wires - Distributed RC Model: April 29, 2013 204424 Digital Design Automation 25 Delay in Long Wires - Distributed RC Model Alternative: Break wire into small segments Approx. Solution - 1st moment of impulse response Important: delay still grows as square of length
Delay in Long Wires - Consequences in design: April 29, 2013 204424 Digital Design Automation 26 Delay in Long Wires - Consequences in design Distributed RC model: Delay grows as square of L! Choose wire material that minimizes r, c Break wire into buffered segments to optimize delay
Elmore Delay: April 29, 2013 204424 Digital Design Automation 27 Elmore Delay Consider R-C ladder network with unequal values First-order time constant at node N is First-order time constant and node I is
Elmore Delay Applications: April 29, 2013 204424 Digital Design Automation 28 Elmore Delay Applications Wire sizing to minimize delay Delay prediction of complex networks (as long as they take the form of a ladder)
Elmore Delay Homework Problem: April 29, 2013 204424 Digital Design Automation 29 Elmore Delay Homework Problem What are the Elmore time constants t 1 , t 2 , t 3 ?
Wire Sizing: April 29, 2013 204424 Digital Design Automation 30 Wire Sizing Recall distributed model of wire: multiple segments note strong impact of R 1 , lesser impact of R 2 , etc Idea: Reduce overall delay by tapering segments Make Segment 1 widest to reduce R1 (increases C1) Make Segment 2 less wide to reduce R2 (increses C2) etc.
Wire Sizing: April 29, 2013 204424 Digital Design Automation 31 Wire Sizing Ideal Result wire should taper exponentially - see Eq. 3-20, p. 163 [Fis95]: More pragmatic approach: step-tapered wire [Fis95] J. Fishburn and C. Schevon, “Shaping a distributed-RC line to minimize Elmore delay”, IEEE Trans. on Circuits and Systems-I , December 1995, pp. 1020-1022
Buffer Insertion: April 29, 2013 204424 Digital Design Automation 32 Buffer Insertion Key Idea: Break long wire up into stages (Sec. 3.7.3) Equivalent Circuit: Fig. 3-44, p. 167 50% delay of each segment: Eq 3-35 Number of stages for minimum delay: Eq 3-36 Best size and number of stages: Eq 3-38 - 3-39 in out
Wire Sizing - New Results: April 29, 2013 204424 Digital Design Automation 33 Wire Sizing - New Results Alternative approach [Alpert01]: Combine buffer insertion and Untapered wires of (small number of) different widths Theoretical result: Tapering gives at best 3.5% improvement over this approach Practical result: tapering generally not worthwhile [Alpert01] “Interconnect Synthesis without wire tapering”, IEEE Trans. CAD , Vol. 20, No. 1, January 2001, pp. 90-104
Delay in RC-Trees: April 29, 2013 204424 Digital Design Automation 34 Delay in RC-Trees Many interconnection networks are trees Extracted RC circuit modeling a gate output Clock trees
Delay in RC-Trees: Penfield-Rubenstein Bounds: April 29, 2013 204424 Digital Design Automation 35 Delay in RC-Trees: Penfield-Rubenstein Bounds Key idea: characterize time constants in terms of Path resistances between nodes Capacitance values at each node
Delay in RC-Trees: Penfield-Rubenstein Bounds: April 29, 2013 204424 Digital Design Automation 36 Delay in RC-Trees: Penfield-Rubenstein Bounds Time constants T p , T D o , T R o (eqn. 3-30 - 3-34) Table 3-2 (p. 165) - bounds for time, voltage