Adapters_for_modelin g_abstraction_level_ final

Views:
 
Category: Entertainment
     
 

Presentation Description

No description available.

Comments

Presentation Transcript

Slide 1: 

How to create adaptors for modeling abstraction levels Umesh Sisodia, [email protected] Presenting on behalf of: Ashwani Singh, [email protected]

Agenda : 

Agenda SoC Modeling SoC Modeling Abstraction Levels Requirement of adaptors Role/Functionality of Adaptors Adaptor Modeling Challenges Queries

SoC Modeling : 

SoC Modeling Abstraction required to speedup things -Timing granularity -Data granularity SoC Modeling Behavior Communication Timing

SoC Modeling Abstraction : 

SoC Modeling Abstraction

1. Mixed-Abstraction-Layered System : 

1. Mixed-Abstraction-Layered System • While creating the VP at higher abstraction level, sometime it is necessary to take the pin level RTL model of a specific IP block. These RTL models might be automatically generated by some tool (like Carbon), thus saving the model creation time. • While creating the VP for a specific use case, to speed up things, it may be a good idea to re-use the existing models at other abstraction levels. This will enable to get the platform working quickly, and then models can be replaced one by one with the correct abstraction. • Adaptors and transactors will also be required for HW/SW coverification while using the virtual platform at higher abstraction level along with the advanced RTL verification environment. Requirement of adaptors Master (TL4) Bus (TL4) Verilog RTL IP Transactor (systemC-Verilog) Slave IP3 TL0 Slave IP2 (TL1) Slave IP1 (TL4) Adaptor (TL4-TL0) Adaptor (TL4-TL0) Adaptor (TL4-TL1)

Slide 6: 

Requirement of adaptors 2. Encourages the reusability of code:The separation of computation and communication, allows the reusability of code across abstraction levels. The TL4 model can be used in combination with proper adaptor to work at different abstraction levels. TL4 Model Used for eSW development

Kind of Adaptors : 

Kind of Adaptors Adaptor’s role: Abstract away the timing points (which are phases in TLM2) Abstract away the data members( normal payload/extended) which are not necessary. Adaptor’s role: -Insert the extra timing points( BP/extended phases) - Add more payload data members (using the extensions) DownStream Adaptors UpStream Adaptors

Handling Timing abstraction - addition/deletion of timing points ( phases) : 

Handling Timing abstraction - addition/deletion of timing points ( phases) Adaptor Adaptor Modeling Challenges

Slide 9: 

Handling payload Extensions TL1 master TL3 slave TL1-TL3 adaptor CFG1: It understands signals: A, B, C,E CFG2: It understands signals: A,E Adaptors adds/deletes data extensions into the payload or validates/invalidates payload members depending upon the configuration of master or slave sockets. Adaptor Modeling Challenges…

Handling order of transactions : 

TL4-TL3 adaptor TL3 slave Both the blocking transport calls will wait until the TLM_COMPLETED for respective nb_trasport, adaptor will unblock the appropriate blocking call.TLM2 ordering rules must be respected. TL4 master T1 T2 Handling order of transactions P2 P1 Adaptor Modeling Challenges…

Handling b/nb and nb/b conversion : 

TL3 master1 TL4 slave The adapter should be able to handle concurrent non-blocking transport calls from multiple initiators. It should be able to create threads for respective blocking transport calls. TL3 master2 TL3 master3 P1 P2 P3 Handling b/nb and nb/b conversion Adaptor Modeling Challenges…

Handle Out-of-order/outstanding txns : 

Handle Out-of-order/outstanding txns TL2 master Adaptor TL4 slave Adaptor Modeling Challenges…

Slide 13: 

THANKS Questions?? SoC Modelling Services (SystemC, TLM2.0)‏ [email protected]

authorStream Live Help