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Dr. Y. NARASIMHA MURTHY Ph.D., Sri Saibaba National College (Autonomous) ANANTAPUR-515001-A.P INTRODUCTION TO VHDL & BEHAVIOURAL MODELLING (During the TWO day workshop on VHDL Technology at Loyola Academy , Alwal ,Hyderabad On 7-02-2013)

HDL ? ??:

HDL ? ??


PROLOGUE In early years the digital circuits were designed manually using the techniques such as Boolean expressions , circuit schematics , Karnaugh maps etc .Most of the people used schematic based soft wares like p spice , h spice etc. With the increasing device densities the choice of this traditional methods has become limited. Because it is a known fact that the schematics with more than 600 gates are incomprehensible.


Contd.. So , it is unimaginable to think how many man-years would be required to design the modern chips which contains millions of transistors . It is a must for IC designers to go for some EDA tool. So, the electronic design Automation (EDA) tool made the multimillion IC design simple and possible.


Contd.. With the increasing use of computer –based design methodologies ,the IC design has migrated to EDA tools. One such outcome of these EDA tools is the HDL (Hardware Description Language). This HDL resembles a general programming language like “C’, but is specifically oriented to describing hardware structures and behaviors. The most common use of a HDL is to provide an alternative to schematics

Is HDL so indispensable???:

Is HDL so indispensable??? O.K. Lets discuss it . For illustration , let us design ,a 16 x 16 multiplier with schematic capture and using the HDL. The multiplier is a complex arrangement of adders and registers . In the present case we have two 16 –bit inputs and one 32-bit product output .So , a total of 64 I/O s. Approximately the circuit requires 6000 equivalent gates.


Contd.. So , in the schematic implementation ,all the required gates have to be loaded, positioned on the page , interconnected and I/O buffers should be added . This will take at least 3 days of hard time . But the HDL implementation ,which also need 6000 gates, requires 8-lines of text and can be done happily in 3 minutes . This file will have all the information required to define the 16 x 16 multiplier .

Simple Code:

Simple Code Entity MULT is port (A,B: in std _ logic(15 down to 0); Y:out std_logic (31 down to 0); end MULT; architecture Behav of MULT is begin Y <= A* B; End Behav ;


Contd.. So, the HDL implementation has All the 6000 gates Only 1 text file 3 minutes to write Completely vendor independent .. Do you accept the importance of the using a HDL in digital circuit design ?? ( source : Xilix Website)

Types of HDLs:

Types of HDLs There are two standard HDL s that are supported by IEEE. One is VHDL and the other is Verilog ® HDL which originated in 1983 at Gateway Design Automation Both Verilog and VHDL simulators gained the acceptance of the designers soon to simulate large digital circuits quickly.

WHAT IS VHDL ??....:



Contd.. I think most of the students at the first instance feel like this … But , is it true ??? No !! Not at All

VHDL is an acronym of:

VHDL is an acronym of V : Very High Speed Integrated Circuit H : Hardware D : Description L: Language


Contd … A Language developed to describe the complex digital circuits. It is a C like language that supports wide range of description styles(Structural description, data flow description , behavioral description and mixed description )



Genesis of VHDL:

Genesis of VHDL During 1980s ,the rapid advances in integrated circuit technology provoked the idea of developing a standard design procedure for digital circuits . The VHSIC Program launched in 1980 ,was an initiative of the Defense Department of US to push the state of the art in VLSI technology, and VHDL was proposed as a versatile hardware description language


Contd … Woods Hole Workshop Held in June 1981 in Massachusetts. In July 1983, a team of Intermetrics , IBM and Texas Instruments were awarded a contract to develop VHDL In August 1985, the final version of the language under government contract was released: VHDL Version 7.2


Contd … In December 1987, VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standard In September 1993, VHDL was re standardized to clarify and enhance the language (IEEE Standard 1076-1993) VHDL has been accepted as a Draft International Standard by the IEC (International Engineering Consortium) VHDL 1993, 1997, 2000, 2002 …






SPECIALITIES VHDL allows the designer to work at various level of abstraction: behavioural; RTL; boolean equations and gates.


Contd.. Allows for various design methodologies : top-down, bottom-up, delay of detail. very flexible in its approach to describing hardware. Provides technology independence VHDL is independent of any technology or process (ASIC,FPGA…)




Format VHDL is a “free format” language . No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way. Example: if (a=b) then or if (a=b) then or if (a = b) then are all equivalent


Contd Because VHDL is a standard, VHDL design descriptions are device independent, allowing the designer to easily benchmark design performance in multiple device architectures. The same code used for designing with programmable logic can be used by an ASIC vendor to produce an ASIC when production volumes warrant a conversion.


Contd VHDL is a well suited language for designing with programmable logic, and it is gaining in popularity. Designing with larger capacity CPLDs (complex programmable logic devices)and FPGAs (field programmable gate arrays) of 600 gates to 20K gates. VHDL delivers portability of code between synthesis and simulation tools, device independent design, and easy ASIC migration. VHDL is an open, standard language, not a proprietary language.


VHDL PROGRAMMING Let us now understand the basics of writing a VHDL program for a digital circuit. For this let us consider the Fundamental sections of a basic VHDL code.

Fundamental sections of a basic VHDL code. :

Fundamental sections of a basic VHDL code .


Contd.. Every piece of VHDL code is composed of at least three fundamental sections LIBRARY declarations: Contains a list of all libraries to be used in the design. ENTITY: Specifies the I/O pins of the circuit. ARCHITECTURE: Contains the VHDL code which describes how the circuit should behave (function).


A VHDL code for the full adder Full-adder Schematic Simulation results from the VHDL design Example code - VHDL


LIBRARY A LIBRARY is a collection of commonly used pieces of code. Placing such pieces inside a library allows them to be reused or shared by other designs. The typical structure of a library is shown aside.

Library Declarations :

Library Declarations To declare a LIBRARY (that is, to make it visible to the design) two lines of code are needed, one containing the name of the library, and the other a use clause. The syntax is as follows LIBRARY library_name ; USE library_name.package_name.package_parts ;


Contd.. At least three packages, from three different libraries, are usually needed in a design : ieee.std_logic_1164(from the ieee library), standard (from the std library) , and work (work library)

Library Declarations:

Library Declarations LIBRARY ieee; -- A semi-colon (;) indicates the end of a statement or a declaration USE ieee.std_logic_1164.all ; LIBRARY std ; - a double dash (--) indicates a comment. USE std . Standard . all ; LIBRARY work ; USE work. all;


Contd.. The std_logic_1164 package of the ieee library specifies a multi-level logic system; std is a resource library (data types, text i/o, etc.) for the VHDL design environment; and the work library is where we save our design (the .vhd file, plus all files created by the compiler, simulator, etc.).

STD_LOGIC type :

STD_LOGIC type Value Meaning ‘U’ Uninitialized ‘X’ Forcing (Strong driven) Unknown ‘0’ Forcing (Strong driven) 0 ‘1’ Forcing (Strong driven) 1 ‘Z’ High Impedance ‘W’ Weak (Weakly driven) Unknown ‘L’ Weak (Weakly driven) 0. Models a pull down. ‘H’ Weak (Weakly driven) 1. Models a pull up. ‘-’ Don't Care


ENTITY An ENTITY is a list with specifications of all input and output pins (PORTS) of the circuit with the following syntax. ENTITY entity_name IS PORT ( port_ name : signal_mode signal_type ; port_ name : signal_mode signal_type ; ... ); END entity_name ;


Contd.. The mode of the signal can be IN, OUT, INOUT, or BUFFER . IN and OUT are truly unidirectional pins, while INOUT is bidirectional. BUFFER, on the other hand, is employed when the output signal must be used (read) internally. The name of the entity can be basically any name, except VHDL reserved words

Example Entity:

Example Entity ENTITY nand_ gate IS PORT (a, b : IN BIT; x : OUT BIT); END nand_gate;


ARCHITECTURE The ARCHITECTURE denotes the description of how the circuit should behave or function . The syntax is as below. ARCHITECTURE architecture_name OF entity_name IS [declarations] BEGIN (code) END architecture_name ;


Contd.. So, an architecture has two parts : a declarative part (optional), where signals and constants (among others) are declared, and the code part (from BEGIN down).

Example -Architecture:

Example -Architecture ARCHITECTURE my arch OF nand_ gate IS BEGIN x <= a NAND b; END my arch; The meaning of the ARCHITECTUREt is that the circuit must perform the NAND operation between the two input signals (a, b) and assign (‘‘<=’’) the result to the output pin (x). The name chosen for this architecture was myarch. In this example, there is no declarative part, and the code contains just a single assignment.


Contd.. It is a known fact that the VHDL representation is a text file describing a digital system, the digital system can be represented in different levels of abstractions such as a behavioral model or a structural model or a mixed model. These levels of abstraction help the designer to develop any complex digital system efficiently.


Contd.. Behavioral level describes the system, the way it behaves and describes the relationship between the input and output signals. The description can be a Register Transfer Level (RTL) or Algorithmic (set of instruction) or simple Boolean equations.


Contd.. RTL typically represents data flow within the systems like data flow between registers. RTL is mostly used for design of combinational logics. In the algorithmic level , specific instruction set of statements define the sequence of operations in the system.


Contd.. Algorithmic level is mostly used for design of sequential logics. The Structural level describes the digital system as gates or as component blocks interconnected to perform the desired operations. Structural level is primarily the graphical representation of the digital system and so it is closer to the actual physical representation of the system.

Concurrent versus Sequential:

Concurrent versus Sequential VHDL code is inherently concurrent (parallel). Only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are sequential. Though within these blocks the execution is sequential, the block, as a whole, is concurrent with any other (external) statements. Concurrent code is also called data flow code.

Concurrent code:

Concurrent code In concurrent code the following can be used : Operators The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN) The GENERATE statement The BLOCK statement.




Multiplexer LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mux IS PORT ( a, b, c, d, s0, s1: IN STD_LOGIC; y : OUT STD_LOGIC); END mux; ARCHITECTURE pure_logic OF mux IS BEGIN y <= (a AND NOT s1 AND NOT s0) OR (b AND NOT s1 AND s0) OR (c AND s1 AND NOT s0) OR (d AND s1 AND s0); END pure_logic;

WHEN (Simple and Selected):

WHEN (Simple and Selected) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mux IS PORT ( a, b, c, d: IN STD_LOGIC; sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0); y: OUT STD_LOGIC); END mux; ARCHITECTURE mux1 OF mux IS BEGIN y <= a WHEN sel = "00" ELSE b WHEN sel= "01" ELSE c WHEN sel="10" ELSE d ; 17 END mux1;


Alternative LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mux IS PORT ( a, b, c, d: IN STD_LOGIC; sel: IN INTEGER RANGE 0 TO 3; y: OUT STD_LOGIC); END mux; ARCHITECTURE mux1 OF mux IS BEGIN y <= a WHEN sel= 0 ELSE b WHEN sel=1 ELSE c WHEN sel=2 ELSE d; END mux1 ;

Tri-state Buffer:

Tri-state Buffer LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY tri_state IS PORT ( ena: IN STD_LOGIC; input: IN STD_LOGIC_VECTOR (7 DOWNTO 0); output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END tri_state; ARCHITECTURE tri_state OF tri_state IS BEGIN output <= input WHEN (ena='0') ELSE (OTHERS => 'Z'); END tri_state;

Sequential Code:

Sequential Code PROCESSES,FUNCTIONS, and PROCEDURES are the only sections of code that are executed sequentially . One important aspect of sequential code is that it is not limited to sequential logic. With it we can build sequential circuits as well as combinational circuits. Sequential code is also called behavioral code.

Sequential Statements:

Sequential Statements


PROCESS A PROCESS is a sequential section of VHDL code. It is characterized by the presence of IF, WAIT, CASE, or LOOP, and by a sensitivity list (except when WAIT is used). A PROCESS must be installed in the main code, and is executed every time a signal in the sensitivity list changes (or the condition related to WAIT is fulfilled).


Syntax PROCESS (sensitivity list) [VARIABLE name type [range] [:= initial_value;]] BEGIN (sequential code) END PROCESS [label];

D-type flip-flop:

D-type flip-flop LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY dff IS PORT (d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC); END dff; ARCHITECTURE behavior OF dff IS BEGIN PROCESS (clk, rst) BEGIN IF (rst='1') THEN q <= '0'; ELSIF (clk‘ EVENT AND clk='1') THEN q <= d; END IF; END PROCESS; END behavior;


DFF- ALTERNATIVE LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY dff IS PORT (d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC); END dff; ARCHITECTURE dff OF dff IS BEGIN PROCESS BEGIN WAIT ON rst, clk; IF (rst='1') THEN q <= '0'; ELSIF (clk'EVENT AND clk='1') THEN q <= d; END IF; END PROCESS; END dff;


CASE CASE is another statement intended exclusively for sequential code. CASE identifier IS WHEN value => assignments ; WHEN value => assignments ; ... END CASE;

Example :

Example CASE control IS WHEN "00" => x<=a; y<=b; WHEN "01" => x<=b; y<=c; WHEN OTHERS => x<="0000"; y<="ZZZZ“ ; END CASE;


VHDL- CODE LIBRARY ieee; USE ieee.std_logic_1164.all; STD_LOGIC ENTITY dff IS PORT (d, clk, rst: IN BIT; q: OUT BIT); END dff; ARCHITECTURE dff3 OF dff IS BEGIN WHEN '1' => q<='0'; WHEN '0' => IF (clk'EVENT AND clk='1') THEN q <= d; END IF; WHEN OTHERS => NULL; END CASE; END PROCESS; END dff3; PROCESS (clk, rst) BEGIN CASE rst IS


Conclusions Design entry is more efficient at the behavioral level than at the register transfer level for a number of reasons. The behavioral model flows from the original algorithm specification; thus, model generation is a less complex and faster process than RTL model generation. In addition, changes in the algorithm are also easier to incorporate in a behavioral model.


Contd.. The Behavioral VHDL module describes features of the language that describe the behavior of components in response to signals. Behavioral descriptions of hardware utilize software engineering practices and constructs to achieve a functional model. Timing information is not necessary in a behavioral description, although such information may be included easily.


REFERENCES During the preparation of this lecture I have collected the information from many books and resources. The following is the list books and resources ,which inspired me and helped me to overcome my ignorance to some extent . 1. Circuit Design with VHDL- Volnei A. Pedroni, the finest resource which no learner can hardly miss.


Contd… 2.Fundamentals of Digital Logic with VHDL design –Stephen Brown. Most elaborately written book. 3.Digital Design with VHDL –Benjamin Abramov 4.VHDL Tutorial –Peter J.Ashenden. 6. Principles of Modern Digital Design - Parag K. Lala.

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