Layout and stick diagram

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CMOS Layers: 

Jhon P. U CMOS Layers n-well process p-well process Twin-tub process

n-well process: 

Jhon P. U n-well process p-substrate n+ n+ n+ n+ p+ p+ p+ p+ n-well Gate NMOS NMOS PMOS PMOS FOX MOSFET Layers in an n-well process

Layer Types: 

Jhon P. U Layer Types p-substrate n-well n+ p+ Gate oxide Gate (polycilicon) Field Oxide Insulated glass Provide electrical isolation

Top view of the FET pattern: 

Jhon P. U Top view of the FET pattern n+ n+ n+ n+ p+ p+ p+ p+ NMOS NMOS PMOS PMOS n-well

Metal Interconnect Layers: 

Jhon P. U Metal Interconnect Layers Metal layers are electrically isolated from each other Electrical contact between adjacent conducting layers requires contact cuts and vias

Metal Interconnect Layers: 

Jhon P. U Metal Interconnect Layers p-substrate n+ n+ n+ n+ Via Active contact Ox3 Metal2 Metal1 Ox2 Ox1

Interconnect Layout Example: 

Jhon P. U Interconnect Layout Example Metal2 Metal1 Metal1 Active contact Gate contact MOS

Designing MOS Arrays: 

Jhon P. U Designing MOS Arrays A B C y x y x A B C

Parallel Connected MOS Patterning: 

Jhon P. U Parallel Connected MOS Patterning x y A B X X X A B x y

Alternate Layout Strategy: 

Jhon P. U Alternate Layout Strategy A B x y X X X X x A B y

Basic Gate Design: 

Jhon P. U Basic Gate Design Both the power supply and ground are routed using the Metal layer n+ and p+ regions are denoted using the same fill pattern. The only difference is the n-well Contacts are needed from Metal to n+ or p+

The CMOS NOT Gate: 

Jhon P. U The CMOS NOT Gate X X X X Vp Gnd Gnd n-well Vp Contact Cut

Alternate Layout of NOT Gate: 

Jhon P. U Alternate Layout of NOT Gate Gnd Vp X Vp Gnd X X X

NAND2 Layout: 

Jhon P. U NAND2 Layout Gnd Vp X Vp Gnd X X X X

NOR2 Layout: 

Jhon P. U NOR2 Layout Gnd Vp X Vp Gnd X X X X

NAND2-NOR2 Comparison: 

Jhon P. U NAND2-NOR2 Comparison X Vp Gnd X X X X X X X X X Vp Gnd MOS Layout Wiring

General Layout Geometry: 

Jhon P. U General Layout Geometry Individual Transistors Shared Gates Shared drain/ source Vp Gnd

Graph Theory: Euler Path: 

Jhon P. U Graph Theory: Euler Path Vp Gnd a c b b a c Out x y x y Vertex Edge Vertex

Slide 19: 

Jhon P. U Stick Diagram

Slide 20: 

Jhon P. U Stick Diagrams Cartoon of a layout. Shows all components. Does not show exact placement, transistor sizes, wire lengths, wire widths, boundaries, or any other form of compliance with layout or design rules. Useful for interconnect visualization, preliminary layout layout compaction, power/ground routing, etc.

Slide 21: 

Jhon P. U Stick Diagrams Metal poly ndiff pdiff Can also draw in shades of gray/line style.

Slide 22: 

Jhon P. U Stick Diagrams Buried Contact Contact Cut

Slide 23: 

Jhon P. U 5 V Dep V out Enh 0V V in 5 v 0 V V in 5 v

Slide 24: 

Jhon P. U Stick Diagram - Example I NOR Gate OUT B A

Slide 25: 

Jhon P. U Stick Diagram - Example II Power Ground B C Out A

Slide 26: 

Jhon P. U Points to Ponder be creative with layouts sketch designs first minimize junctions but avoid long poly runs have a floor plan plan for input, output, power and ground locations

Slide 27: 

Jhon P. U The End