fpga (field programmable gate array)

FPGA (Field Programmable Gate Array):

FPGA (Field Programmable Gate Array)

contents:

contents What is FPGA? History of Evolution FPGA programmability Antifuse Programming SRAM Programming Floating Gate programming FPGA Architecture CLB IOB Programmable Floating Channel Why FPGA? FPGA Drawbacks Application Conclusion 2

What is FPGA?:

What is FPGA? It is an IC(Integrated Circuit) with a very high logic capacity Completely programmable even after the a product is shipped or in the “ field ” so the name is given. 3

History of Evolution::

History of Evolution: FPGAs belong to a class of devices named as FPD(field programmable device) or PLD(programmable logic devices) FPD/PLDs- can be configured by the end user to realize various functionality. The evolution of FPGA goes like this PROM PLA PAL CPLD FPGA 4

History of Evolution (cntd…):

History of Evolution ( cntd …) Programmable Read Only Memory (PROM) Structure fuse programming n address i /p can implement n i /p logic function uses full decoder for its i /p Problem Area efficiency fuses PROM CELLS 5

History of Evolution (cntd…):

History of Evolution ( cntd …) Programmable Logic Array (PLA) Structure Programmable AND plane followed by programmable or wired OR plane. Sum of product form Advantage No decoder required Problem Two levels of programming adds delay and increases cost . Programmable Array Logic (PAL) Structure Programmable AND plane and fixed OR plane. Advantage Low cost and size. Problem Less flexible than PLA All these PLA and PAL are Simple Programmable Logic Devices (SPLD). Common Problem: Logic plane structure grows rapidly with number of inputs 6

History of Evolution (cntd…):

History of Evolution ( cntd …) To mitigate the problem Complex Programmable Logic Devices (CPLD) Structure programmably interconnect multiple SPLDs. advantage logic capacity up to the equivalent of about 50 typical SPLD devices Problem : Extending to higher density difficult 7

History of Evolution (cntd…):

History of Evolution ( cntd …) All the previous devices indicates that the complete solution would be a Very high capacity device with wide range of programmability. Then FPGA came into the picture. 8

FPGA PROGRAMMABILITY:

FPGA PROGRAMMABILITY Programmability of FPGA is achieved in three ways Antifuse programming methodology SRAM programming technology Floating Gate Programming 9

Antifuse programming methodology :

Antifuse programming methodology Antifuse systems( eg . amorphous Si,ONO ) are placed at the junctions of different connecting paths. These systems(built of special materials) normally have high resistance (effectively open circuits) Upon application of programming voltage across them resistance drop to a few ohms. Advantage: Small size Low series resistance and low parasitic capacitance Disadvantage: Interconnect is not reprogrammable R>1Mohm Before the antifuse blown antifuse After the antifuse blown R=few ohms Connecting paths 10

SRAM programming technology :

SRAM programming technology Loads and stores values in SRAMs to facilitate programmability to control pass gates. 1= closed switch connection 0= open For mux , SRAM determines the mux input selection process. Advantage Fast re-programmability Standard IC fabrication Tech. is used Disadvantage SRAM volatile Requires large area 11

Floating Gate Programming :

Floating Gate Programming Tech used in EPROM and EEPROM devices is used Switch is disable by applying high voltage to gate-2 between gate-1 and drain. The charge is removed by UV light Advantage:- No external permanent memory is needed to program it at power-up Disadvantage:- Extra processing steps Static power loss due to pull up resistor and high on resistance +v EPROM transister Bit Line Gate 1 Gate 2 Word line 12

FPGA architecture :

FPGA architecture There are three primary configurable elements in FPGA 1) Configurable Logic Block(CLB) - implement different functions. 2) Input/Output Block(IOB) - provides the interface between external pins and internal signal lines 3)Programmable Routing Channel - controls the connections among different blocks Programmable interconection Configurable logic block I/O block 13 Configurable Routing channel

Configurable Logic Block(CLB):

Configurable Logic Block(CLB) G1 G2 G3 G4 F1 F2 F3 F4 H1 SET RESET CONTROL MUX controlled by configuration program SET RESET CONTROL DIN CLBs contain 3 Look Up Table(F,G &H function generator) Two D Flip-Flops And A group of MUXs SR SR 14

CLBs(cntd..):

CLBs( cntd ..) Look Up Table Can perform any function on its i /p depending on the values stored in the memory location. Combination of F,G & H allows to implement a function of upto 9 variables. Advantage: Minimizes no. of blocks required Thereby increases speed and density D Flip-Flop 2 edge triggered Flip-Flops are having common clock & clock enable i / ps Clock may be inverted before driving Flip-Flops thus configuring them as either positive or negative edge triggered. Clock enable i /p to Flip-Flop is active high. Set-Reset i /p allows to set or reset Flip-Flops asynchronously. 15

CLBs(cntd..):

CLBs( cntd ..) MUX Used to allow the intended signal to go to the next stage. Allows the combinational functions o/p that is F,G or H o/p to be o/p of the CLB through X or Y Controls the D Flip-Flop i /p (allows F,G or H o/p or a direct input to CLB as DIN to go to the i /p of d Flip-Flop) Determines triggering edge of the clock. 16

Input/Output Block(IOB):

Input/Output Block(IOB) Two types of IOBs are there 1)Dedicated for configuration of FPGA 2)User Configurable User configurable IOBs can be configured as i / p,o /p or bidirectional for providing connections of internal CLBs to external package pins INPUT BLOCK The i /p signal can directly go to routing channel or it can go via i /p register I/P register can be level or edge sensative Clock can be direct or inverted Registered data path has one tap delay element to adjust set up or hold time of Flip-Flops. 17

Input/Output Block(IOB)(cntd..):

Input/Output Block(IOB) ( cntd ..) OUTPUT BLOCK CLB o/ ps can be inverted and go directly or via a register to the o/p buffer user controlled T i /p ORing with GTS(Global Tri Sate)signal controls o/p buffer( e.g -if high ,places buffer in high impedence state) GTS which is common to all user IOBs is made high during configuration Programmable pull up or down netwrk is there for connecting unused pin to Vcc or GND. 18

Programmable Routing Channel :

Programmable Routing Channel Routing Channel -metallic conductor used to make connection Three types are there CLB Routing Channel :-runs along each row and columns of CLBs. IOB Routing Channel :-forms Versa Ring outside CLB array & connects IOB with CLB routing channels. Global Routing Channel :-routs global signals ( eg . Clock) with minimum delay. Programmability in routing channels is obtained by using :- (a) connection box and (b) switch box 19

Programmable Routing Channel(cntd..):

Programmable Routing Channel ( cntd ..) Connection Box:- connects channel wires to the i/o pins of CLBs. Switch Box:- allow wires to switch between vertical and horizontal wires. Routing channels may be of three types (a) Single length ,(b) double length & (c) long lines Switch box Connection box 20

Programmable Routing Channel(cntd..):

Programmable Routing Channel ( cntd ..) Single length lines span through one CLB & provide short connections among CLBs Double length line spans two CLBs, offers low routing delay. Long lines run along entire length or width of the array longs doubles singles SB SB SB SB SB SB 21 CB CB CB

Programmable Routing Channel(cntd..):

Programmable Routing Channel ( cntd ..) Interconnect Point in both switching and connection box –implemented through 6 pass transistors. Interconnect point Pass Transistors vertical wires Horizontal Wires 22

Why FPGA??:

Why FPGA?? In the field FPGA has strong opponent in the form of ASIC(application Specific IC). ASICs are designed to perform a particular function using custom design technique. FPGA Advantages FPGAs are flexible,can be used for prototyping. Offers less time-to-market. NRE cost is low. Design cycle is simple Easy upgrades like software 23

FPGA drawbacks:

FPGA drawbacks FPGAs are lagging in some fields while compared to ASICs ASICs are specifically designed for some purpose, so are faster than FPGAs. ASICs require less power than FPGAs. ASICs are cost effective for very large volume design. 24

Application:

Application Applications of FPGAs include (a) digital signal processing , (b) aerospace and defense systems, (c) ASIC prototyping, (d) medical imaging , (e)metal detection and a growing range of other areas. The inherent parallelism of the logic resources on an FPGA allows for considerable computational throughput. This has driven a new type of processing called reconfigurable computing , where time intensive tasks are offloaded from software to FPGAs. 25

Conclusion :

Conclusion Choice of ASICs or FPGAs are completely case dependent For a good design technique and implementation a perfect mixture of both will ensure the optimum profitability. 26