uP1_lec5_memory

Slide 1: 

Instructor: Dr. Michael Geiger Fall 2008 Lecture 5: Static & Dynamic Memory ECE 461/ECE 566Microprocessors IUniversity of Massachusetts Dartmouth

Outline : 

12/2/2009 ECE 461/566: Lecture 5 2 Outline Announcements Quiz 3 next time—covers today’s lectures ECE 566 research paper posted (due 11/19) Reminder: regrade requests Extension until next week Cover lecture 6 as well today Memory organization SRAM DRAM

Memory configuration : 

12/2/2009 ECE 461/566: Lecture 5 3 Memory configuration Talk about memory using 2 terms Capacity: # of bits (or bytes) memory contains Organization: (# of locations) x (bits per location) Product = capacity of each “chip” Examples: 4M x 8  4 MB 32M x 1  4 MB

Memory organization, pt. 2 : 

12/2/2009 ECE 461/566: Lecture 5 4 Memory organization, pt. 2 Can approach overall memory setup from a couple of perspectives: Given memory organization, how many chips do we need to provide appropriate amount of data? i.e., minimum # of chips needed to fill data bus For example, need two 64K x 8 RAMs for project Given a specific number of chips with a given organization, how do we set them up? Can end up with multiple “rows” of memory

Memory organization ex. 1 : 

Memory organization ex. 1 What’s the minimum number of memory chips we need to build a 68000-based system, given an organization of: 64K x 16? 32K x 4? 128K x 2? Remember, data bus is 16 bits; therefore: Need 1 64K x 16 chip Need 4 64K x 4 chips (4 chips x 4 data bits/chip = 16) Need 8 128K x 2 chips (8 chips x 2 data bits/chip = 16) 12/2/2009 ECE 461/566: Lecture 5 5

Memory organization ex. 2 : 

12/2/2009 ECE 461/566: Lecture 5 6 Memory organization ex. 2 How would we organize the following sets of memory modules? Two 128K x 8 chips? Four 64M x 4 chips? Sixteen 32K x 2 chips? What’s the decoding circuitry look like for each of these organizations?

Memory organization ex. 2 (cont.) : 

12/2/2009 ECE 461/566: Lecture 5 7 Memory organization ex. 2 (cont.) Two 128K x 8 chips One chip holds upper bytes (D15 – D8), other holds lower bytes (D7 – D0) Both share same address range Upper chip enabled with UDS*, lower with LDS* Four 64M x 4 chips? Two chips to hold upper bytes, other two hold lower bytes Both share same address range Upper chips enabled with UDS*, lower with LDS* Sixteen 32K x 2 chips? Only need 8 of these to fill 16-bit data bus, so two “rows” of memory, each with its own address range, spanning 64 KB Within each row, 4 chips for upper bytes, 4 for lower

Memory characteristics : 

12/2/2009 ECE 461/566: Lecture 5 8 Memory characteristics RAM (random access memory) vs. ROM (read-only memory) If general-purpose computer, most of the immediate access memory is RAM If intended for a single task, it’s mostly ROM Some ROM is always necessary Two choices with RAM Static RAM (SRAM) Dynamic RAM (DRAM)

SRAM vs. DRAM : 

12/2/2009 ECE 461/566: Lecture 5 9 SRAM vs. DRAM Static memory 6 transistors per cell Straightforward to use Dynamic memory 1 transistor per cell More complex Address multiplexing Refresh

SRAM implementation : 

12/2/2009 ECE 461/566: Lecture 5 10 SRAM implementation Word line (WL) selects appropriate row On read, cell drives bitline (BL) values On write, bitlines are driven and values are stored

SRAM timing : 

12/2/2009 ECE 461/566: Lecture 5 11 SRAM timing Read (L): Assert OE*; assert CS* once address valid Write (R): Assert CS* when address valid; WE* once processor chooses write operation

DRAM implementation : 

12/2/2009 ECE 461/566: Lecture 5 12 DRAM implementation Store information as charge on capacitor Charge leaks from capacitor Requires refresh Small cell size allows higher density … but requires more address pins Multiplex addresses—row and column

DRAM timing (read) (p. 385) : 

12/2/2009 ECE 461/566: Lecture 5 13 DRAM timing (read) (p. 385) Row address strobe (RAS) indicates row address on address bus Column address strobe (CAS) indicates column address on address bus

DRAM timing (write) (p. 386) : 

12/2/2009 ECE 461/566: Lecture 5 14 DRAM timing (write) (p. 386) RAS/CAS timing similar to read W* (write enable) asserted once processor indicates write operation is to take placs

DRAM controller : 

12/2/2009 ECE 461/566: Lecture 5 15 DRAM controller One problem with these signals: what’s processor actually give you? Need DRAM controller to take processor outputs and generate appropriate signals RAS, CAS, refresh cycles