DCT_slides

Design and Implementation of a High-Speed, Low-Power VLSI Chip for the DCT Transform : 

Design and Implementation of a High-Speed, Low-Power VLSI Chip for the DCT Transform Project Advisor: Professor A. Doboli Participates: Tak Yuen Lam, Kit Lam, Wei Kit Ng, Ying Lam

Back Ground : 

Back Ground The DCT application can have many purposes: Filtering Teleconferencing high-definition television (HDTV) speech coding, image coding data compression, and more.

Back Ground : 

Back Ground All of these use DCT algorithm for compression and/or filtering purposes. The DCT has energy packing capabilities approaches the statistically optimal transform in de-correlating a signal. It was implemented with discrete components in a chip.

Goal : 

Goal . Implementation of a VLSI chip with: -high speed -low power compute the 2-D Discrete Cosine Transform (DCT) function of an 8 x 8 element matrix is presented.

Goal : 

Goal Save Power Consumption during Computing Operation in the chip: -Specially design multiplier with less computation. -Less switching -Simplify of the equations. High Speed Processing: using pipeline technology. Ignore zero’s in the multiplier.

Basic Formula : 

Basic Formula Forward DCT: Inverse DCT:

Basic Formula : 

Basic Formula C(u) = ,C(v) = for u,v = 0 C(u) = ,C(v) = for u,v = 1 through N-1; N = 4, 8, or 16

1-D DCT Matrix : 

1-D DCT Matrix

Simplification: : 

Simplification:

The following equations are derived from the matrix above : 

The following equations are derived from the matrix above

Simplified Equations : 

Simplified Equations Y(0) = c4[j + k+l+m] Y(2) = c2[j-k] + c6[m-l] Y(4) = -c4[j+k+l+m] Y(6) = c6[j-k] –c2[m-l] Y(1) = e + f + h + [c+c3-c5-c7]a Y(3) = e + g + I + [c1+c3+c5-c7]b Y(5) = e + g + h + [c1+c3-c5+c7]c Y(7) = e + f + I + [-c1+c3+c5-c7]d

Simplified Equations : 

Simplified Equations a = x0–x7; b= x1-x6; c = x2–x5; d = x3-x4 j = x0+x7; k = x1+x6; l = x2+x5; m= x3+x4 e = c3[a+b+c+d] f=[c7-c3][a-d] g=[-c1-c3][b+c] h=[c5-c3][a+c] I=[-c5-c3][b+d]

1D DCT Flow Chart : 

1D DCT Flow Chart Pixel Memory Cosine Matrix Memory Multiplier DCT Coefficients Register Bank Shifter

2D DCT Flow Chart : 

2D DCT Flow Chart 1 D DCT Transpose 1 D DCT Control

1-D DCT Architecture(First Version) : 

1-D DCT Architecture(First Version)

1-D DCT Architecture(Final Version) : 

1-D DCT Architecture(Final Version) X0 X1 X3 X4 X2 X5 X1X6 X0 X7 X3 X4 X2 X5 X1 X6 Y0 Y4 Y2 Y6 Y1 Y7 Y5 Y3 State 1 State 2 State 3

Transpose Architecture : 

Transpose Architecture OUT 3

Hardware: Fuller Adder : 

Hardware: Fuller Adder

Hardware: Multipier : 

Hardware: Multipier Example:

Simplified Multiplication : 

Simplified Multiplication Example: - ignore

Comparison : 

Comparison

VLSI: Full Adder (from Library) : 

VLSI: Full Adder (from Library)

VLSI: Multiplier : 

VLSI: Multiplier

Multiplier Simulation : 

Multiplier Simulation

VLSI: 1 bit Transpose : 

VLSI: 1 bit Transpose

VLSI: 8x8 Transpose : 

VLSI: 8x8 Transpose

Transpose Simulation : 

Transpose Simulation

VLSI: 1D DCT Part One : 

VLSI: 1D DCT Part One

1 D DCT Part One Simulation : 

1 D DCT Part One Simulation

VLSI: 1D DCT Part Two : 

VLSI: 1D DCT Part Two

1 D DCT Part two Simulation : 

1 D DCT Part two Simulation

Java simulation : 

Java simulation Java Code: public void transform() { g = new int[8][8];   for ( int i = 0; i < 8; i++ ) { for ( int j = 0; j < 8; j++ ) { double ge = 0.0; for ( int x = 0; x < 8; x++ ) { for ( int y = 0; y < 8; y++ ) { double cg1 = (2.0*(double)x+1.0)*(double)i*Math.PI/16.0; double cg2 = (2.0*(double)y+1.0)*(double)j*Math.PI/16.0;   ge += ((double)f[x][y]) * Math.cos(cg1) * Math.cos(cg2);   } } double ci = ((i==0)?1.0/Math.sqrt(2.0):1.0); double cj = ((j==0)?1.0/Math.sqrt(2.0):1.0); ge *= ci * cj * 0.25; g[i][j] = (int)Math.round(ge); } } }

Simulation Result : 

Simulation Result INPUT MATRIX:

Simulation Result : 

Simulation Result Output matrix after DCT: