MIL-STD-1553-B BUS CONTROLLER ON FPGA MIL-STD-1553-B BUS CONTROLLER ON

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MIL-STD-1553-B BUS CONTROLLER ON FPGA:

MIL-STD-1553-B BUS CONTROLLER ON FPGA SUBMITTED BY :- Soniya Panwar Santosh Kumari

INTRODUCTION:

INTRODUCTION In this project, we will realize the MIL-STD-1553-B Bus Controller on FPGA board. Here, we are sending 20 bit command word and data word by using Bus Controller on FPGA board to another system. In order to do this, we must know about the following:- MIL-STD-1553-B FPGA VHDL XILINX ISE DESIG SUITE IMPACT AVNET BOARD

MIL-STD-1553-B:

MIL-STD-1553-B MIL-STD-1553-B is a military standard that defines the electrical and protocol characteristics for a data bus. Data bus provides medium for the exchange of data and information between the systems.

MIL-STD-1553-B Characteristics:

MIL-STD-1553-B Characteristics Data Rate MHz Word Length 20 bits Data Bit/ Word 16 bits Message Length Maximum of 32 data words Transmission Technique Half- Duplex Operation Asynchronous Encoding Manchester-II bi-phase Protocol Command/Response Bus Control Single or Multiple Fault Tolerance Typically Dual Redundant, second bus in “Hot Backup” status Message Formats Controller to Terminal, Terminal to Controller, Terminal to Terminal , Broadcast, System Control Number of Remote Terminals Maximum of 31 Terminal Types Remote terminal, Bus controller, Bus monitor Transmission Media Twisted shield pair Coupling Transformer and direct

HARDWARE ELEMENT:

HARDWARE ELEMENT The standard defines four hardware elements: The transmission media. Remote terminals. Bus controllers. Bus monitors.

PowerPoint Presentation:

Transmission Media :- The transmission media, or data bus, is defined as a twisted shield pair transmission line consisting of the main bus and a number of stubs. Remote Terminals :- The remote terminal is necessary to transfer data between the data bus and the subsystem. Bus Monitor :- A bus monitor is a terminal that listens to the exchange of information on the data bus. Today it is common for bus monitors to contain a remote terminal.

Bus Controller:

Bus Controller The bus controller is responsible for directing the flow of data on the data bus. The bus controller is the only one allow to issue command onto the data bus. The commands may be for the transfer of data or the control and management of the bus. There are three types of bus controller architectures: A word controller. A message controller. A frame controller.

Protocol :

Protocol The control, data flow, status reporting, and management of the bus are provided by three word types. These word types are: Command words. Data words. Status words. Each word type has a unique format. Each bit is twenty bits in length. The first three bits are used as a synchronization field and the next sixteen bits are the information field and the last bit is the parity bit.

PowerPoint Presentation:

Command Words :- The command word specifies the functions that a remote terminal is to perform. Only the active bus controller transmit this word. The word begins with the command sync in the first three bit times. Data Word :- The data word contains the actual information that is being transferred within a message. It can be transmitted by either a remote terminal or a bus controller. Status Word :- A remote terminal in response to a valid message transmits only the status word. The status word is used to convey to the bus controller whether the message was properly received or to convey the status of the remote terminal.

WORD FORMAT:

WORD FORMAT The terminal hardware is responsible for the Manchester encoding and decoding of the word types. BIT TIMES COMMAND WORD SYNC TERMINAL ADDRESS T/R SUBADDRESS/ MODE WORD COUNT/MODE CODE PAR DATA WORD SYNC DATA PAR STATUS WORD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 1 5 5 1 16 1 5 1 1 1 3 1 1 1 1 1 1

MIL-STD-1553 Applications:

MIL-STD-1553 Applications It has been applied in satellites. It has been employed on large transports, bombers and helicopters. It is even contained within missiles and servers. The navy has applied the data bus to both surface and subsurface ships.

What is FPGA ?:

What is FPGA ? FPGA :- Field Programmable Gate Array. It can be considered as an array of Configurable Logic Blocks (CLBs) that can be connected together through a vast interconnection. FPGAs have traditionally found use in high-speed custom digital applications where designs tend to be more constrained by performance rather than cost. The explosion of integration and reduction in price has led to the more recent widespread use of FPGAs in common embedded applications.

Internal Structure of FPGA:

Internal Structure of FPGA

Architecture of FPGA:

Architecture of FPGA The architecture of FPGA consists of four fundamental programmable functional elements: Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data. Input / Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Block RAM provides data storage in the form of 18-Kbit dual-port blocks. Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals.

Architecture of FPGA:

Architecture of FPGA

ADVANTAGE OF FPGA::

ADVANTAGE OF FPGA: Faster response times Reduced time to market Low cost Long-term maintenance Reduced development time and risk Better product High level of integration

APPLICATIONS:

APPLICATIONS Aerospace and defense Automotive Broadcast Full-featured consumer applications Fulfilling industrial/scientific/medical needs Wireless communications Wired communications

Programming language used : VHDL:

Programming language used : VHDL VHDL (Very high speed integrated circuit Hardware Description Language) is a language used to describe a digital circuit at behavior or structure level. The digital circuit VHDL model is then simulated and the working of the circuit can be verified by simulated wave forms. It has four type of architecture modeling:- Data Flow Modeling Behavioral Modeling Structural Modeling Mixed Modeling

History of VHDL:

History of VHDL Three companies, IBM, Texas Instruments, and Intermetrics , were first awarded the contract by the DOD to develop a version of the language in 1983. Version 7.2 of VHDL was developed and released to the public in 1985.

XILINX ISE DESIGN SUITE 10.1:

XILINX ISE DESIGN SUITE 10.1 XILINX is an American technology company, primarily a supplier of programmable logic devices (PLDs). It is known for inventing FPGA and as the first semiconductor company. All Xilinx FPGA families consist of an array of configurable Logic Blocks (CLBs) embedded in a configurable interconnect structure and surrounded by configurable I/O blocks.

Introduction:

Introduction Combined with the Spartan-3 generation FPGA family, the ISE optimized design tools help you finish faster and lower your project costs. The ISE package is a collection of Xilinx software design tools that concentrate on delivering the most productivity available for your Spartan-3 generation logic performance.

Features of Xilinx ISE Suite:

Features of Xilinx ISE Suite The following is an outline of the features offered in the ISE tools: Design Entry  Synthesis Simulation Implementation Device Download

iMPACT Configuration Tool:

iMPACT Configuration Tool The iMPACT configuration tool, GUI based tool, allows you to configure your PLD designs using JTAG Connector. It also allows you to do the following: Download Read back and verify design configuration data Debug configuration problems

FPGA Board –AVNET:

FPGA Board –AVNET The Spartan-3A Evaluation Kit provides a platform for engineers designing with the Xilinx Spartan-3A FPGA. The board provides the necessary hardware to not only evaluate the advanced features of these devices but also to implement user applications using peripherals and expansion connectors on the Spartan-3A evaluation board.

Features:

Features Xilinx 3S400A-4FTG256C FPGA • Clocks 16 MHz Oscillator ( Maxim) 12 MHz Clock from PSoC device 32 kHz Clock from PSoC device • Memory 32 Mb Page-Mode Flash Memory ( Spansion ) 128 Mb SPI Flash Memory ( Spansion ) • Interfaces USB 2.0 ( PSoC ) JTAG Programming/Configuration Port Temperature Sensor ( Texas Instruments) • Buttons and switches Four User LEDs Four PSoC Cap Sense capacitive switches Four FPGA user “pushbuttons” (forwarded from PSoC Cap Sense switches) Reset Push Button Switch • User I/O and expansion Digilent 6-pin header (2) 2x20 0.1” Expansion Connector • Configuration and Debug JTAG

Components :

Components The Spartan-3A evaluation board requires a +5 V input via a USB cable. LED (D1) should be illuminated when power is applied. A blue LED (D7) should light when program is downloaded in the board. LEDs :- Four LEDs are provided for signaling purposes and connected to the FPGA. LEDs FPGA Pin# LED1 (D5) D14 LED2 (D4) C16 LED3 (D3) C15 LED4 (D2) B15

GPIO Connector (J4) pin assignment:

GPIO Connector (J4) pin assignment

PowerPoint Presentation:

Module Clocks :- Programming Mechanisms :- The Spartan-3A evaluation board provides four mechanisms to program and configure the FPGA; these are, Parallel Flash, JTAG, Serial Flash, and the Cypress PSoC . Here we are using JTAG Connector. Clocks FPGA Pin# 16.0MHz C10 (GCLK4) 12.0MHz N9 (GCLK0) 32.0kHz T7 (GCLK13)

Project Description:

Project Description On the basis of above knowledge we first write VHDL code for MIL-STD-1553-B Bus controller on Xilinx ISE Suite 10.1(software). Then synthesis and simulate the program and generate the bit file. Now, with help of JTAG connector, we burn this program on FPGA board (Avnet) using IMPACT 10.1. Voltage level of FPGA and MILL-STD-1553B are different, in order to make them compatible we have to connect a circuit in between these to systems. So we made a Converter PCB. For this we made a schematic diagram in Proteus7.7 which is given below.

Schematic Diagram of PCB:

Schematic Diagram of PCB

PowerPoint Presentation:

In bus controller, we have 2 word types:-  Command word Data word Command Words - The command word specifies the functions that a remote terminal is to perform. Only the active bus controller transmits this word. The word begins with the command sync in the first three bit times. Data Word - The data word contains the actual information that is being transferred within a message. It can be transmitted by either a remote terminal or a bus controller.

In Programming Part::

In Programming Part: In this project the values of command word and data word are given below:- Terminal Address- 10110 T/R- 0 (here 0 denote that remote terminal should receive the command) Sub Address- 11101 Word Count- 00001 Par- as per the command word Data- 0111001010001001 Here the value of Word Count is 00001 therefore after Command Word we get single Data Word. If the value of Word Count is 00010 then we get Data Word twice and if the value of Word Count is 00011 then we get Data Word three times similarly, and so on. At the end of Data Word we should get a Status Word from the Remote terminal as an acknowledgement but due to unavailability of resources (i.e. Remote terminal) and time, we are unable to get the Status Word.

COMMAND WORD:

COMMAND WORD

DATA WORD:

DATA WORD

In FPGA Part: :

In FPGA Part: In our project we are getting four outputs from FPGA:- Result - at pin number “A14” from where we get serial Command Word and Data Word. Clk_out - at pin number “A13” to provide clock to the Converter PCB. En - at pin number “C13” to provide reset at pin number 6 of Multiplexer located at PCB. Work - at pin number “B15” (LED), when reset = ‘0’, led = ‘1’. These pins are GPIO Connector (J4) pins of FPGA used for general purpose input/output.  

Hardware TESTING:

Hardware TESTING To test the program we first burn the code in Spartan 3A board then send the output to a Converter PCB which converts the output into Manchester II Bi-phase format which we can visualize on CRO(Cathode Ray Oscilloscope), so the final output should be like the figure given below:-

STANDARD OUTPUT:

STANDARD OUTPUT

Complete Setup:

Complete Setup

Hardware Connections:

Hardware Connections

Wave Form of Command Word:

Wave Form of Command Word

Wave Form of Data Word:

Wave Form of Data Word

CONCLUSION:

CONCLUSION In this project we are realizing MIL-STD-1553-B Bus Controller on FPGA . In which we are supposed to program a FPGA board which works as a Bus Controller of MIL-STD-1553-B and is able to sending 20 bit Command word and Data word through Spartan 3A board. For which we had to write a VHDL Code with the help of Xilinx ISE design Suite 10.1. Then burn that program into Spartan 3A board with the help of iMPACT 10.1 which is a part of Xilinx ISE design Suite 10.1 and JTAG Connector and then we can check the output by connecting it to another system or an Oscilloscope. We had connected a Converter PCB in between FPGA Board and CRO as an interface then finally we get the output in Manchester II bi phase Code at another end.

THANK YOU:

THANK YOU

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