Unit-1 & unit-2

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microcontroller-8051architecture & programming

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Ms Shilpa Chaman 1 1 ETC-501 Ms Shilpa Chaman 1

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Ms Shilpa Chaman 2 2  1.1 Comparison between Microprocessor and Microcontroller  1.2 Features architecture and pin configurations  1.3 CPU timing and machine cycle  1.4 Input / Output ports  1.5 Memory organization  1.6 Counters and timers  1.7 Interrupts  1.8 Serial data input and output Ms Shilpa Chaman 2

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 Microprocessor is heart of Computer system.  Here μp is interfaced to Memory and I/O components  The circuit is not compact.  Cost of the entire system increases  The entire power consumption is high.  Microprocessor is heart of Computer system.  CPU RAM ROM Timers Serial ports I/O port all are on a single chip  Can be used in compact systems.  Cost of the entire system is low  Total power consumption is less also power saving modes like idle mode and power saving mode are aplicable Ms Shilpa Chaman 5

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 Microprocessors are based on von Neumann model/architecture where program and data are stored in same memory module  Mainly used in personal computers.  Their clock speed is quite high in 5 MHz - GHz.  Flexibiltiy Versatility  Different Application softwares can be loaded to RAM  Micro controllers are based on Harvard architecture where program memory and Data memory are separate.  Used mainly in washing machine MP3 players digicam cars r  They operate from a few to 30 to 50 MHz  Limited Flexibility.  Only one application software which is ROM based. Ms Shilpa Chaman 6

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Ms Shilpa Chaman 9 9  Ms Shilpa Chaman 9

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Ms Shilpa Chaman 11 11 Ms Shilpa Chaman 11 AT89S8253 from Atmel Corporation

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Ms Shilpa Chaman 18 18 1. Same memory holds data instructions. 2. A single set of address/data buses between CPU and memory and therefore data transfers and instruction fetches must be scheduled - they can not be performed at the same time. 3. It is comparatively slower. 4. MCs with von-Neumanns architecture are called CISC microcontrollers. 1. Separate memories for data and instructions. 2. It has separate data and instruction busses allowing transfers to be performed simultaneously on both busses. 3. Thus a greater flow of data is possible through the CPU and of course a greater speed of work. 4. MCs with Harvard architecture are called "RISC MCs". 5. It has fewer instructions than von-Neumanns and instructions are usually executed in one cycle.

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Ms Shilpa Chaman 29 ORG 0000H MOV R033H MOVES 33 IN REGISTER R0 OF BANK0 SETB PSW.3 BANK 1 IS SELECTED MOV R144H MOVES 44 IN REGISTER R1 OF BANK1 SETB PSW.4 BANK 3 IS SELECTED MOV R355H MOVES 55 IN REGISTER R3 OF BANK3 CLR PSW.3 BANK 2 IS SELECTED MOV R466H MOVES 66 IN REGISTER R4 OF BANK2 END

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Ms Shilpa Chaman 46 Interrupt Vector Address System Reset 0000H External 0 0003H Timer 0 000BH External 1 0013H Timer 1 001BH Serial Port 0023H Timer 2 002BH

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Ms Shilpa Chaman 57 Example: Write a program to copy a block of 10 bytes from RAM location starting at 37h to RAM location starting at 59h. Solution: MOV R037h source pointer MOV R159h dest pointer MOV R210 counter L1: MOV AR0 MOV R1A INC R0 INC R1 DJNZ R2L1

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 MOV DPTR4500  MOVX A DPTR  MOV R0A  INC DPTR  MOVX A DPTR  MOV R1A  INC DPTR  MOVX A DPTR  MOV R2A  INC DPTR  MOVX A DPTR  MOV R3A Ms Shilpa Chaman 59

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Ms Shilpa Chaman 62  ORG 0000H  MOV R030H R030H  MOV R110 R110 ACT AS COUNT  MOV DPTR0200H DPTR200H look-up table  BACK: CLR A ACC IS CLEARED  MOVC AA+DPTR Index ADDRESSING MOV R0A save first char in LOC 30H  INC DPTR DPTR201 point to next char  DJNZ R1BACK  Here: SJMP HERE stay here   Data is burned into code space starting at 200H   ORG 200H  DB 149162536496481100  END end of program 

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Ms Shilpa Chaman 79 SETB bit bit1 CLR bit bit0 SETB C CY1 SETB P0.0 bit 0 from port 0 1 SETB P3.7 bit 7 from port 3 1 SETB ACC.2 bit 2 from ACCUMULATOR 1 SETB 05 set high D5 of RAM loc. 20h Note: CLR instruction is as same as SETB i.e.: CLR C CY0 But following instruction is only for CLR: CLR A A0

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Ms Shilpa Chaman 81  MUL AB B|A AB MOV A25H MOV B65H MUL AB 25H65H0E99 B0EH A99H  DIV AB A A/B B A mod B MOV A25 MOV B10 DIV AB A2 B5

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Ms Shilpa Chaman 82 RR – RL – RRC – RLC A EXAMPLE: RR A RR: RRC: RL: RLC: C C

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Ms Shilpa Chaman 83 DEC byte bytebyte-1 INC byte bytebyte+1 INC R7 DEC A DEC 40H 4040-1

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Ms Shilpa Chaman 84 Conditional Jumps :

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Ms Shilpa Chaman 85 DJNZ Write a program to clear ACC then add 3 to the accumulator ten time Solution: MOV A0 MOV R210 AGAIN: ADD A03 DJNZ R2AGAIN repeat until R20 10 times MOV R5A

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Ms Shilpa Chaman 92 ANL - ORL – XRL Bitwise Logical Operations: AND OR XOR EXAMPLE: MOV R589H ANL R508H CPL A 1’s complement Example: MOV A55H A01010101 B L01: CPL A MOV P1A ACALL DELAY SJMP L01

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Ms Shilpa Chaman 93 ACALL: Absolute Call ADD ADDC: Add Acc. With Carry AJMP: Absolute Jump ANL: Bitwise AND CJNE: Compare Jump if Not Equal CLR: Clear Register CPL: Complement Register DA: Decimal Adjust DEC: Decrement Register DIV: Divide Accumulator by B DJNZ: Dec. Reg. Jump if Not Zero INC: Increment Register JB: Jump if Bit Set JBC: Jump if Bit Set and Clear Bit JC: Jump if Carry Set JMP: Jump to Address JNB: Jump if Bit Not Set JNC: Jump if Carry Not Set JNZ: Jump if Acc. Not Zero JZ: Jump if Accumulator Zero LCALL: Long Call LJMP: Long Jump MOV: Move Memory MOVC: Move Code Memory MOVX: Move Extended Memory MUL: Multiply Accumulator by B NOP: No Operation ORL: Bitwise OR POP: Pop Value From Stack PUSH: Push Value Onto Stack RET: Return From Subroutine RETI: Return From Interrupt RL: Rotate Accumulator Left RLC: Rotate Acc. Left Through Carry RR: Rotate Accumulator Right RRC: Rotate Acc. Right Through Carry SETB: Set Bit SJMP: Short Jump SUBB: Sub. From Acc. With Borrow SWAP: Swap Accumulator Nibbles XCH: Exchange Bytes XCHD: Exchange Digits XRL: Bitwise Exclusive OR Undefined: Undefined Instruction

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 Microcontrollers often have: A. CPUs B. RAM C. ROM D. all of the above  The internal RAM memory of the 8051 is: A. 32 bytes B. 64 bytes C. 128 bytes D. 256 bytes  The address space of the 8051 is divided into four distinct areas: internal data external data internal code and external code. A. True B. False Ms Shilpa Chaman 19 5

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Ms Shilpa Chaman 19 6  The 8051 has ________ 16-bit counter/timers. A. 1 B. 2 C. 3 D. 4  The 8051 has ________ parallel I/O ports. A. 2 B. 3 C. 4 D. 5  The total external data memory that can be interfaced to the 8051 is: A. 32K B. 64K C. 128K D. 256K Bit-addressable memory locations are: A. 10H through 1FH B. 20H through 2FH C. 30H through 3FH D. 40H through 4FH

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 Which architecture is followed by general purpose microprocessors a Harvard architecture b Von Neumann architecture c none of the mentioned d all of the mentioned  Which architecture provides separate buses for program and data memory a Harvard architecture b Von Neumann architecture c none of the mentioned d all of the mentioned  Harvard architecture allows: a separate program and data memory b pipe-ling c complex architecture d all of the mentioned Ms Shilpa Chaman 19 7

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 8051 series has how many 16 bit registers a 2 b 3 c 1 d 0  When 8051 wakes up then 0×00 is loaded to which register a DPTR b SP c PC d PSW  When the micro controller executes some arithmetic operations then the flag bits of which register are affected a PSW b SP c DPTR d PC  How is the status of the carry auxiliary carry and parity flag affected if write instruction MOV A9C ADD A64H a CY0AC0P0 b CY1AC1P0 c CY0AC1P0 d CY1AC1P1  19 8

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 How are the bits of the register PSW affected if we select Bank2 of 8051 a PSW.50 and PSW.41 b PSW.20 and PSW.31 c PSW.31 and PSW.41 d PSW.30 and PSW.41  If we push data onto the stack then the stack pointer a increases with every push b decreases with every push c none of the mentioned d both of the mentioned  On power up the 8051 uses which RAM locations for register R0- R7 a 00-2F b 00-07 c 00-7F d 00-0F  How many bytes of bit addressable memory is present in 8051 based micro controllers a 8 bytes b 32 bytes c 16 bytes d 128 bytes Ms Shilpa Chaman 19 9

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Ms Shilpa Chaman 20 1 The 8051 microcontroller is of ___pin package as a ______ processor. a 30 1byte b 20 1 byte c 40 8 bit d 40 8 byte Which pin of port 3 is has an alternative function as write control signal for external data memory a P3.8 b P3.3 c P3.6 d P3.1 What is the Address SFR for TCON SCON SBUF PCON and PSW respectively a 88H 98H 99H 87H 0D0H. b 98H 99H 87H 88H 0D0H c 0D0H 87H 88H 99H 98H d 87H 88H 0D0H 98H 99H 7. Match the following: TCON i contains status information SBUF ii timer / counter control register. TMOD iii idle bit power down bit PSW iv serial data buffer for Tx and Rx. PCON v timer/ counter modes of operation. a 1-ii 2-iv 3-v 4-i 5-iii. b 1-i 2-v 3-iv 4-iii 5-ii. c 1-v 2-iii 3-ii 4-iv 5-i. d 1-iii 2-ii 3-i 4-v 5-iv.

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If the __ pin is ___ then we have the option of using the ____ ROM or EPROM together with _____ memory and devices. a EA high internal external b EA low internal external c EA high external internal d EA low external internal Ms Shilpa Chaman 20 2 The SP is of ___ wide register. And this may be defined anywhere in the ______. a 8 byte on-chip 128 byte RAM. b 8 bit on chip 256 byte RAM. c 16 bit on-chip 128 byte ROM d 8 bit on chip 128 byte RAM.

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 1. What is the clock source for the timers a some external crystal applied to the micro-controller for executing the timer b from the crystal applied to the micro-controller c through the software d through programming.  2. What is the frequency of the clock that is being used as the clock source for the timer a some externally applied frequency f’ b controller’s crystal frequency f c controller’s crystal frequency /12 d externally applied frequency/12  3. What is the function of the TMOD register a TMOD register is used to set different timer’s /Counters modes b TMOD register is used to load the count of the timer. c Destination register where the result is obtained after timer operation  d Is used to interrupt the timer 4. Auto reload mode is allowed in which mode of the timer a Mode 0 b Mode 1 c Mode 2 d Mode 3 Ms Shilpa Chaman 20 3

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 1. Find out the roll over value for the timer in Mode 0 Mode 1 and Mode 2 a 00FFH0FFFHFFFFH b 1FFFH0FFFHFFFFH c 1FFFHFFFFH00FFH d 1FFFH00FFHFFFFH  Sol: For Mode 0 13 bit value is used so 1FFFH is chosen to be the roll over value. Similarly for Mode 1- FFFFH and for Mode 2- FFH is the roll over value.  2.What steps are followed when we need to turn on any timer a load the count start the timer keep monitoring it stop the timer b load the TMOD register load the count start the timer keep monitoring it stop the timer c load the TMOD register start the timerload the count keep monitoring it stop the timer d none of the mentioned  TF1 TR1 TF0 TR0 bits are of which register a TMOD b SCON c TCON d SMOD  In the instruction “MOV TH1-3″ what is the value that is being loaded in the TH1 register a 0xFCH b 0xFBH c 0xFDH d 0xFEH Ms Shilpa Chaman 20 4

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 Which of the following best states the reason that why baud rate is mentioned in serial communication a to know about the no of bits being transmitted per second b to make the two devices compatible with each other so that the transmission becomes easy and error free c to use Timer 1 d for wasting memory  With what frequency UART operates where f denoted the crystal frequency a f/12 b f/32 c f/144 d f/384  What is the function of SCON register a to control SBUF and SMOD registers b to program the start bit stop bit and data bits of framing c none of the mentioned d both of the mentioned  What should be done if we want to double the baud rate a change a bit of the TMOD register b change a bit of the PCON register c change a bit of the SCON register d change a bit of the SBUF register Ms Shilpa Chaman 20 5

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 What is null modem connection a no data transmission b no MAX232 c the RxD of one is the TxD for the other d no serial communication  Which of the following best describes the use of framing in asynchronous means of communication a it binds the data properly b it tells us about the start and stop of the data to be transmitted or received c it is used for error checking d it is used for flow control  What is the difference between UART and USART communication a they are the names of the same particular thing just the difference of A and S is there in it b one uses asynchronous means of communication and the other uses synchronous means of communication c one uses asynchronous means of communication and the other uses asynchronous and synchronous means of communication d one uses angular means of the communication and the other uses linear means of communication  Which devices are specifically being used for converting serial to parallel and from parallel to serial respectively a timers b counters c registers d serial communication Ms Shilpa Chaman 20 6

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 1. When any interrupt is enabled then where does the pointer moves immediately after this interrupt has occurred a to the next instruction which is to be executed b to the first instruction of ISR c to the first location of the memory called the interrupt vector table d to the end of the program  Answer: c  2. What are the contents of the IE register when the interrupt of the memory location 0×00 is caused a 0xFFH b 0x00H c 0x10H d 0xF0H  Answer: b  3. After RETI instruction is executed then the pointer will move to which location in the program a next interrupt of the interrupt vector table b next instruction of the program after the IE instruction c next instruction after the RETI in the memory d none of the mentioned  Answer: b  Which pin of the external hardware is said to exhibit INT0 interrupt a pin no 10 b pin no 11 c pin no 12 d pin no 13  Answer: c Ms Shilpa Chaman 20 7

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 5. Which bit of the IE register is used to enable TxD/RxD interrupt a IE.D5 b IE.D2 c IE.D3 d IE.D4  Answer: d  6. Which of the following combination is the best to enable the external hardware interrupt 0 of the IE register assuming initially all bits of the IE register are zero a EX01 b EA1 c any of the mentioned d both of the mentioned  Answer: d  7. Why normally LJMP instructions are the topmost lines of the ISR a so as to jump to some other location where there is a wider space of memory available to write the codes b so as to avoid overwriting of other interrupt instructions c both of the mentioned d none of the mentioned  Answer: c Explanation: There is a small space of memory present in the vector table between two different interrupts so in order to avoid overwriting of other interrupts we normally jump to other locations where a wide range of space is available. Ms Shilpa Chaman 20 8

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 8. Which register is used to make the pulse a level or a edge triggered pulse a TCON b IE c IPR d SCON  Answer: a  9. What is the disadvantage of a level triggered pulse a a constant pulse is to be maintained for a greater span of time b difficult to analyse its effects c it is difficult to produce d another interrupt may be caused if the signal is still low before the completion of the last instruction  Answer: d Explanation: In a level triggered pulse if the signal does not becomes high before the last instruction of the ISR then the same interrupt will be caused again so monitoring of pulse is required for a level triggered pulse.  10. What is the correct order of priority that is set after a controller gets reset a TxD/RxD T1 T0 EX1 EX0 b TxD/RxD T1 T0 EX1 EX0 c EX0 T0 EX1 T1 TxD/RxD d EX0 T0 EX1 T1 TxD/RxD  Answer: c Ms Shilpa Chaman 20 9

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 org 0000h  mov dptr8100h  movx adptr  mov ba  mul ab  inc dptr  movx dptra  inc dptr  mov ab  movx dptra  end Ms Shilpa Chaman 21 3

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 org 0000h  mov dptr8100h  movx adptr  mov ba  mov r0a  mul ab  mov br0  mul ab  inc dptr  movx dptra  inc dptr  mov ab  movx dptra  end Ms Shilpa Chaman 21 4

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 org 0000h  mov dptr8100h // loc of ram  movx adptr //get no from ram  mov ba  mov r0a  mul ab //find square  mov r2b //move msb of result in r2  mov br0 //get original no in b  mul ab //mul square result lsb with no  mov r3b //move msb of result in r3  inc dptr  movx dptra //move lsb of cube result in ram Ms Shilpa Chaman 21 5

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 mov br0//get original no in b  mov ar2 //move msb of sq result in a  mul ab //mul square result msb with no  addc ar3 //add with carry a+r3  inc dptr  movx dptra  mov ab  inc dptr  movx dptra  end Ms Shilpa Chaman 21 6

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