SANDEEP VATWANI LOGICAL GATES PROJECT

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WELL COME TO SLIDE SHOW: 

WELL COME TO SLIDE SHOW

PRESENTED BY:-: 

PRESENTED BY:- NAME:- SANDEEP VATWANI STD:-XI SCHOOL:-ST XAVIERS HIGH SCHOOL HANSOL

Basic Logic Gates: 

Basic Logic Gates

Basic Logic Gates and Basic Digital Design: 

Basic Logic Gates and Basic Digital Design NOT, AND, and OR Gates NAND and NOR Gates DeMorgan’s Theorem Exclusive-OR (XOR) Gate Multiple-input Gates

Slide 5: 

NOT Gate -- Inverter X Y 0 1 1 0

NOT: 

NOT Y = ~X (Verilog) Y = !X (ABEL) Y = not X (VHDL) Y = X’ Y = X Y = X (textook) not (Y , X) (Verilog)

NOT: 

NOT X ~X ~~X = X X ~X ~~X 0 1 0 1 0 1

AND Gate: 

AND Gate AND X Y Z Z = X & Y X Y Z 0 0 0 0 1 0 1 0 0 1 1 1

AND: 

AND X & Y (Verilog and ABEL) X and Y (VHDL) X Y X Y X * Y XY (textbook) and ( Z,X,Y) ( Verilog) U V

OR Gate: 

OR Gate OR X Y Z Z = X | Y X Y Z 0 0 0 0 1 1 1 0 1 1 1 1

OR: 

OR X | Y (Verilog) X # Y (ABEL) X or Y (VHDL) X + Y (textbook) X V Y X U Y or ( Z,X,Y) (Verilog)

Basic Logic Gates and Basic Digital Design: 

Basic Logic Gates and Basic Digital Design NOT, AND, and OR Gates NAND and NOR Gates DeMorgan’s Theorem Exclusive-OR (XOR) Gate Multiple-input Gates

NAND Gate: 

NAND Gate NAND X Y Z X Y Z 0 0 1 0 1 1 1 0 1 1 1 0 Z = ~(X & Y) nand (Z,X,Y)

NAND Gate: 

NAND Gate NOT-AND X Y Z W = X & Y Z = ~W = ~(X & Y) X Y W Z 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 W

NOR Gate: 

NOR Gate NOR X Y Z X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 Z = ~(X | Y) nor (Z,X,Y)

NOR Gate: 

NOR Gate NOT-OR X Y W = X | Y Z = ~W = ~(X | Y) X Y W Z 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 0 Z W

Basic Logic Gates and Basic Digital Design: 

Basic Logic Gates and Basic Digital Design NOT, AND, and OR Gates NAND and NOR Gates DeMorgan’s Theorem Exclusive-OR (XOR) Gate Multiple-input Gates

NAND Gate: 

NAND Gate X Y X Y Z Z Z = ~(X & Y) Z = ~X | ~Y = X Y W Z 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 X Y ~X ~Y Z 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 0

De Morgan’s Theorem-1: 

De Morgan’s Theorem-1 ~(X & Y) = ~X | ~Y NOT all variables Change & to | and | to & NOT the result

NOR Gate: 

NOR Gate X Y Z Z = ~(X | Y) X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 X Y Z Z = ~X & ~Y X Y ~X ~Y Z 0 0 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0

De Morgan’s Theorem-2: 

De Morgan’s Theorem-2 ~(X | Y) = ~X & ~Y NOT all variables Change & to | and | to & NOT the result

De Morgan’s Theorem: 

De Morgan’s Theorem NOT all variables Change & to | and | to & NOT the result -------------------------------------------- ~X | ~Y = ~(~~X & ~~Y) = ~(X & Y) ~(X & Y) = ~~(~X | ~Y) = ~X | ~Y ~X & !Y = ~(~~X | ~~Y) = ~(X | Y) ~(X | Y) = ~~(~X & ~Y) = ~X & ~Y

Basic Logic Gates and Basic Digital Design: 

Basic Logic Gates and Basic Digital Design NAND and NOR Gates DeMorgan’s Theorem Exclusive-OR (XOR) Gate Multiple-input Gates

Exclusive-OR Gate: 

Exclusive-OR Gate X Y Z XOR X Y Z 0 0 0 0 1 1 1 0 1 1 1 0 Z = X ^ Y xor ( Z,X,Y)

XOR: 

XOR X ^ Y (Verilog) X $ Y (ABEL) X @ Y xor ( Z,X,Y) (Verilog)

Exclusive-NOR Gate: 

Exclusive-NOR Gate X Y Z XNOR X Y Z 0 0 1 0 1 0 1 0 0 1 1 1 Z = ~(X ^ Y) Z = X ~^ Y xnor ( Z,X,Y)

XNOR: 

XNOR X ~^ Y (Verilog) (X $ Y) (ABEL) xnor ( Z,X,Y) (Verilog)

Basic Logic Gates and Basic Digital Design: 

Basic Logic Gates and Basic Digital Design NOT, AND, and OR Gates NAND and NOR Gates DeMorgan’s Theorem Exclusive-OR (XOR) Gate Multiple-input Gates

Multiple-input Gates: 

Multiple-input Gates Z 1 2 3 4 Z Z Z

Multiple-input AND Gate: 

Multiple-input AND Gate Z 1 Output is HIGH only if all inputs are HIGH Z 1 An open input will float HIGH

Multiple-input OR Gate: 

Multiple-input OR Gate Output is LOW only if all inputs are LOW Z 2 2 Z

Multiple-input NAND Gate: 

Multiple-input NAND Gate Output is LOW only if all inputs are HIGH Z 3 3 Z

Multiple-input NOR Gate: 

Multiple-input NOR Gate Output is HIGH only if all inputs are LOW Z 4 4 Z