INTRODUCTION :
INTRODUCTION BERT or Bit Error Rate Test
BERT patterns
Need of BERT
Existing System :
Existing System Logic Gates
PROPOSED SYSTEM
BERT : High Performance Maximize The Error Removal
System Structure :
OUTPUT System Structure
Slide 5:
SOFTWARE USED ALTERA MAX+PLUS II This MAX+PLUS II software is used to implement the BERT programming code ALTERA reserves the right to make changes without notice in the devices or the device specification identified in this document
Slide 6:
HARDWARE USED FPGA (FIELD PROGRAMMABLE GATE ARRAY) ALTERA FLEX 10K C30:
FLEX means (FLEXIBLE LOGIC ELEMENT MATRIX) architecture incorporates all features necessary to implement common gate array mega functions with up to 250,000 gates the FLEX 10K family provides density, speed and features to integrate entire systems.