seminar on Chameleon Chip


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Presentation Transcript

Chameleon Chip : 

Chameleon Chip By, Rakesh Kashyap . R 0925924 MCA 3rd Sem

Preface : 

Preface Advantages: very high performance and efficient Disadvantages: not flexible (can’t be altered after fabrication) expensive Advantages: software is very flexible to change Disadvantages: performance can suffer if clock is not fast fixed instruction set by hardware Advantages: fills the gap between hardware and software much higher performance than software higher level of flexibility than ASIC’s

Building blocks of a Digital Circuit : 

Conductors vs. Semiconductors Periodic Table Semiconductors Intrinsic SC Extrinsic SC P type N type Building blocks of a Digital Circuit

Energy bands : 

Energy bands

Silicon atomic structure : 

Silicon atomic structure

Intrinsic and Extrinsic lattice : 

Intrinsic and Extrinsic lattice

Building blocks of a Digital Circuit : 

Junction Theory Diode Biasing p-n junction Building blocks of a Digital Circuit

Biasing p-n junction : 

Biasing p-n junction

Building blocks of a Digital Circuit : 

Bipolar Junction Transistor How does a transistor work? Biasing a transistor Characteristics of a transistor (regions) Building blocks of a Digital Circuit

Characteristics of a transistor : 

Characteristics of a transistor

Application-specific integrated circuit : 

An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use For example, a chip designed solely to run a cell phone is an ASIC. Designers of digital ASICs use a hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs. Application-specific integrated circuit

Field-programmable gate array : 

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing. FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be wired together. Field-programmable gate array


COPACOBANA, the Cost-Optimized Parallel COde Breaker, is an FPGA-based machine which is optimized for running cryptanalytical algorithms. COPACOBANA is suitable for parallel computation problems which have low communication requirements. DES cracking is such a parallelizable problem: an exhaustive key search of the Data Encryption Standard (DES) takes no longer than a week on average with COPACOBANA. FPGA example COPACOBANA

Slide 19: 

128 Virtex-4 SX 35 FPGAs brute-force attack against DES cracked in 7 days


Uses 28 Spartan-3 5000 FPGA’s RIVYERA Data Encryption Standard (DES) was cracked in just 22 hours and 15 minutes.

Cchameleon Processors : 

A chameleon processor is a reconfigurable microprocessor with erasable hardware that can rewire itself dynamically. This allows the chip to adapt effectively to the programming tasks demanded by the particular software they are interfacing with at any given time. Reconfigurable processor usually contains several parallel processing computational units known as functional blocks. While reconfiguring the chip, the connections inside the functional blocks and the connections in between the functional blocks are changing, that means when a particular software is loaded the present hardware design is erased and a new hardware design is generated by making a particular number of connections active while making others idle. Cchameleon Processors

Continued… : 

This will define the optimum hardware configuration for that particular software. It takes just 20 microseconds to reconfigure the entire processing array. Reconfigurable processors are currently available from Chameleon Systems, Billions of Operations (BOPS), and PACT (Parallel Array Computing Technology). Among those only Chameleon is providing a design environment, which allows customers to convert their algorithms to hardware configuration by themselves. Continued…

Multifunction Implementation : 

In a conventional ASIC or FPGA, multiple algorithms are implemented as separate hardware modules. Four algorithms would divide the chip into four functional areas. With Reconfigurable Technology, many algorithms are loaded into the entire reconfigurable Fabric one at a time. So finally the result is: much higher performance, lower cost and lower power consumption Multifunction Implementation

Traditional Processor Vs RCP : 

Traditional Processor Vs RCP

Architecture : 


Die map of CS2112 : 

Die map of CS2112

Continued… : 

32-bit RISC processor @125MHz 64 bit memory controller 32 bit PCI controller reconfigurable processing fabric (RPF) high speed system bus programmable I/O (160 pins) DMA(Direct Mem Access) Subsystem Configuration Subsystem Continued…

Continued… : 


Reconfigurable Processing Fabric(R P F) : 

The Fabric provides unmatched algorithmic computation power to Chameleon Chip. It consists of 84,32-bit Data path Units 24, 16×24-bit Multipliers Operating at 125Mhz, they provide up to 3,000 16-bit Million Multiply-Accumulates Per Second 24,000, 16-bit Million Operations Per Second. The fabric is divided into Slices, the basic unit of reconfiguration. The CS2112 has 4 Slices with 3 Tiles in each. Each tile can be reconfigured at runtime Tiles contain : Datapath Units Local Store Memories 16x24 multipliers Control Logic Unit Reconfigurable Processing Fabric(R P F)

Data Path Unit (DPU) : 

Data Path Unit (DPU)

Dynamic Interconnect : 

Dynamic Interconnect

Programmable I/O : 

These chips includes banks of Programmable I/O (PIO) pins which provide tremendous bandwidth. Each Programmable I/O bank (ie each slice) of 40 Programmable I/O pins delivers 0.5 GBytes/sec I/O bandwidth. Totally 2GBytes/sec aggregate I/O bandwidth is available from all the slices. These PIO banks can provide interface and handshaking signals for SRAM, A/D, D/A, FPGA and other devices. Programmable I/O

Technologies Used In Chip : 

eCONFIGURABLE™ TECHNOLOGY: This technology reconfigures fabric in one clock cycle and increases voice/data/video channels per chip. As mentioned earlier, each Slice can be configured independently. Loading the Background Plane from external memory requires just 3 µsec per Slice; this operation does not interfere with active processing on the Fabric. Swapping the Background Plane into the Active Plane requires just one clock cycle. with eConfigurable Technology; Technologies Used In Chip

Example of reconfiguration : 

Example of reconfiguration

Continued… : 

C~SIDE Development Tools : With this software development tool , Chameleon Systems are providing the ability for the customers to do the programming themselves thus keeping the secrecy of their algorithms. The Chameleon Systems Integrated Development Environment (C~SIDE) is a complete toolkit for designing, debugging and verifying RCP designs. C~Side uses a combined C language and Verilog flow to map algorithms into the chip’s reconfigurable processing fabric (RPF). Continued…

Design Process : 

Design Process

Continued… : 

eBIOS (eConfigurable Basic I/O Services ):  It provides a interface between the Embedded Processor System and the Fabric. eBIOS provides resource allocation, configuration management and DMA services. The eBIOS calls are automatically generated at compile time, but can be edited for precise control of any function. Continued…

Comparison With Other Technologies : 

Today’s system architects have at their disposal an arsenal of highly integrated, high-performance semiconductor technologies, such as application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), digital signal processors (DSPs), and field-programmable gate arrays (FPGAs). However, system architects continue to struggle with the requirement that communication systems deliver both performance and flexibility. Enter the reconfigurable processor, an entirely new category of semiconductor solution that serves as a system-level platform for a broad range of applications. Comparison With Other Technologies

Advantages : 

can create customized communications signal processors increased performance and channel count can more quickly adapt to new requirements and standards lower development costs and reduce risk. Reducing power Reducing manufacturing cost. Advantages

Disadvantages : 

Inertia – Engineers slow to change Inertia is the worst problem facing reconfigurable computing  RCP designs requires comprehensive set of tools 'Learning curve' for designers unfamiliar with reconfigurable logic Disadvantages

Applications : 

Wireless Base stations The reconfigurable technology mainly focuses on base stations and their unpredictable combination of voice and data-traffic. Base-station infrastructure will have to be adaptive enough to accommodate those requirements. With a fixed processor the channels must be able to support both simple voice calls and high-bandwidth data connections Wireless Local Loop (WLL) Reconfigurable technology is widely applied in Wireless Local Loops also because of their high processing power, bandwidth and reconfigurable nature. High-Performance DSL (Digital Subscriber Line Technology) DSL technology brings high Bandwidth to homely users. Software-Defined Radio (SDR) SDR concept is applied in Cell phone Technology Applications

Conclusion : 

These new chips called chameleon chips are able to rewire themselves on the fly to create the exact hardware needed to run a piece of software at the outmost speed. Its applications are in, data-intensive Internet, DSP, wireless base-stations, voice compression, software-defined radio, high-performance embedded telecom and datacom applications, xDSL concentrators, fixed wireless local loop, multichannel voice compression, multiprotocol packet and cell processing protocols. Its advantages are that it can create customized communications signal processors ,it has increased performance and channel count, and it can more quickly adapt to new requirements and standards and it has lower development costs and reduce risk. Conclusion

Slide 46: 


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