Slide 2:
Basic process of DMA For 8088 in maximum mode: The RQ/GT1 and RQ/GT0 pins are used to issue DMA request and receive acknowledge signals. Sequence of events of a typical DMA process 1) Peripheral asserts one of the request pins, e.g. RQ/GT1 or RQ/GT0 (RQ/GT0 has higher priority) 2) 8088 completes its current bus cycle and enters into a HOLD state 3) 8088 grants the right of bus control by asserting a grant signal via the same pin as the request signal. 4) DMA operation starts 5) Upon completion of the DMA operation, the peripheral asserts the request/grant pin again to relinquish bus control. For 8088 in minimum mode: The HOLD and HLDA pins are used instead to receive and acknowledge the hold request respectively. Normally the CPU has full control of the system bus. In a DMA operation, the peripheral takes over bus control temporarily.
Slide 3:
DMA controller A DMA controller interfaces with several peripherals that may request DMA. The controller decides the priority of simultaneous DMA requests communicates with the peripheral and the CPU, and provides memory addresses for data transfer. DMA controller commonly used with 8088 is the 8237 programmable device. The 8237 is in fact a special-purpose microprocessor. Normally it appears as part of the system controller chip-sets. The 8237 is a 4-channel device. Each channel is dedicated to a specific peripheral device and capable of addressing 64 K bytes section of memory.