Microprocessor Interfacing Basics

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Introduction to 8086 I/O Interfacing Suresh P. Nair [ME, (PhD)] MIEEE Professor & Head Department of Electronics and Communication Engineering Royal College of Engineering and Technology Chiramanangad PO, Akkikkavu, Thrissur, Kerala, India

PowerPoint Presentation:

Suresh.P.Nair , HOD - ECE , RCET 2 8086 Interfacing Basics

Topics:

Topics I/O Interfacing Basics I/O space I/O interfaces I/O interfacing circuits Hand shaking Serial and Parallel interfacing Address decoding 8086 Interfacing Basics Suresh.P.Nair , HOD - ECE , RCET 3 FROM 1 ST MODULE FROM 2 ND MODULE

Basic I/O Architecture:

Basic I/O Architecture Suresh.P.Nair , HOD - ECE , RCET 4 8086 Interfacing Basics

8086 Memory and I/O Address Spaces:

8086 Memory and I/O Address Spaces Suresh.P.Nair , HOD - ECE , RCET 5 8086 Interfacing Basics

I/O space:

I/O space Suresh.P.Nair , HOD - ECE , RCET 6 8086 Interfacing Basics

Interfacing Configurations:

Interfacing Configurations 2 Types Memory mapped I/O I/O mapped I/O (Isolated I/O) 8086 Interfacing Basics Suresh.P.Nair , HOD - ECE , RCET 7

Interfacing Configurations:

Interfacing Configurations 8086 Interfacing Basics Suresh.P.Nair , HOD - ECE , RCET 8 Isolated I/O: uses the dedicated I/O instructions ( IN, OUT and INS, OUTS) and has its own address space for I/O ports (0000H-FFFFH), isolated from the memory address space. Memory mapped I/O: uses memory reference instructions (e.g. MOV). So address space is shared between memory and I/O (used by only one of them). Both techniques can be used with Intel processors. But most Intel-based systems use isolated I/O.

PowerPoint Presentation:

Isolated I/O Using dedicated I/O instructions e.g. IN, OUT b. Memory-mapped I/O Using ordinary memory transfer instructions e.g . MOV 64 K I/O bytes Range of memory addresses assigned for I/O transfers Memory : MOV I/O : IN Memory MOV

Memory Mapped I/O:

Memory Mapped I/O Suresh.P.Nair , HOD - ECE , RCET 10 8086 Interfacing Basics

Isolated I/O:

Isolated I/O Suresh.P.Nair , HOD - ECE , RCET 11 8086 Interfacing Basics

Isolated I/O:

Isolated I/O Suresh.P.Nair , HOD - ECE , RCET 12 8086 Interfacing Basics I/O devices are treated separately from memory Address 0000 to 00FF is referred to page 0 . Special instructions exist for this address range Byte wide ports Word wide ports

Isolated I/O:

Isolated I/O Suresh.P.Nair , HOD - ECE , RCET 13 8086 Interfacing Basics The most common I/O transfer technique used in the Intel-based system is isolated I/O. Isolated describes how I/O locations are isolated from memory in a separate I/O address space Addresses for isolated I/O devices, called ports , are separate from memory. Because the ports are separate, the user can expand the memory to its full size without using any of memory space for I/O devices.

Memory-Mapped I/O :

Memory-Mapped I/O Memory-mapped I/O does not use the IN or OUT instructions. It uses any instruction that transfers data between the microprocessor and memory. treated as a memory location in memory map Advantage is any memory transfer instruction can access the I/O device. Disadvantage is a portion of memory system is used as the I/O map. reduces memory available to applications 8086 Interfacing Basics Suresh.P.Nair , HOD - ECE , RCET 14

Input / Output Data Instructions:

Input / Output Data Instructions Suresh.P.Nair , HOD - ECE , RCET 15 8086 Interfacing Basics

Isolated I/O:

Isolated I/O Suresh.P.Nair , HOD - ECE , RCET 16 8086 Interfacing Basics To write the data 00H into Output port 62H: MOV AL,00H OUT 62H,AL or MOV AL,00H MOV DX,62H OUT DX,AL To read a byte from Input port address 71H: IN AL,71H or MOV DX,71H IN AL,DX

I/O interfaces :

I/O interfaces Memory mapped I/O Interface Minimum Mode Maximum Mode I/O mapped I/O (Isolated I/O) Interface Minimum Mode Maximum Mode

Memory mapped I/O Interface:

Memory mapped I/O Interface Minimum Mode Maximum Mode Same as interfacing 8086 memory in Minimum Mode and Maximum Mode 8086 Interfacing Basics Suresh.P.Nair , HOD - ECE , RCET 18

I/O mapped I/O (Isolated I/O) Interface:

I/O mapped I/O (Isolated I/O) Interface Suresh.P.Nair , HOD - ECE , RCET 19 8086 Interfacing Basics Minimum-mode interface

I/O mapped I/O (Isolated I/O) Interface:

I/O mapped I/O (Isolated I/O) Interface Suresh.P.Nair , HOD - ECE , RCET 20 8086 Interfacing Basics Maximum-mode interface

Input / Output Bus Cycles:

Input / Output Bus Cycles Suresh.P.Nair , HOD - ECE , RCET 21 8086 Interfacing Basics Output bus cycle of the 8086

Input / Output Bus Cycles:

Input / Output Bus Cycles Suresh.P.Nair , HOD - ECE , RCET 22 8086 Interfacing Basics Input bus cycle of the 8086

I/O Interfacing CIRCUITS:

I/O Interfacing CIRCUITS Suresh.P.Nair , HOD - ECE , RCET 23 8086 Interfacing Basics

Basic Input Interface:

Basic Input Interface Suresh.P.Nair , HOD - ECE , RCET 24 8086 Interfacing Basics

Basic Output Interface:

Basic Output Interface Suresh.P.Nair , HOD - ECE , RCET 25 8086 Interfacing Basics

Hand shaking:

Hand shaking Many I/O devices accept or release information slower than the microprocessor. A method of I/O control called handshaking or polling , synchronizes the I/O device with the microprocessor. An example is a parallel printer that prints a few hundred characters per second (CPS). The processor can send data much faster . a way to slow the microprocessor down to match speeds with the printer must be developed 8086 Interfacing Basics Suresh.P.Nair , HOD - ECE , RCET 26

Hand shaking:

Hand shaking I/O synchronization is achieved by implementing what is known as handshaking as part of the input/output interface. E.g. - Parallel printer interface 8086 Interfacing Basics Suresh.P.Nair , HOD - ECE , RCET 27

I/O interface that employs handshaking:

I/O interface that employs handshaking Suresh.P.Nair , HOD - ECE , RCET 28 8086 Interfacing Basics The software polls or tests the BUSY pin to decide whether the printer is busy. If the printer is busy , the processor waits. If not , the next ASCII character goes to the printer. This process of interrogating the printer, or any asynchronous device like a printer, is called handshaking or polling .

Handshake sequence flowchart:

Handshake sequence flowchart Suresh.P.Nair , HOD - ECE , RCET 29 8086 Interfacing Basics

Serial and Parallel interfacing:

Serial and Parallel interfacing 8086 Interfacing Basics Suresh.P.Nair , HOD - ECE , RCET 30

I/O Port Address Decoding:

I/O Port Address Decoding Very similar to memory address decoding , especially for memory-mapped I/O devices. The difference between memory decoding and isolated I/O decoding is the number of address pins connected to the decoder. In the personal computer system, we always decode all 16 bits of the I/O port address. 8086 Interfacing Basics Suresh.P.Nair , HOD - ECE , RCET 31

Decoding 8-Bit I/O Port Addresses:

Decoding 8-Bit I/O Port Addresses Fixed I/O instruction uses an 8-bit I/O port address that on A 15 –A 0 as 0000H–00FFH . we often decode only address connections A 7 –A 0 for an 8-bit I/O port address The DX register can also address I/O ports 00H–FFH . If the address is decoded as an 8-bit address, we can never include I/O devices using a 16-bit address. 8086 Interfacing Basics Suresh.P.Nair , HOD - ECE , RCET 32

Decoding 8-Bit I/O Port Addresses:

Decoding 8-Bit I/O Port Addresses Figure below shows a 74ALS138 decoder that decodes 8-bit I/O ports F0H - F7H . identical to a memory address decoder except we only connect address bits A 7 –A 0 to the inputs of the decoder 8086 Interfacing Basics Suresh.P.Nair , HOD - ECE , RCET 33

Decoding 16-Bit I/O Port Addresses:

Decoding 16-Bit I/O Port Addresses The difference between decoding an 8-bit and a 16-bit I/O address is that 8 additional address lines (A 15 –A 8 ) must be decoded. Figure shown illustrates a circuit that contains a PLD and a 4-input NAND gate used to decode I/O ports EFF8H–EFFFH. PLD generates address strobes for I/O ports. 8086 Interfacing Basics Suresh.P.Nair , HOD - ECE , RCET 34

8- and 16-bit I/O Ports:

8- and 16-bit I/O Ports Suresh.P.Nair , HOD - ECE , RCET 35 8086 Interfacing Basics

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