Intel 8086 Software

INTEL 8086 Software & Hardware Architecture : 

INTEL 8086 Software & Hardware Architecture Suresh P. Nair [ME, (PhD)] MIEEE Professor & Head Department of Electronics and Communication Engineering Royal College of Engineering and Technology Chiramanangad PO, Akkikkavu, Thrissur, Kerala, India

MODULE 1 & 2 : 

MODULE 1 & 2 Complete idea about INTEL 8086 Microprocessor

Topics to be covered: 

Topics to be covered Software Architecture of the INTEL 8086. Hardware Architecture of INTEL 8086. 8086 Programming and program development. RCET Microprocessor & Microcontroller 3

Software architecture of the INTEL 8086: 

Software architecture of the INTEL 8086 Memory segmentation and addressing Block diagram of 8086 Address space & Data organization Data Types Registers Stack I/O space RCET Microprocessor & Microcontroller 4

Hardware Architecture of INTEL 8086: 

Hardware Architecture of INTEL 8086 Pin Diagram and Pin Details min/max mode Coprocessor and Multiprocessor configuration Hardware organization of address space Control signals I/O interfaces RCET Microprocessor & Microcontroller 5

8086 programming and program development.: 

8086 programming and program development. Assembly Language Programming. Instruction Set. Assembler Directives. Programming Exercises. RCET Microprocessor & Microcontroller 6

Software Architecture of INTEL 8086: 

Software Architecture of INTEL 8086 RCET Microprocessor & Microcontroller 7

Software architecture of the INTEL 8086: 

Software architecture of the INTEL 8086 Memory segmentation and addressing Block diagram of 8086 Address space & Data organization Data Types Registers Stack I/O space RCET Microprocessor & Microcontroller 8

Memory segmentation and addressing: 

Memory segmentation and addressing Von – Newman architecture & Harvard architecture Program Memory & Data Memory Need for Segmentation To implement Harvard architecture Easy to debug Same Interfacing ICs can be used To avoid overlap of stack with normal memory Compatible with 8085 RCET Microprocessor & Microcontroller 9

Segmented Memory: 

Segmented Memory RCET Microprocessor & Microcontroller 10

Memory Address Generation: 

Memory Address Generation The BIU has a dedicated adder for determining physical memory addresses. RCET Microprocessor & Microcontroller 11 Physical Address (20 Bits) Adder Segment Register (16 bits) 0 0 0 0 Offset Value (16 bits)

Segment : Offset Address: 

Segment : Offset Address Logical Address is specified as segment:offset Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address. Thus the physical address of the logical address A4FB:4872 is: A4FB0 + 4872 A9822 RCET Microprocessor & Microcontroller 12

Segments, Segment Registers & Offset Registers: 

Segments, Segment Registers & Offset Registers Segment Size = 64KB Maximum number of segments possible = 14 Logical Address – 16 bits Physical Address – 20 bits 2 Logical Addresses for each Segments. Base Address (16 bits) Offset Address (16 bits) Segment registers are used to store the Base address of the segment. RCET Microprocessor & Microcontroller 13

Segments, Segment Registers & Offset Registers: 

Segments, Segment Registers & Offset Registers 4 Segments in 8086 Code Segment (CS) Data Segment (DS) Stack Segment (SS) Extra Segment (ES) RCET Microprocessor & Microcontroller 14 SEGMENT SEGMENT REGISTER OFFSET REGISTER Code Segment CSR Instructio n Pointer (IP) Data Segment DSR Source Index (SI) Extra Segment ESR Destination Index (DI) Stack Segment SSR Stack Pointer (SP) / Base Pointer (BP)

Block diagram of 8086: 

Block diagram of 8086 RCET Microprocessor & Microcontroller 15

Block diagram of 8086: 

Block diagram of 8086 RCET Microprocessor & Microcontroller 16

Pipelined architecture of the 8086 microprocessors: 

Pipelined architecture of the 8086 microprocessors RCET Microprocessor & Microcontroller 17

Execution and bus interface units: 

Execution and bus interface units RCET Microprocessor & Microcontroller 18

Software Model of the 8086 Microprocessors: 

Software Model of the 8086 Microprocessors RCET Microprocessor & Microcontroller 19

Address space & Data organization: 

Address space & Data organization RCET Microprocessor & Microcontroller 20 Memory address space Storing a word in memory What is the word in (b) in Hex?

Aligned and misaligned data word: 

Aligned and misaligned data word RCET Microprocessor & Microcontroller 21

Aligned and misaligned double words of data: 

Aligned and misaligned double words of data RCET Microprocessor & Microcontroller 22

Storing double word in memory: 

Storing double word in memory RCET Microprocessor & Microcontroller 23

Data Types: 

Data Types RCET Microprocessor & Microcontroller 24 Unsigned word integer 0 – 65,535 Unsigned byte integer 0 - 255

Data Types: 

Data Types RCET Microprocessor & Microcontroller 25 Signed integers -128 - +127 -32,768 - +32,767

Data Types: 

Data Types RCET Microprocessor & Microcontroller 26 Binary Coded Decimal (BCD) Unpacked BCD Packed BCD

American Standard Code for Information Interchange (ASCII): 

American Standard Code for Information Interchange (ASCII) RCET Microprocessor & Microcontroller 27

Dedicated, Reserved, and General use Memory: 

Dedicated, Reserved, and General use Memory RCET Microprocessor & Microcontroller 28

8086 Registers: 

8086 Registers RCET Microprocessor & Microcontroller 29

General Purpose Registers: 

General Purpose Registers Normally used for storing temporary results Each of the registers is 16 bits wide (AX, BX, CX, DX) Can be accessed as either 16 or 8 bits AX, AH, AL RCET Microprocessor & Microcontroller 30 AX - the Accumulator BX - the Base Register CX - the Count Register DX - the Data Register

General Purpose Registers: 

General Purpose Registers AX Accumulator Register Preferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language Code Must be used in multiplication and division operations Must also be used in I/O operations BX Base Register Also serves as an address register RCET Microprocessor & Microcontroller 31

General Purpose Registers: 

General Purpose Registers CX Count register Used as a loop counter Used in shift and rotate operations DX Data register Used in multiplication and division Also used in I/O operations RCET Microprocessor & Microcontroller 32

Pointer and Index Registers: 

Pointer and Index Registers All 16 bits wide, L/H bytes are not accessible Used as memory pointers Example: MOV AH, [SI] Move the byte stored in memory location whose address is contained in register SI to register AH IP is not under direct control of the programmer RCET Microprocessor & Microcontroller 33

Flag Register: 

Flag Register RCET Microprocessor & Microcontroller 34 Carry Parity Auxiliary Carry Zero Overflow Direction Interrupt enable Trap Sign 6 are status flags 3 are control flag

8086 Programmer’s Model: 

8086 Programmer’s Model RCET Microprocessor & Microcontroller 35 ES CS SS DS IP AH BH CH DH AL BL CL DL SP BP SI DI FLAGS AX BX CX DX Extra Segment Code Segment Stack Segment Data Segment Instruction Pointer Accumulator Base Register Count Register Data Register Stack Pointer Base Pointer Source Index Register Destination Index Register BIU registers (20 bit adder) EU registers

The Stack: 

The Stack The stack is used for temporary storage of information such as data or addresses. When a CALL is executed, the 8086 automatically PUSH es the current value of CS and IP onto the stack. Other registers can also be pushed Before return from the subroutine , POP instructions can be used to pop values back from the stack into the corresponding registers. RCET Microprocessor & Microcontroller 36

The Stack: 

The Stack RCET Microprocessor & Microcontroller 37

Example for PUSH: 

Example for PUSH RCET Microprocessor & Microcontroller 38

Example for POP: 

Example for POP RCET Microprocessor & Microcontroller 39

The I/O address space: 

The I/O address space RCET Microprocessor & Microcontroller 40

Hardware Architecture of INTEL 8086: 

Hardware Architecture of INTEL 8086 RCET Microprocessor & Microcontroller 41

Hardware Architecture of INTEL 8086: 

Hardware Architecture of INTEL 8086 Pin Diagram and Pin Details min/max mode Hardware organization of address space Control signals Coprocessor and Multiprocessor configuration I/O interfaces RCET Microprocessor & Microcontroller 42

INTEL 8086 - Pin Diagram: 

INTEL 8086 - Pin Diagram RCET Microprocessor & Microcontroller 43

INTEL 8086 - Pin Details: 

INTEL 8086 - Pin Details RCET Microprocessor & Microcontroller 44 Ground Clock Duty cycle: 33% Power Supply 5V  10% Reset Registers, seg regs, flags CS: FFFFH, IP: 0000H If high for minimum 4 clks

INTEL 8086 - Pin Details: 

INTEL 8086 - Pin Details RCET Microprocessor & Microcontroller 45 Address/Data Bus: Contains address bits A 15 -A 0 when ALE is 1 & data bits D 15 – D 0 when ALE is 0. Address Latch Enable: When high, multiplexed address/data bus contains address information.

INTEL 8086 - Pin Details: 

INTEL 8086 - Pin Details RCET Microprocessor & Microcontroller 46 INTERRUPT Non - maskable interrupt Interrupt request Interrupt acknowledge

INTEL 8086 - Pin Details: 

INTEL 8086 - Pin Details RCET Microprocessor & Microcontroller 47 Direct Memory Access Hold acknowledge Hold

INTEL 8086 - Pin Details: 

INTEL 8086 - Pin Details RCET Microprocessor & Microcontroller 48 Address/Status Bus Address bits A 19 – A 16 & Status bits S 6 – S 3

INTEL 8086 - Pin Details: 

INTEL 8086 - Pin Details RCET Microprocessor & Microcontroller 49 Bus High Enable/S7 Enables most significant data bits D 15 – D 8 during read or write operation. S 7 : Always 1. BHE#, A 0 : 0,0 : Whole word (16-bits) 0,1: High byte to/from odd address 1,0: Low byte to/from even address 1,1: No selection

INTEL 8086 - Pin Details: 

INTEL 8086 - Pin Details RCET Microprocessor & Microcontroller 50 Min/Max mode Minimum Mode: +5V Maximum Mode: 0V Minimum Mode Pins Maximum Mode Pins

Minimum Mode- Pin Details: 

Microprocessor & Microcontroller Minimum Mode- Pin Details RCET 51 Read Signal Write Signal Memory or I/0 Data Bus Enable Data Transmit/Receive

Maximum Mode - Pin Details: 

Maximum Mode - Pin Details RCET Microprocessor & Microcontroller 52 Status Signal Inputs to 8288 to generate eliminated signals due to max mode. S2 S1 S0 000: INTA 001: read I/O port 010: write I/O port 011: halt 100: code access 101: read memory 110: write memory 111: none - passive

Maximum Mode - Pin Details: 

Maximum Mode - Pin Details RCET Microprocessor & Microcontroller 53 DMA Request/Grant Lock Output Lock Output Used to lock peripherals off the system Activated by using the LOCK: prefix on any instruction

Maximum Mode - Pin Details: 

Maximum Mode - Pin Details RCET Microprocessor & Microcontroller 54 Queue Status Used by numeric coprocessor (8087) QS1 QS0 00: Queue is idle 01: First byte of opcode 10: Queue is empty 11: Subsequent byte of opcode

Minimum Mode 8086 System: 

Minimum Mode 8086 System RCET Microprocessor & Microcontroller 55

Minimum Mode 8086 System: 

Minimum Mode 8086 System RCET Microprocessor & Microcontroller 56

‘Read’ Cycle timing Diagram for Minimum Mode: 

‘Read’ Cycle timing Diagram for Minimum Mode RCET Microprocessor & Microcontroller 57

‘Write’ Cycle timing Diagram for Minimum Mode: 

‘Write’ Cycle timing Diagram for Minimum Mode RCET Microprocessor & Microcontroller 58

Maximum Mode 8086 System : 

Maximum Mode 8086 System RCET Microprocessor & Microcontroller 59

Maximum Mode 8086 System : 

Maximum Mode 8086 System RCET Microprocessor & Microcontroller 60

Maximum Mode 8086 System : 

Maximum Mode 8086 System Here, either a numeric coprocessor of the type 8087 or another processor is interfaced with 8086. The Memory, Address Bus, Data Buses are shared resources between the two processors. The control signals for Maximum mode of operation are generated by the Bus Controller chip 8788. The three status outputs S0*, S1*, S2* from the processor are input to 8788. The outputs of the bus controller are the Control Signals, namely DEN, DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE etc. RCET Microprocessor & Microcontroller 61

Memory Read timing in Maximum Mode: 

Memory Read timing in Maximum Mode RCET Microprocessor & Microcontroller 62

Memory Write timing in Maximum Mode: 

Memory Write timing in Maximum Mode RCET Microprocessor & Microcontroller 63

Memory Banking: 

Memory Banking RCET Microprocessor & Microcontroller 64

Interface 8086 to 6116 Static RAM: 

65 Interface 8086 to 6116 Static RAM 8086 A ____BHE ALE A ( 10-0 ) D ( 7-0 ) __ R/W OE* CS* A ( 10-0 ) __ R/W OE* CS* D D ( 7-0 ) 20 Latch Addr Decoder A ( 11 - 1 ) 21 A 0 , BHE * A ( 19 - 12 ) A ( 11-1 ) __ M/IO ___ RD ___ WR Low byte (Even Bank) D ( 7-0 ) D ( 15 - 8 ) 16 A 0 RAMCS* MEM* BHE* 6116 (2K x8) High byte (Odd Bank)

8086 Interrupts: 

8086 Interrupts RCET Microprocessor & Microcontroller 66

8086 Interrupts Procedure: 

8086 Interrupts Procedure RCET Microprocessor & Microcontroller 67

8086 External Interrupts: 

8086 External Interrupts RCET Microprocessor & Microcontroller 68

8086 Interrupt Vector Table: 

8086 Interrupt Vector Table RCET Microprocessor & Microcontroller 69

8086 Interrupt Vector Table: 

8086 Interrupt Vector Table RCET Microprocessor & Microcontroller 70

Total Memory and IVT: 

Total Memory and IVT RCET Microprocessor & Microcontroller 71

8086 Control Signals: 

8086 Control Signals ALE BHE M/IO DT/R RD WR DEN RCET Microprocessor & Microcontroller 72

Coprocessor and Multiprocessor configuration : 

Coprocessor and Multiprocessor configuration Multiprocessor Systems refer to the use of multiple processors that executes instructions simultaneously and communicate with each other using mail boxes and Semaphores. Maximum mode of 8086 is designed to implement 3 basic multiprocessor configurations: 1. Coprocessor (8087) 2. Closely coupled (8089) 3. Loosely coupled (Multibus) RCET Microprocessor & Microcontroller 73

Coprocessor and Multiprocessor configuration : 

Coprocessor and Multiprocessor configuration Coprocessors and Closely coupled configurations are similar in that both the 8086 and the external processor shares the: - Memory - I/O system - Bus & bus control logic - Clock generator RCET Microprocessor & Microcontroller 74

Coprocessor / Closely Coupled Configuration: 

Coprocessor / Closely Coupled Configuration RCET Microprocessor & Microcontroller 75

TEST pin of 8086: 

TEST pin of 8086 Used in conjunction with the WAIT instruction in multiprocessing environments. This is input from the 8087 coprocessor. During execution of a wait instruction, the CPU checks this signal. If it is low, execution of the signal will continue; if not, it will stop executing. RCET Microprocessor & Microcontroller 76

Coprocessor Execution Example: 

Coprocessor Execution Example Coprocessor cannot take control of the bus, it does everything through the CPU RCET Microprocessor & Microcontroller 77

Closely Coupled Execution Example: 

Closely Coupled Execution Example Closely Coupled processor may take control of the bus independently. Two 8086’s cannot be closely coupled. RCET Microprocessor & Microcontroller 78

Loosely Coupled Configuration: 

Loosely Coupled Configuration has shared system bus, system memory, and system I/O . each processor has its own clock as well as its own memory (in addition to access to the system resources). Used for medium to large multiprocessor systems . Each module is capable of being the bus master . Any module could be a processor capable of being a bus master, a coprocessor configuration or a closely coupled configuration. RCET Microprocessor & Microcontroller 79

Loosely Coupled Configuration: 

Loosely Coupled Configuration No direct connections between the modules. Each share the system bus and communicate through shared resources. Processor in their separate modules can simultaneously access their private subsystems through their local busses, and perform their local data references and instruction fetches independently. This results in improved degree of concurrent processing. Excellent for real time applications, as separate modules can be assigned specialized tasks RCET Microprocessor & Microcontroller 80

Advantages of Multiprocessor Configuration: 

Advantages of Multiprocessor Configuration High system throughput can be achieved by having more than one CPU. The system can be expanded in modular form. Each bus master module is an independent unit and normally resides on a separate PC board. One can be added or removed without affecting the others in the system. A failure in one module normally does not affect the breakdown of the entire system and the faulty module can be easily detected and replaced Each bus master has its own local bus to access dedicated memory or IO devices. So a greater degree of parallel processing can be achieved. RCET Microprocessor & Microcontroller 81

WAIT State: 

WAIT State A wait state (T w ) is an extra clocking period, inserted between T2 and T3 , to lengthen the bus cycle, allowing slower memory and I/O components to respond. The READY input is sampled at the end of T2 , and again, if necessary in the middle of Tw. If READY is ‘0’ then a Tw is inserted. RCET Microprocessor & Microcontroller 82

8086 System Memory Circuitry: 

8086 System Memory Circuitry Minimum Mode System Memory Circuitry Maximum Mode System Memory Circuitry RCET Microprocessor & Microcontroller 83

Minimum Mode System Memory Circuitry: 

Minimum Mode System Memory Circuitry RCET Microprocessor & Microcontroller 84

Maximum Mode System Memory Circuitry: 

Maximum Mode System Memory Circuitry RCET Microprocessor & Microcontroller 85