Multi-Core_Processor-Benchmarking- Mirab

How to measure Multi-Instruction, Multi-Core Processor Performance using Simulation : 

3/30/2009 How to measure Multi-Instruction, Multi-Core Processor Performance using Simulation Deepak Shankar Darryl Koivisto Mirabilis Design Inc.

Mirabilis Design™ : 

3/30/2009 Mirabilis Designã Inc. Confidential Mirabilis Design™ Concept Engineering software and services Founded in 2003 & based in Sunnyvale, USA 19 customers and 18 projects completed Product Two major product-lines: Architect™ and Explorer Third Generation Applications High-performance systems, custom semiconductors and real-time software Comprehensive System Design Software Provider

Trends : 

3/30/2009 Mirabilis Designã Inc. Confidential Trends Semiconductor companies are migrating to 2, 4, 8 multi-instruction, multi-core processors to improve performance, reduce power Processors are migrating from SIMD to MIMD architectures Compute system vendors are packaging multi-processor systems to improve performance, reduce cost Scaling from single processor, single core to multi-processor, multi-core requires more inter-processor communication: Amdahl’s Law of Parallel Computing Many benchmarks are limited to single processor, single core, there is a need for a new methodolgy

Benchmark Challenges : 

3/30/2009 Mirabilis Designã Inc. Confidential Benchmark Challenges Different configurations lead to remarkably different performance and power metrics Multi-Processors vs. Multi-Cores Shared vs. Distributed Caches Communication Bandwidth between Processors/Cores Multi-Threaded applications make benchmarking more difficult How are Applications partitioned: thread per node or application per node How are Applications distributed, controlled Speed of Processors, Memory, Communication is not scaleable in all cases

Multi-Core/Processor Benchmarking Solution : 

3/30/2009 Mirabilis Designã Inc. Confidential Multi-Core/Processor Benchmarking Solution Speedup equations that take into account parallel execution Speedup_Factor, Multi_Instr_Mhz, Multi_Core_Mhz Modeling Platform that supports multi-instruction, multi-core topologies using routing tables Create models for different processor memory, and connectivity configurations Scaleable infrastructure for end-users to experiment with their specific variations Processor Models that support published benchmarks Key parameters, multi-instruction per cycle, shared cache Multiple instances, scriptable pipeline Ability to correlate baseline results to hardware tests Interactive and graphical demonstration of the benchmark results Hundreds of built-in statistics

Speedup Equations : 

3/30/2009 Mirabilis Designã Inc. Confidential Speedup Equations Multi-Instruction                       Single_Instruction_App_Time Speedup_Factor = ----------------------------                    Multi_Instruction_App_Time     Multi_Instr_Mhz =  Single_Instruction_Mhz * Speedup_Factor   Multi-Core                    Single_Core_App_Time                     Speedup_Factor = ---------------------                    Multi_Core_App_Time     Multi_Core_Mhz  =  Single_Core_Mhz * Speedup_Factor   Note: Multi_Core_App_Time assumes time to complete Single_Core_App_Time distributed among N cores plus communication time.

Performance, Power and Functional Exploration : 

3/30/2009 Mirabilis Designã Inc. Confidential Performance, Power and Functional Exploration Idea Discussion Need to design Traffic Mgr -Variable sizes and priority -Over 1000 concurrent port processing Customer Requirements Analysis Bottlenecks Throughput Capacity Golden Reference Architecture Defn. Component Size Function mapping Concept Engineering and Design Optimization

VisualSim Provides : 

3/30/2009 Mirabilis Designã Inc. Confidential VisualSim Provides Graphical and Hierarchical Modeling based on Ptolemy Simulation Engine Modeling blocks to quickly construct a custom/ platform model Mixed abstractions and mixed-signal modeling Over 2000 power, buffering and performance statistics generators built into architecture blocks Interface and Documentation Built-in documentation capability Embedding models in documents for remote execution Wizard for native code (C/C++/Java/RTL/SystemC) Modeling libraries, mixed abstraction and hierarchical development

Multi-Processor Benchmark Model : 

3/30/2009 Mirabilis Designã Inc. Confidential Multi-Processor Benchmark Model

Detailed Benchmark Results : 

3/30/2009 Mirabilis Designã Inc. Confidential Detailed Benchmark Results

Benchmark Drives Business : 

3/30/2009 Mirabilis Designã Inc. Confidential Benchmark Drives Business Use Benchmark for marketing, Product Specification and Early System Prototyping Knowledge Base Auto-Generate Specification Communicate Requirements VisualSim is the Media for Universal Communication Architect Field Support Customer Input Map Requests Graphically Marketing Involved Early in the Design Test & Diagnostics Application Driven selection Customer Decision

Slide 12: 

3/30/2009 Functional, Performance vs. Power Concept Engineering