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Fault Secure Encoder and Decoder for NanoMemory Applications:

Fault Secure Encoder and Decoder for NanoMemory Applications


NANO DEVICES N ANOTECHNOLOGY provides smaller, faster, and lower energy devices which allow more powerful and compact circuitry; however, these benefits come with a cost—the nano scale devices may be less reliable. As a result, we can expect combinational logic to be susceptible to transient faults. Since NANO devices are more faster and faster there may be a chance of more probability to get error percentage.


FAULT TOLERANCE MECHANISM Fault tolerant mechanism means, if even we get a wrong output for a particular device we are going to yield a correct output. In this project we are going to apply a fault tolerant mechanism to ENCODER, MEMORY and DECODER. By applying that tolerant mechanism synchronization between encoder memory and decoder are made.


ABSTRACT In this project we design a fault-tolerant encoder and corrector, where the fault-secure detector monitors their operation. We also presented a unified approach to tolerate permanent defects and transient faults. This unified approach reduces the area overhead. Theoretically, by using syndrome matrix we are going to find, if there are any transition errors or not. From one step majority logic corrector we are going to find out errors and also correcting errors in decoder.


INTRODUCTION Due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and must also be protected So In this project, we introduce a fault-tolerant which tolerates transient faults in the supporting logic of nano memory (i.e., encoder, decoder (corrector), and detector circuitries).


TYPES OF ERRORS Generally errors occurred in circuits are classified in to Soft errors Hard errors Mainly soft errors occurred due transition errors. Hard errors occurred, when any physical failures in the circuit. In this project we are mainly concentrating on soft errors.

Block diagram:

Block diagram Fig. 1. Overview of our proposed fault-tolerant memory architecture, with pipelined corrector.

Block diagram:

Block diagram ENCODER detector INFORMATION VECTOR MEMORY BLOCK Detector One step majority logic corrector Fig: Overview of proposed block diagram

Detection of errors in encoder:

Detection of errors in encoder Low density parity check (LDP) have fault secure detector capability. In this approach we are finding a syndrome matrix (S) to detect errors in encoder. Depend up on the density of the syndrome matrix we can find whether any error occurred or not.


IMPLEMENTATION OF SYNDROME VECTOR S = CH T C = Coded vector (output of the encoder) H= Parity check matrix H = X T I G = IX I= Identity matrix.



Finding ‘X’ matrix::

Finding ‘X’ matrix: For the coded vectors c 0 ,c 1 ,c 2 ,c 3 ,c4,c5,c6 directly inputs are given. For coded vectors c7,c8,c9,c10,c11,c12,c13,c14 The encoder inputs are linearly ex-ored and given to the output. Finally, the ‘x’ matrix is derived.

PowerPoint Presentation:

From above all matrixes SYNDROME matrix is calculated. If Syndrome (s) vector contains all ‘zero’s then the received code word is correct. If it contains any ‘one’, received code word is wrong If any error occurred then immediately detector again intimate to encoder to produce correct coded word. If no error found then it just ignores it.

Detection of errors in decoder:

Detection of errors in decoder One-step majority logic correction is the procedure that identifies the correct value of a each bit in the codeword directly from the received codeword this is in contrast to the general message-passing error correction strategy This method consists of two parts: 1) generating a specific set of linear sums of the received vector bits and 2) finding the majority value of the computed linear sums

One step majority logic structure:

One step majority logic structure Above shown figure corrects, if there any errors in decoder output.

PowerPoint Presentation:

In the above figure denotes row density of the linear sum of XOR gates as shown in above figure. In the above figure denotes majority out put of all four row density values. Out put will be the majority value of row density values. If the final majority value is equal to the c(15) bit output will be ‘0’ else ‘1’.

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Result We identify a specific LDPC code that can tolerate up to 33 errors in each memory word or supporting logic that requires only 30% area overhead for memory blocks of 10 Kbits or larger. Larger codes can achieve even higher reliability and lower area overhead. We quantify the importance of protecting encoder and decoder (corrector) circuitry and illustrate a scenario where the system failure rate (FIT) is dominated by the failure rate of the encoder and decoder.


ADVANTAGES The advantage of using systematic codes is that there is no need for a decoder circuit to extract the information bits. The complexity of operations are very easy by using low density values. Less power consumption Time to market is very less. It takes less cost to construct .


DISADVANTAGES It takes more time to compute all iterations. High fan in majority gate is required . Low fan out in output grabbing. Some how, less secure.


APPLICATIONS In nano memory applications. In high speed feature coming processors. In the BIST applications.


NANO MEMORY APPLICATIONS It is necessary to prepare undergraduate engineering students with an ability to design, analyze and manufacture nanocomponents and nanosystems, to create nanodevices for economically feasible, innovative applications of nanotechnology in all spheres of our daily life.


PROCESSORS Computing involves progress in many areas, data visualization, human-computer interfaces (vision, speech, robotics), mobile applications (wireless and batteries), micro-electron-mechanical-systems (MEMS), and the more prosaic areas of networking, processing, and data storage and access. This talk focuses primarily on these classic areas (processing, storage, networking)


BIST APPLICATIONS. embedded memories are highly programmable and offer the user many options such as selectable word depth and data width. Other modes of operations include built in FIFO support and cascadability with adjacent rams along with several more features. With all of these integrated features, a method for testing this memory resource is required. There have been many published memory test algorithms that are designed to detect memory faults. These algorithms are applicable to testing memory resources in FPGAs. The main concern in testing memory resources is the test time required to detect all faults.


CONCLUSION In this paper, we presented a fully fault-tolerant memory system that is capable of tolerating errors not only in the memory bits but also in the supporting logic including the ECC encoder and corrector. We used Euclidean Geometry codes. We proved that these codes are part of a new subset of ECCs that have FSDs. Using these FSDs we design a fault tolerant encoder and corrector, where the fault-secure detector monitors their operation. We also presented a unified approach to tolerate permanent defects and transient faults. This unified approach reduces the area overhead.

Feature enhancement :

Feature enhancement IN this project the power consumed is very high. So, in order to reduce power we can use Low transitions random test generation along with this equipment.


REFERENCES ITRS, “International technology roadmap for semiconductors,” 2005. [Online]. Available: Home2005.htm Y. Chen, G.-Y. Jung, D. A. A. Ohlberg, X. Li, D. R. Stewart, J. O. Jeppesen, K. A. Nielsen, J. F. Stoddart, and R. S. Williams, “Nanoscale molecular-switch crossbar circuits,” Nanotechnology , vol. 14, pp. 462–468, 2003. A. DeHon, “Nanowire-based programmable architectures,” ACM J. Emerging Technol. Comput. Syst. , vol. 1, no. 2, pp. 109–162, 2005 R. J. McEliece , The Theory of Information and Coding . Cambridge, U.K.: Cambridge University Press, 2002. H. Naeimi, “A greedy algorithm for tolerating defective crosspoints in nanoPLA design,” M.S. thesis, Dept. Comput. Sci., California Inst. Technol., Pasadena, CA, Mar. 2005. H. Naeimi, “Reliable integration of terascale designs with nanoscale devices,” Ph.D. dissertation, Dept. Comput. Sci., California Inst. Technol., Pasadena, CA, Sep. 2007. H. Naeimi and A. DeHon, “Fault secure encoder and decoder for memory applications,” in Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Syst. , Sep. 2007, pp. 409–417.

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