Slide 2:
CISC Processors RISC Processors Emphasis on hardware Emphasis on software CISC provides flexibility in choosing various ways of performing the data transfer and arithmetic and other operations RISC provides no flexibility in choosing the many different ways of performing the data transfer and arithmetic and other operations CISC implements each instruction in a one or more clock cycles resulting in more amount of circuitry and more amount of power dissipation because of its complex instruction set. RISC implements each instruction in a single clock cycle using a distinct hard-wired control at lesser amount of circuitry and lesser amount of power dissipation because of its reduced instruction set. Small amount of cache and very few registers to allow more instruction with memory Large cache and large number of registers to prevent lore interaction with memory Small code sizes Large code sizes Less transistors for memory storage More transistors for memory storage