Verification & Testing of VLSI

Verification & Testing of VLSI: 

Verification & Testing of VLSI Malammanavar rudresh VTU ,VLSI -BELGUM

Purpose of this Course: 

Purpose of this Course Synthesis of Digital Circuits Considered as a better option over design Valid for large digital systems Could lead to Sub-optimal designs Verification takes 70% of designer time Redesigns are expensive Exhaustive testing is not feasible Functional tests are better

1.1 Technology Challenges: 

1.1 Technology Challenges Moore’s Law Doubling of transistor count every 18 months 10 7 - 10 8 transistors/chip capability Hierarchical Design Timing Closure Parasitics comparable to fan-out load Long interconnect increases uncertainity

Technological Challenges (2): 

Technological Challenges (2) Physical properties At Deep Sub Micron (DSM) levels quantum effects like tunneling are significant Signal Integrity (SI) and Data Integrity (DI) Leakages and cross-talk Auto correction during design cycles

Technological Challenges (3): 

Technological Challenges (3) Design Productivity Gap Tools we use today were designed based on requirements yesterday. Tools evolve with need For a leading edge problem, tools always fall short. Number of designers available is far less than what industry needs Both lead to lower productivity

Technological Challenges (4) : 

Technological Challenges (4) Time-to-Market Trends Inter-twining of technology and economy Consumer market is the driving force In Hi-tech market is not sensitive to cost In consumer market, user is never trained Competition grows stronger by day Faster releases to market

Technological Chaleenges (5): 

Technological Chaleenges (5) SOC Technology Integration of several IPs High design complexity Large time for verification

1.2 Verification Technology Options: 

1.2 Verification Technology Options Simulation Code Coverage Transaction based verification Emulation Rapid Prototyping

Simulation: 

Simulation SPICE DC analysis Only for small circuits Very detailed but slow Event-based Simulators Individual Path Delays analyzed Hazards can be detected Slower than cycle based simulators Cycle-based Simulators Values at clock transition only Lesser computation

Transaction-based Verification : 

Transaction-based Verification A Functionally complete operation is a transaction External behavior of transaction can be verified in lesser time Protocol or Interface driven

Code Coverage: 

Code Coverage Synthesis code analysis FSM Traversal Visiting all nodes? All paths are traversed at least once? Branch conditions occur? State after branching Loop Exits State after loop exit Other checks Variable initialization

Emulation: 

Emulation System built with existing components FPGA implementation is common Cheaper to experiment with a design Real input output Can apply real test vectors Behavioral tests also possible Expensive In-Circuit emulators use same chip as target chip.

Other Options: 

Other Options Rapid prototyping Emulators, FPGA, Breadboard designs Hardware Accelerators Parts of software are converted to hardware and interfaced with software environment Analog & Mixed Signal Simulation VerilogA: Analog extensions to Verilog Still a long way to go.

Static Verification Methods : 

Static Verification Methods Lint Checking Static Timing Verification Formal Technologies Theorem Proving

Lint Checking: 

Lint Checking Similar to a pre-compile check Typical mistakes of programming Assignment errors Reg-wire mismatch Using un-initialized variable Wrong port (function argument)… Modern IDE can provide dynamic feedback about correctness of code.

Static Timing-Verification: 

Static Timing-Verification Time is not static (!!!) Calculating Path delays Typical and worst-case delays for gates Rise and Fall times Sum of delays in the paths Loading behavior is dynamic Quick check This is an important verification stage

Formal Model Checking: 

Formal Model Checking Formal Equivalence Checking Mathematical Equivalence Given a set A = { a, b, c} a = a (Reflexivity) If a = b, then b = c (Symmetry) If a = b and b = c then a = c (Transitivity)

Theorem Proving: 

Theorem Proving First Order Logic BusLocked ⇒ BusReleased If a bus is locked, it will be released ∀(BusLocked) (BusLocked ⇒ BusReleased) Universal Quantifier For all conditions under which bus is locked, there will be a bus release condition ∃(BusLocked) (BusLocked ∧ ⌐ BusReleased) Existential Operator Con There exists a busLock condition where bus is locked but bus is not released.

Which is the Fastest Option: 

Which is the Fastest Option Event-based Simulation Cycle-based Simulation Formal Verification Emulation Rapid prototype

1.3 SOC Verification Methodology: 

1.3 SOC Verification Methodology Top Down Approach is shown here Verification is done at every stage System verification IP Verification Protocol verification Netlist verification Static timing verification . . .

Net-list Extraction: 

Net-list Extraction Need for extraction Synthesis process is target specific Parasitic effects Clock and power distribution What detail is to be extracted Depends on what you wish to analyze Line details? Clock Skew?

SOC Verification (2): 

SOC Verification (2) Level 0: Incoming Inspection Level 1: Resource Allocation Memory allocation Area requirements Level 2: Interconnection Level 3: Comparisons Design Boundaries Error handling

Design Boundaries: 

Design Boundaries Power Feature Size Operating Frequency Technology Change

1.4 Testbench Creation: 

1.4 Testbench Creation Testbench in HDL Verilog / VHDL … Testbench in PLI Programming Language Interface C, C++ … Waveform-based

Scope of Tests: 

Scope of Tests Specification-based Behavioral Transaction based Transmission of a frame, e.g. Interface based Unit path, Protocol, … Issue based Floating point performance Legacy Compliance

Testing Issues: 

Testing Issues Exhaustive tests not feasible Automatic Test Pattern Generation D-Algorithm, PODEM, FAN, … Speed of generation of tests Partitioning Speed of running a test Test Compression Alpha Tests and Beta Tests Regression Tests Other Important Topics in Testing Self Test, Specialty tests, JTAG

Testbench Migration: 

Testbench Migration Proven test may be improved or moved to a new environment Behavior to Structural description Function to RTL RTL to Netlist …

2.0 System Level Verification: 

2.0 System Level Verification Functional/Behavioral Design Architecture Mapping

Functional Design: 

Functional Design Core & Peripheral Selection Device Count Minimum Performance Limits Technology Selection Memory estimation Communication Specs Internal / External Boundary and Corner Cases Design Discontinuity Undocumented features Test Generation

Hardware Modules: 

Hardware Modules Hardware / Software Tradeoffs Layout flexibility Performance related to layout Time to market Design capability Tool Capability Macro Cells GDS II Tapeout Bus Architecture Heirarchical Data / Instruction buses Data Path verification

Software IP Modules: 

Software IP Modules Software RTOS, Control Programs Interface Design and Verification Bus architecture Architecture Mapping Technology Mapping IO and Bus Interface Performance Verification

References: 

References Prakash Rashinkar, Peter Paterson, Leena Singh, “System-on-a-chip verification”, Kluwer Academic Publishers, 2001

1.7 Verification IP Reuse: 

1.7 Verification IP Reuse

1.8 Verification Approaches: 

1.8 Verification Approaches Top-Down Design and Verification Approaches Bottom-Up Verification Approach

1.10 Verification Plans: 

1.10 Verification Plans Project Functional Overview Verification Approach Abstraction Levels

Verification Technologies: 

Verification Technologies Abstraction Level for Intent Verification Test Application Approach Results Checking

Functional Verification Flow: 

Functional Verification Flow Test Definition Testbench Requirements Models

Testbench Elements: 

Testbench Elements Verification Metrics Regression Testing

Issue Tracking and Management: 

Issue Tracking and Management Resource Plan Project Schedule

1.11 Bluetooth SOC : A Reference Design : 

1.11 Bluetooth SOC : A Reference Design Bluetooth Device Elements Bluetooth Network

Bluetooth SOC: 

Bluetooth SOC Design Blocks SOC operation

System-Level Verification: 

System-Level Verification Dr. Uday Wali

2.1 System Design: 

2.1 System Design

2.2 System Verification: 

2.2 System Verification Functional Verification Performance Verification

System-Level Test bench: 

System-Level Test bench Creating a System-Level Test bench System Test bench Metrics

Hardware Modeling: 

Hardware Modeling Mixed-Level Simulation Design Partitioning

System Test bench Migration: 

System Test bench Migration Migrating a Testbench to Different Abstraction Levels.

Migrating a System Testbench to Different Environments: 

Migrating a System Testbench to Different Environments Bluetooth SOC

Applying the System-Level Test bench: 

Applying the System-Level Test bench Emulation Hardware Acceleration