logging in or signing up Looping Statements mis06ec Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINT lite Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: (To copy code, click on the text box) Embed: URL: Thumbnail: WordPress Embed Customize Embed The presentation is successfully added In Your Favorites. Views: 252 Category: Education License: All Rights Reserved Like it (1) Dislike it (1) Added: June 21, 2009 This Presentation is Public Favorites: 0 Presentation Description No description available. Comments Posting comment... Premium member Presentation Transcript Looping Statements : Looping Statements Mr.Bhavesh Soni Lecturer in EC UVPCE Looping Statements : 2 Looping Statements There are four types of looping statements. While,for,repeat and forever The syntax of these is very similar to C programmng While Loop : 3 While Loop While loop execute until the while expression is not true Example : increment count form 0 to 127.exit at count 128 Display the count variable integer count ; initial begin count =0; while (count < 128 ) begin $display (“count =%d”,count); count = count +1; end end For Loop : 4 For Loop Contains three parts: An initial condition A check to see if the terminating condition is true A procedural assignment to change value of the control variable For loop provide more compact loop structure than the while loop For Loop Example : 5 For Loop Example integer count; initial for ( count=0; count<128; count=count+1) $display ( “count = %d”,count); For Loop Example : 6 For Loop Example // initialize array elements `define MAX_STATE 32 Integer state[0: `MAX_STATE-1] //state with element 0:31 Integer i; Initial begin for(i=0;i<32;i=i+2) //even location with 0 state [i] = 0; for(i=1;i<32;i=i+2) //odd location with 1 state [i] = 1; end Repeat Loop : 7 Repeat Loop Repeat construct executes the loop a fixed number of times It cannot be used to loop on a general logical expression ( not like while ) It must contain the number, which can be constant, a variable or a signal value Repeat Loop example : 8 Repeat Loop example // increment and display count from 0 to 127 integer count; initial begin count=0; repeat(128) begin $display(“count = %d”,count); count = count +1; end end Repeat Loop example : 9 Repeat Loop example //data buffer module ex module data_buffer(data_start,data,clock); parameter cycles = 8; input data_start; input [15:0] data; input clock; reg [15:0] buffer [0:7]; integer i; always @(posedge clock) begin if(data_start) i=0; repeat(cycles) @(posedge clock) buffer[i] =data; i = i +1; end endmodule Forever Loop : 10 Forever Loop Loop does not contain any expression and executes forever until the $finish It is typically used in conjunction with timing control constructs If timing control constructs is not used it execute this statement infinitely Forever Loop Example : 11 Forever Loop Example // clock generation reg clk; initial begin clock = 1’b0; forever #10 clk = ~clk; // clock with period of 20 // without always end //Synchronize two reg //at every posedge of clk reg clk; reg x,y; Initial forever@(posedge clk)x=y; Looping Statements : 12 Looping Statements Forever continuously executes a statement. repeat executes a statement a fixed number of times. while executes a statement until an expression becomes false. If the expression starts out false, the statement is not executed at all Looping Statements : 13 Looping Statements 4. For controls execution of its associated statement(s) by a three-step process System Tasks : 14 System Tasks All system tasks appear in the form $<keyword> Operation done by system tasks Displaying on the screen Monitoring values of nets Stopping finishing Always written inside procedures Displaying information : 15 Displaying information $display is the main system task for displaying values of variables or strings or expression Usage : $display(p1,p2,p3,…..,pn); p1,p2,p3,…..,pn are quoted string or variables or expressions Format is very similar to printf in C $display inserts new line at the end of the string by default $display & $monitor string format specification : 16 $display & $monitor string format specification $display task : 17 $display task // display the string in quotes $display (“Hello Verilog World”); -- Hello Verilog World // display value of current simulation time 230 $display ($time); -- 230 $display task : 18 $display task // display value of 41-bit virtual address 1fe0000001c at time 200 Reg [0:40] virtual_addr; $display (“At time %d virtual address is %h”,$time,virtual_addr); -- At time 200 virtual address is 1fe0000001c $display task : 19 $display task // Display value of port_id 5 in binary reg [4:0] port_id; $display (“ID of the port is %b ”,port_id); -- ID of the port is 00101 //display x characters //display value of 4-bit bus 10xx in binary reg [3:0] bus; $display(“Bus value is %b”,bus); -- Bus value is 10xx $display task : 20 $display task // Display special character, newline and % $display(“This is a \n multiline string with a %% sign”); -- This is a -- multiline string with a % sign Monitoring information : 21 Monitoring information $monitor is to monitor a signal when its value changes Usages : $monitor(p1,p2,p3,…..pn); p1,p2,p3,…..,pn can be quoted string or variables or signal name Monitor statement : 22 Monitor statement // monitor time and value of the signals clock and reset $monitor($time,”value of signals clock = %b reset =%b”,clock,reset); Output of monitor statement -- 0 value of signals clock =0 reset =1 -- 5 value of signals clock =1 reset =1 -- 10 value of signals clock =0 reset =0 Stopping and finishing a simulation : 23 Stopping and finishing a simulation $stop is provided to stop during a simulation Usage : $stop; The designer can then debug the design $stop suspend the simulation and designer examine the values of signals in the design $finish task terminate the simulation Usage : $finish; $stop & $finish tasks : 24 $stop & $finish tasks // stop at 100 in the simulation and examine the result // finish the simulation at time 1000 initial begin clock = 0; reset =1; #100 $stop;//suspend the simulation at time =100 #900 $finish;// terminate the simulation at time =1000 end Compiler directives : 25 Compiler directives Defined by using `<keyword>construct Two types of compiler directives `define `include `define Directive : 26 `define Directive It is used to define text macros This is similar to the #define construct in C The defined constants or text macros are used in the verilog code by preceding them with a `(back tick) `define Directive example : 27 `define Directive example // define macro that defines default wordsize // used as `WORD_SIZE `define WORD_SIZE 32 //$stop will be substituted wherever `S appears `define S $stop; `include Directive : 28 `include Directive It allows you to include entire contents of a verilog source file in another verilog file during compilation This works similarly to the #include in C It is used to include header files `include Directive : 29 `include Directive // include the file header.v, which contains declarations in the main verilog file design.v `include header.v ……….… <verilog code in file design.v> …………. …………. You do not have the permission to view this presentation. In order to view it, please contact the author of the presentation.
Looping Statements mis06ec Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINT lite Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: (To copy code, click on the text box) Embed: URL: Thumbnail: WordPress Embed Customize Embed The presentation is successfully added In Your Favorites. Views: 252 Category: Education License: All Rights Reserved Like it (1) Dislike it (1) Added: June 21, 2009 This Presentation is Public Favorites: 0 Presentation Description No description available. Comments Posting comment... Premium member Presentation Transcript Looping Statements : Looping Statements Mr.Bhavesh Soni Lecturer in EC UVPCE Looping Statements : 2 Looping Statements There are four types of looping statements. While,for,repeat and forever The syntax of these is very similar to C programmng While Loop : 3 While Loop While loop execute until the while expression is not true Example : increment count form 0 to 127.exit at count 128 Display the count variable integer count ; initial begin count =0; while (count < 128 ) begin $display (“count =%d”,count); count = count +1; end end For Loop : 4 For Loop Contains three parts: An initial condition A check to see if the terminating condition is true A procedural assignment to change value of the control variable For loop provide more compact loop structure than the while loop For Loop Example : 5 For Loop Example integer count; initial for ( count=0; count<128; count=count+1) $display ( “count = %d”,count); For Loop Example : 6 For Loop Example // initialize array elements `define MAX_STATE 32 Integer state[0: `MAX_STATE-1] //state with element 0:31 Integer i; Initial begin for(i=0;i<32;i=i+2) //even location with 0 state [i] = 0; for(i=1;i<32;i=i+2) //odd location with 1 state [i] = 1; end Repeat Loop : 7 Repeat Loop Repeat construct executes the loop a fixed number of times It cannot be used to loop on a general logical expression ( not like while ) It must contain the number, which can be constant, a variable or a signal value Repeat Loop example : 8 Repeat Loop example // increment and display count from 0 to 127 integer count; initial begin count=0; repeat(128) begin $display(“count = %d”,count); count = count +1; end end Repeat Loop example : 9 Repeat Loop example //data buffer module ex module data_buffer(data_start,data,clock); parameter cycles = 8; input data_start; input [15:0] data; input clock; reg [15:0] buffer [0:7]; integer i; always @(posedge clock) begin if(data_start) i=0; repeat(cycles) @(posedge clock) buffer[i] =data; i = i +1; end endmodule Forever Loop : 10 Forever Loop Loop does not contain any expression and executes forever until the $finish It is typically used in conjunction with timing control constructs If timing control constructs is not used it execute this statement infinitely Forever Loop Example : 11 Forever Loop Example // clock generation reg clk; initial begin clock = 1’b0; forever #10 clk = ~clk; // clock with period of 20 // without always end //Synchronize two reg //at every posedge of clk reg clk; reg x,y; Initial forever@(posedge clk)x=y; Looping Statements : 12 Looping Statements Forever continuously executes a statement. repeat executes a statement a fixed number of times. while executes a statement until an expression becomes false. If the expression starts out false, the statement is not executed at all Looping Statements : 13 Looping Statements 4. For controls execution of its associated statement(s) by a three-step process System Tasks : 14 System Tasks All system tasks appear in the form $<keyword> Operation done by system tasks Displaying on the screen Monitoring values of nets Stopping finishing Always written inside procedures Displaying information : 15 Displaying information $display is the main system task for displaying values of variables or strings or expression Usage : $display(p1,p2,p3,…..,pn); p1,p2,p3,…..,pn are quoted string or variables or expressions Format is very similar to printf in C $display inserts new line at the end of the string by default $display & $monitor string format specification : 16 $display & $monitor string format specification $display task : 17 $display task // display the string in quotes $display (“Hello Verilog World”); -- Hello Verilog World // display value of current simulation time 230 $display ($time); -- 230 $display task : 18 $display task // display value of 41-bit virtual address 1fe0000001c at time 200 Reg [0:40] virtual_addr; $display (“At time %d virtual address is %h”,$time,virtual_addr); -- At time 200 virtual address is 1fe0000001c $display task : 19 $display task // Display value of port_id 5 in binary reg [4:0] port_id; $display (“ID of the port is %b ”,port_id); -- ID of the port is 00101 //display x characters //display value of 4-bit bus 10xx in binary reg [3:0] bus; $display(“Bus value is %b”,bus); -- Bus value is 10xx $display task : 20 $display task // Display special character, newline and % $display(“This is a \n multiline string with a %% sign”); -- This is a -- multiline string with a % sign Monitoring information : 21 Monitoring information $monitor is to monitor a signal when its value changes Usages : $monitor(p1,p2,p3,…..pn); p1,p2,p3,…..,pn can be quoted string or variables or signal name Monitor statement : 22 Monitor statement // monitor time and value of the signals clock and reset $monitor($time,”value of signals clock = %b reset =%b”,clock,reset); Output of monitor statement -- 0 value of signals clock =0 reset =1 -- 5 value of signals clock =1 reset =1 -- 10 value of signals clock =0 reset =0 Stopping and finishing a simulation : 23 Stopping and finishing a simulation $stop is provided to stop during a simulation Usage : $stop; The designer can then debug the design $stop suspend the simulation and designer examine the values of signals in the design $finish task terminate the simulation Usage : $finish; $stop & $finish tasks : 24 $stop & $finish tasks // stop at 100 in the simulation and examine the result // finish the simulation at time 1000 initial begin clock = 0; reset =1; #100 $stop;//suspend the simulation at time =100 #900 $finish;// terminate the simulation at time =1000 end Compiler directives : 25 Compiler directives Defined by using `<keyword>construct Two types of compiler directives `define `include `define Directive : 26 `define Directive It is used to define text macros This is similar to the #define construct in C The defined constants or text macros are used in the verilog code by preceding them with a `(back tick) `define Directive example : 27 `define Directive example // define macro that defines default wordsize // used as `WORD_SIZE `define WORD_SIZE 32 //$stop will be substituted wherever `S appears `define S $stop; `include Directive : 28 `include Directive It allows you to include entire contents of a verilog source file in another verilog file during compilation This works similarly to the #include in C It is used to include header files `include Directive : 29 `include Directive // include the file header.v, which contains declarations in the main verilog file design.v `include header.v ……….… <verilog code in file design.v> …………. ………….