Lab 6 - 555 Timer

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LECTURE 6 555 Timer :

LECTURE 6 555 Timer Engr.Shahbaz Mob#03345202825 IIUI Islamabad

Pins Configurations:

Pins Configurations Trigger input : when <  1 / 3  Vs ('active low') this makes the output high (+Vs). It monitors the discharging of the timing capacitor in an astable circuit. It has a high input impedance > 2M . Threshold input: when >  2 / 3  Vs ('active high') this makes the output low (0V)*. It monitors the charging of the timing capacitor in astable and monostable circuits. It has a high input impedance > 10M . * providing the trigger input is >  1 / 3  Vs, otherwise the trigger input will override the threshold input and hold the output high (+Vs). .

PowerPoint Presentation:

Reset input: when less than about 0.7V ('active low') this makes the output low (0V), overriding other inputs. When not required it should be connected to +Vs. It has an input impedance of about 10k Control input: this can be used to adjust the threshold voltage which is set internally to be 2 / 3  Vs. Usually this function is not required and the control input is connected to 0V with a 0.01µF capacitor to eliminate electrical noise. It can be left unconnected if noise is not a problem. The discharge pin is not an input, but it is listed here for convenience. It is connected to 0V when the timer output is low and is used to discharge the timing capacitor in astable and monostable circuits

Common Types of 555 circuits:

Astable - producing a square wave Monostable - producing a single pulse when triggered Bistable - a simple memory which can be set and reset Buffer - an inverting buffer (Schmitt trigger) Common Types of 555 circuits



Mono Stable:

Mono Stable


Comparizan STM STM Astable The circuit is called an a stable because it is not stable in any state: the output is continually changing between 'low' and 'high'. An astable circuit produces a 'square wave' Monostable i t is stable in just one state: 'output low'. The 'output high' state is temporary. A monostable circuit produces a single output pulse when triggered

Inverting Buffer :

Inverting Buffer When the input voltage is between 1 / 3 and 2 / 3 Vs the output remains in its present state. This intermediate input region is a deadspace where there is no response, a property called hysteresis, it is like backlash in a mechanical linkage. This type of circuit is called a Schmitt trigger.

Bistable :

Bistable The circuit is called a bi stable because it is stable in two states output high and output low


Precision timing Pulse generation Sequential timing Time delay generation Pulse width modulation Pulse position modulation Linear ramp generator Applications

Lab Assignment :

Lab Assignment How To achieve a duty cycle of less than 50% ? Time period in mono stable is, T = 1.1 × R1 × C1 Why 1.1? Design police siren sound using 555 Design circuit whose o/p has Amplitude = Reg #/10 volts and time period = Reg # ms and duty cycle =.75xReg# .


555 and 556 Timer Circuits.htm 555 timer.htm 555 timer - Google Search.mht References

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