High performance vlsi adder

High performance vlsi adder: 

High performance vlsi adder

Abstract : 

Abstract This project is digital hardware based. Implemented using Verilog and Spartan 3 FPGA core Softwares used are ModelSim XE III 6.0d and Xilinx ISE 8.1i Here hardware specific Ling Adder is transformed to general purpose Ling adder

Parallel adders: 

Parallel adders Ripple carry adder

Slide 4: 

The result of an addition of two bits depends on the carry generated by the addition of the previous two bits. Sum of the most significant bit is only available after the carry signal has rippled through the adder from the least significant stage to the most significant stage. It can get very slow when one needs to add many bits.

Slide 5: 

This can be easily understood if one considers the addition of the two 4-bit words: 1 1 1 1 2 + 0 0 0 1 2 , as shown in Figure 3.

Slide 7: 

2.Carry look ahead adder The carry-look-ahead adder solves this problem by calculating the carry signals in advance, based on the input signals. Carry generate g i =a i .b i Carry propagate p i = a i ^b i Carry c i = g i +p i c i-1 Sum s i = p i ^c i

Slide 8: 

Cumulative delay is eliminated But the carry logic is getting quite complicated for more than 4 bits.

Project outline: 

Project outline 1.Literature survey CLA algorithms like Lings algorithm are hardware specific Since hardware specific , the addition process consume nonlinear current and hence battery recharging should be done frequent ly Hardware specific additon process have unequal delay in processing different datas

Slide 10: 

In hardware CLAs are implemented in 3 stages final sum Pre-calculation of p i , g i for each stage Calculation of carry c i for each stage. Combine c i and p i of each stage to generate the sum bits s i

Ling adder: 

Ling adder Ling Adder is a special kind of CLA Adders The improvement is in the carry generation stage which is the most intensive one Pseudo carry h i = c i + c i-1 is propagated instead of c i

Slide 13: 

LINGS ALGORITHM h i+1 =c i+1 + c i (1) = g i +p i c i +c i = g i +c i h i+1 = g i +c i (2) g i h i +1 = g i (3) p i c i = p i c i +p i g i +p i p i c i =p i c i +p i c i+1 =p i h i+1

Slide 14: 

p i c i = p i h i+1 (4) c i+1 = g i +p i c i = g i h i +1 + p i h i+1 c i+1 = h i+1 t i (5) where t i = g i + p i

Slide 15: 

h i+1 = g i +c i c i+1 = h i+1 t i c i =t i-1 h i h i+1 =g i +t i-1 h i g i +t i-1 h i (6) s i =t i ^h i+1 +g i t i-1 h i (7)

Proposed model: 

Proposed model Proposed Lings algorithm is a generalized algorithm Since it is not hardware specific current consumption can be made almost linear Delay will be same for all addition process Addition process will be faster than normal CLA So by using these subroutines in Math coprocessor effectively we can increase the overall system performance