RF presentation

RF Transceiver and Power harvesting block:

RF Transceiver and Power harvesting block

Slide 2:

Three stages: 1-matching circuit 2-voltage doublers 3-regulation 4-scatterrer (transmitter) In our presentation we focus on voltage doublers/multipliers and rectification Tasks: 1-Search and study different power harvesting topologies 2-compare between topologies and choose best topologies to simulate and compare results 3-search for appropriate simulation programs and choose one to work with 4-Search appropriate spice models to work with 5-Simulate chosen topologies and compare results

STUDIED VOLTAGE DOUBLERS TOPOLOGIES:

STUDIED VOLTAGE DOUBLERS TOPOLOGIES 1-Cockcroft-Walton Voltage Multiplier 2-Dickson Voltage Multiplier 3-Modified Dickson Voltage Multipliers 4-Cross Coupled Voltage Multiplier 5-Mandal-Sarpeshkar Voltage Multiplier 6-Cross Coupled With Bridge Structure 7-Modified Diode Connected Rectifier 8-Bergeret Voltage Multiplier

Slide 4:

Basic Voltage Doublers Cell [1] Negative half cycle: D1 on(S.C) D2 off(O.C) C1 charges to peak voltage Positive half cycle: D2 on(S.C) D1 off(O.C) C2 charges to double peak voltage - + - + 2vp - + vp - +

1-Cockcroft-Walton Voltage Multiplier[1] :

1-Cockcroft-Walton Voltage Multiplier [1] Clocking signals φ, φ’ Parasitic capacitance problem The effectiveness of Cockcroft-Walton voltage multiplier largely diminishes in monolithic integration where stray capacitance Cs and C become comparable.

2.1-Dickson Voltage Multiplier[1] :

2.1-Dickson Voltage Multiplier [1] Clocking signals φ and φ’ are injected to all the coupling nodes The coupling and stray capacitors are driven by the clocking signals directly The shunt capacitors connected to the output node of the Dickson voltage multiplier must withstand the full output voltage. Schottky diodes are widely used in Dickson voltage multipliers due to their low forward conduction voltage, large saturation current, low junction capacitance, and small series resistance.

2.2-Dickson Voltage Multiplier Using MOSFET[1] :

2.2-Dickson Voltage Multiplier Using MOSFET [1] Each diode is replaced by a diode connected MOSFET(MOSFET with its Gate connected to its Drain) The advantage of these configurations is their full compatibility with standard CMOS technologies The main drawback is the voltage loss across the MOSFET devices of at least one threshold voltage. This is accompanied with low power efficiency, especially when the amplitude of the input voltage is low.

2.3-Dickson Voltage Multiplier with static charge transfer switches[1] :

2.3-Dickson Voltage Multiplier with static charge transfer switches [1] MOSFET working in the triode is connected in parallel with each of the MOSFET diodes The observation that the voltage drop across of the drain and source of a MOSFET is low if the device is operated in the triode region suggests that the voltage loss of MOSFET diodes can be minimized by connecting a MOSFET working in the triode in parallel with each of the MOSFET diodes.

2.3-Dickson Voltage Multiplier with bootstrapped gate transfer switches[1] :

2.3-Dickson Voltage Multiplier with bootstrapped gate transfer switches [1] Proposed bootstrapped gate transfer switches to replace MOSFET diodes of Dickson voltage multiplier. For each transistor, there are five additional transistors M1a,...,5a and one capacitor Ca are added.

2.3-Dickson Voltage Multiplier with bootstrapped gate transfer switches[1] :

2.3-Dickson Voltage Multiplier with bootstrapped gate transfer switches [1] When φ = 1 M1a,3a,5a are ON M2a,4a are OFF Ca is charged to peak voltage of vin When φ = 0 M1a,3a,5a are OFF M2a,4a are ON The voltage of the capacitor Ca is applied between the gate and drain of M2 + Vb -

2.3-Dickson Voltage Multiplier with bootstrapped gate transfer switches[1] :

IF we assigned input voltage such that its peak exactly equals to MOSFET threshold voltage we will totally eliminate voltage drop between the Drain and Source Output voltage of a 5stage Dickson voltage multiplier with bootstrapped gate transfer switches, C1−4 = 15 pF, Cout = 30 pF, f = 5 MHz, and Vm = 2V, is 9 V approximately. The output voltage is only 4 V approximately with static charge transfer switches. The power conversion efficiency is increased from 40% approximately with static charge transfer switches to above 90% with bootstrapped gate transfer switches. The circuit could be simply referred to as the following two circuits for φ = 0 and φ = 1 2.3-Dickson Voltage Multiplier with bootstrapped gate transfer switches [1]

3-Modified Dickson Voltage Multipliers[1] :

3-Modified Dickson Voltage Multipliers [1] Voltage multiplier requires non-overlapping clock signals φ and φ’. For power telemetry, only one RF signal is available φ’ and vin terminals are grounded and the RF input is connected to φ terminal To overcome the drawback that VDS≠0 in modified Dickson with MOS-diodes, native nMOS transistors whose threshold voltage is approximately zero have been used. The main drawback is that native MOS structure is not generally supported. Also, the large channel resistance of native MOSFETs deteriorates the performance. RF input

4-Cross Coupled Voltage Multiplier[2] :

4-Cross Coupled Voltage Multiplier [2] The main disadvantage of ordinary MOS-Diode connected basic cell is the voltage drop Vds that in fact could be referred to as non-zero ON Resistance of the transistor BUT, HOW TO SOLVE THIS PROBLEM??! Try to increase the gate voltage for transistors this is directly translated into decreasing the ON Resistance of the transistor which is almost inverse proportional to Vgs

4-Cross Coupled Voltage Multiplier[2] :

4-Cross Coupled Voltage Multiplier [2] The Cross Coupled Voltage Multiplier effectively provide high gate voltage for NMOS transistor by connecting the gate to the output voltage which is high To make the circuit work properly the second transistor that is connected to the output is replaced by PMOSFT with its gate connected to ground this provide small Vsg of PMOSFT, hence small ON-Resistance The main problem of this circuit is that providing high gate voltage for NMOSFT and low gate voltage for PMOSFT increase the reverse leakage current

5-Mandal-Sarpeshkar Voltage Multiplier[1][3] :

5-Mandal-Sarpeshkar Voltage Multiplier [1][3] This is the basic cell of Mandal-Sarpeshkar Voltage Multiplier This cell obviously provide a solution for the disadvantage of Cross Coupled Voltage Multiplier We can see that the on resistance of the transistors is decreased by increasing Vgs of the transistors and the reverse leakage is reduced by reversing the polarity of the Vgs in the cross coupled structures

5-Mandal-Sarpeshkar Voltage Multiplier[1][4] :

5-Mandal-Sarpeshkar Voltage Multiplier [1][ 4] This circuit introduces the full Mandal-Sarpeshkar Voltage Multiplier The first stage acts as a full-wave rectifier While the capacitors used in successive stages charges up to increase the voltage level

6-Cross Coupled With Bridge Structure Voltage Multiplier[2] :

6-Cross Coupled With Bridge Structure Voltage Multiplier [2] Cross Coupled With Bridge Structure Voltage Multiplier provide another improvement circuit of Cross Coupled Voltage Multiplier to reduce the reverse leakage current by reversing the polarity of the Vgs in OFF state of the MOSFETS

7-Modified Diode Connected Rectifier[5] :

7-Modified Diode Connected Rectifier [5] This circuit is produced to us by ENG. Ahmed Kamal Here the problem of reverse leakage current is solved in a different manner by providing active feedback to control the gate voltage to minimize reverse leakage current

7-Bergeret Voltage Multiplier[1] :

7-Bergeret Voltage Multiplier [1] Bergeret modified the configuration of conventional voltage multiplier by only using a single stage rectifier to generate a dc voltage. This voltage is then used to power a low frequency VCO whose outputs, together with the output of the single stage rectifier, are used to drive a high efficiency voltage multiplier We think that this may be useful to manage to use Dickson voltage multiplier with bootstrapped gate transfer switches because it can’t work without clocks φ and φ’ unlike modified Dickson voltage multipliers

BEST TOPOLOGIES TO SIMULATE AND COMPARE RESULTS :

BEST TOPOLOGIES TO SIMULATE AND COMPARE RESULTS 1-Mandal-Sarpeshkar Voltage Multiplier 2-Cross Coupled With Bridge Structure 3-Modified Diode Connected Rectifier

SIMULATION PROGRAM:

SIMULATION PROGRAM We started comparing different simulation programs such as cadence spectre , multisim ,…etc After all we found an extremely interesting program which is ALTIUM designer which is advanced tool produced by mentor This program has many advantages of accurate simulations, advanced interface, many included spice models of (Maxim, Motorola, National Semiconductor, Atmel…etc) and even transmission lines

SIMULATION1-Output Voltage Versus Time (Transient response) For Single Stage:

SIMULATION1 -Output Voltage Versus Time (Transient response) For Single Stage

Comparison Between Topologies Based On simulation 1 :

Comparison Between Topologies Based On simulation 1

SIMULATION2-Output Voltage Versus Time (Transient response) For cascaded Stages:

SIMULATION2 -Output Voltage Versus Time (Transient response) For cascaded Stages

Comparison Between Topologies Based On simulation 2 :

Comparison Between Topologies Based On simulation 2

MATCHING CIRCUIT[6] :

MATCHING CIRCUIT [6] In matching want to place interface circuit in the front of our system to eliminate reflections thus receive maximum power The main requirements for matching is that the matching circuit be reactive so that there is no power dissipated in it and the maximum power is supplied to voltage doublers Two possible methods of matching are to be produced: 1-Matching using analytical solution 2-Matching using Smith Chart

1-Matching using analytical solution[6] :

1-Matching using analytical solution [6] In this method a matching circuit is assumed and total input impedance-after adding matching elements-is equated to equal Z0 From this equation we could obtain the values of the matching elements

2-Matching using Smith Chart[6] :

2-Matching using Smith Chart [6] Impedance and Reactance Smith charts provide locus of constant resistance and reactance in the Γ -plane Knowing the normalized load point we can reach the origin on constant resistance circles and satisfying matching with reactive elements Impedance smith chart Reactance smith chart

REGULATORS:

REGULATORS There is many discrete regulators exists that provide our requirements , but we have not chosen a specific one yet We started simulating discrete regulators in our circuits We also started searching for MOSFET implemented regulators and obtained some useful results Regulators acts as a basic bias cell that provide pure supply with no oscillations that is capable of driving resistive loads

SPICE MODELS:

SPICE MODELS The main requirement in choosing transistor in our design is that it have low threshold voltage as we don’t require high speed transistors which used for GHZ applications Big difference in threshold voltage don’t mainly appear in discrete components, so any model from existing models-that we have already obtained-is OK

REFERENCES:

REFERENCES [1] CMOS Circuits for Passive Wireless Microsystems Fei Yuan, July 2010 [2] High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs Koji Kotani , Member, IEEE, Atsushi Sasaki, and Takashi Ito, Senior Member, IEEE EEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 11, NOVEMBER 2009 [3] A High-Efficiency CMOS Rectifier for Low-Power RFID Tags Alireza Sharif Bakhtiar , M. Sadegh Jalali , and Shahriar Mirabbasi Department of Electrical and Computer Engineering University of British Columbia, Vancouver, BC, Canada IEEE RFID 2010 [4] Low-Power CMOS Rectifier Design for RFID Applications Soumyajit Mandal , Student Member, IEEE, and Rahul Sarpeshkar , Member, IEEE IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 6, JUNE 2007 [5]Eng. Ahmed kamal Grad- Proj -Concept 24-10-2010 [6] Islam A. Eshrah , 2008 ELC 305a – Fall 2009