logging in or signing up 23573279-SR-Flip-Flop lokesh12341 Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINT lite Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: (To copy code, click on the text box) Embed: URL: Thumbnail: WordPress Embed Customize Embed The presentation is successfully added In Your Favorites. Views: 158 Category: Entertainment License: All Rights Reserved Like it (0) Dislike it (0) Added: November 26, 2010 This Presentation is Public Favorites: 0 Presentation Description No description available. Comments Posting comment... Premium member Presentation Transcript SR Flip-Flop : SR Flip-Flop The SR Flip-Flop How it works Where does it fit with others Master-Slave Flip-Flops Negative Edge Triggered Flip-Flops The SR Flip-Flop : The SR Flip-Flop S R Q Q S R Action 0 0 Keep state 0 1 Q = 0 1 0 Q = 1 1 1 Undefined Clocked SR Flip-Flop : Clocked SR Flip-Flop S R Q Q CLK Clocked D Flip-Flop : Clocked D Flip-Flop Q Q CLK D JK Flip-Flop : JK Flip-Flop J K Q Q CLK T Flip-Flop : T Flip-Flop Q Q CLK T Master-Slave Flip-Flop : Master-Slave Flip-Flop J K Q Q CLK Master-Slave Flip-Flop : Master-Slave Flip-Flop Happens only once per clock cycle Acts as a double check Negative Edge Triggered D Flip-Flop : Negative Edge Triggered D Flip-Flop Q Q D CLK Negative Edge Triggered D Flip-Flop : Negative Edge Triggered D Flip-Flop Same benefits as a Master-Slave More efficient Finite State Machines : Finite State Machines What they are Build One What it is : What it is A way of modelling using “states” States Transitions Actions Example From Book (Pg. 464) : Example From Book (Pg. 464) Modulo-4 Synchronous Counter 00 to 11 and repeats Has one input to reset the counter and start over R S1S0 T+1 T+10 0 0 01 010 0 1 10 100 1 0 11 110 1 1 00 001 0 0 00 001 0 1 00 001 1 0 00 001 1 1 00 00 How Do We Build This? : How Do We Build This? Facts Two Bites of storage One input Two output Start with two D Flip-Flops Four states so four ANDs Two outputs so two ORs Plug it all together and fill in the gaps The Build (Pg. 467) : The Build (Pg. 467) D Q Q CLK D Q Q RESET q1 q0 You do not have the permission to view this presentation. In order to view it, please contact the author of the presentation.
23573279-SR-Flip-Flop lokesh12341 Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINT lite Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: (To copy code, click on the text box) Embed: URL: Thumbnail: WordPress Embed Customize Embed The presentation is successfully added In Your Favorites. Views: 158 Category: Entertainment License: All Rights Reserved Like it (0) Dislike it (0) Added: November 26, 2010 This Presentation is Public Favorites: 0 Presentation Description No description available. Comments Posting comment... Premium member Presentation Transcript SR Flip-Flop : SR Flip-Flop The SR Flip-Flop How it works Where does it fit with others Master-Slave Flip-Flops Negative Edge Triggered Flip-Flops The SR Flip-Flop : The SR Flip-Flop S R Q Q S R Action 0 0 Keep state 0 1 Q = 0 1 0 Q = 1 1 1 Undefined Clocked SR Flip-Flop : Clocked SR Flip-Flop S R Q Q CLK Clocked D Flip-Flop : Clocked D Flip-Flop Q Q CLK D JK Flip-Flop : JK Flip-Flop J K Q Q CLK T Flip-Flop : T Flip-Flop Q Q CLK T Master-Slave Flip-Flop : Master-Slave Flip-Flop J K Q Q CLK Master-Slave Flip-Flop : Master-Slave Flip-Flop Happens only once per clock cycle Acts as a double check Negative Edge Triggered D Flip-Flop : Negative Edge Triggered D Flip-Flop Q Q D CLK Negative Edge Triggered D Flip-Flop : Negative Edge Triggered D Flip-Flop Same benefits as a Master-Slave More efficient Finite State Machines : Finite State Machines What they are Build One What it is : What it is A way of modelling using “states” States Transitions Actions Example From Book (Pg. 464) : Example From Book (Pg. 464) Modulo-4 Synchronous Counter 00 to 11 and repeats Has one input to reset the counter and start over R S1S0 T+1 T+10 0 0 01 010 0 1 10 100 1 0 11 110 1 1 00 001 0 0 00 001 0 1 00 001 1 0 00 001 1 1 00 00 How Do We Build This? : How Do We Build This? Facts Two Bites of storage One input Two output Start with two D Flip-Flops Four states so four ANDs Two outputs so two ORs Plug it all together and fill in the gaps The Build (Pg. 467) : The Build (Pg. 467) D Q Q CLK D Q Q RESET q1 q0