Flip-Flop

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FF

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Presentation Transcript

Flip-Flops : 

Flip-Flops

Basic RS Flip-Flop (NAND) : 

Basic RS Flip-Flop (NAND) A flip-flop holds 1 "bit". "Bit" ::= "binary digit."

Clocked D Flip-Flop : 

Clocked D Flip-Flop The present state is held when CP is low.

Clock Pulse Definition : 

Clock Pulse Definition Edges can also be referred to as leading and trailing.

Master-Slave Flip-Flop : 

Master-Slave Flip-Flop

Flip-Flop on RT54SX-A(Not hardened) : 

Flip-Flop on RT54SX-A(Not hardened)

RT54SX-A SEU Performance : 

RT54SX-A SEU Performance

RT54SX-S Latch(SEU Hardened) : 

RT54SX-S Latch(SEU Hardened)

Flip-Flop Timing: RT54SX-S : 

Flip-Flop Timing: RT54SX-S

Slide 10: 

Metastability - Introduction Can occur if the setup, hold time, or clock pulse width of a flip-flop is not met. A problem for asynchronous systems or events. Can be a problem in synchronous systems. Three possible symptoms: Increased CLK -> Q delay. Output a non-logic level Output switching and then returning to its original state. Theoretically, the amount of time a device stays in the metastable state may be infinite. Many designers are not aware of metastability.

Slide 11: 

Metastability In practical circuits, there is sufficient noise to move the device output of the metastable state and into one of the two legal ones. This time can not be bound. It is statistical. Factors that affect a flip-flop's metastable "performance" include the circuit design and the process the device is fabricated on. The resolution time is not linear with increased circuit time and the MTBF is an exponential function of the available slack time.

Slide 12: 

Metastability - Calculation MTBF = eK2*t / ( K1 x FCLK x FDATA) t is the slack time available for settling K1 and K2 are constants that are characteristic of the flip-flop Fclock and Fdata are the frequency of the synchronizing clock and asynchronous data. Software is available to automate the calculations with built-in tables of parameters. Not all manufacturers provide data.

Slide 13: 

Metastability - Sample Data

Slide 14: 

Synchronizer (Bad Circuit)

Metastable State:Possible Output from a Flip-flop : 

Metastable State:Possible Output from a Flip-flop

Metastable State:Possible Outputs from a Flip-flop : 

Metastable State:Possible Outputs from a Flip-flop Correct Output

Parallel Registers : 

Parallel Registers

4-Bit Parallel Register : 

4-Bit Parallel Register

4-Bit Register With Enable : 

4-Bit Register With Enable

Register Files (Simplified) : 

Register Files (Simplified) D and Q are both sets of lines, with the number of lines equal to the width of each register. There are often multiple address ports, as well as additional data ports.

Memory Devices : 

Memory Devices

Slide 22: 

Register MagneticCoreMemory Sense wires serve as OR plane.

Slide 23: 

SemiconductorMemory Decoder (AND plane) OR plane

Slide 24: 

Rad-Hard PROM Architecture No latches in this architecture

W28C64 EEPROMSimplified Block Diagram : 

W28C64 EEPROMSimplified Block Diagram A6-12 A0-5 CE* WE* OE* CLK I/O0-7 Latch Enable PE RSTB VW