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Source of power dissipation in digital integrated circuits.:

Source of power dissipation in digital integrated circuits. By-Prashant kumar M-tech 1 st year Dept. of E lectronics Engg . Pondicherry university

motivation:

motivation Why we worry about power

because:

because Limitation of source of energy

And why about power dissipation:

And why about power dissipation Limitation of technology of battery

motivation:

motivation The development of competitive market sectors such as wireless applications, laptops, and portable medical devices, depends on the power dissipation as the most important parameter because the growth rate of the battery technologies is not so promising . T he low power dissipation is equally important with the remaining two design parameters, namely area and speed. D esign of an efficient integrated circuit in terms of power, area, and speed simultaneously, has become a very challenging problem.

power efficient device = prevent unnecessary dissipation:

power efficient device = prevent unnecessary dissipation

Power dissipation ?:

Power dissipation ? When a current flows through a component, that component will heat up. This process is called power dissipation and is measured in Watts.

The components of power dissipation in CMOS circuits :

The components of power dissipation in CMOS circuits

The components of power dissipation in CMOS circuits :

The components of power dissipation in CMOS circuits Dynamic Power dissipation Short-circuit power dissipation Leakage Power Dissipation Static Power dissipation

Pavg=pdynamic+pshort-circuit +pleakage +pstatic:

P avg = p dynamic +p short-circuit + p leakage + p static FORMULATION

Dynamic Power dissipation:

Dynamic Power dissipation The dynamic power dissipation, , is caused by the charging and discharging of capacitances in the circuit.

example of a CMOS inverter driving a load capacitor :

example of a CMOS inverter driving a load capacitor

Slide13:

When the input waveform undergoes a falling transition- the pMOS transistor conducts (ON) and the nMOS transistor turns off The current drawn from the power supply charges now the capacitor C L up to V dd . During this charging process, the energy drawn from the power supply is C L . V dd ^2, of which - half is stored in the capacitor and the other half is dissipated in the parasitic capacitances of pMOS transistor and the interconnect .

Slide14:

When the input waveform undergoes a rising transition The nMOS transistor conducts and The pMOS transistor turns off Now , there is a current path directly from the output capacitor to the ground and, thus, a discharging current flows through this path.

Formulation:

Formulation Therefore, the dynamic power dissipated by a CMOS inverter over a time interval [0,T] can be computed by : P dynamic = C L. V 2 dd N 0→1 / T Where N 0→1 is the number of rising transitions at the inverter’s output, or equivalently the number of times is C L charged, over the period [0,T].

power Reduction Approaches of Dynamic dissipation:

p ower Reduction Approaches of Dynamic dissipation power reduction can be achieved by various manners: Reduction of output capacitance,C L , Reduction of power supply voltage,V dd , Reduction of the average number of transitions per clock cycle,N , (or switching activity) and Reduction of clock frequency

Short-circuit power dissipation:

Short-circuit power dissipation The short-circuit power disspation , , is caused by the current flow through the direct path existing between the power supply and the ground during the transition phase.

example:

example Consider again the CMOS inverter When the input signal changes from the logic value’1’ to the logic value ’0 ’, or vice versa, there exists a very small time interval during which both nMOS and pMOS transistors are ON, and hence a short-circuit current flows between the power supply and the ground. if the rising input voltage exceeds the threshold voltage,V thn , the nMOS transistor of the inverter circuit starts conducting , while the pMOS transistor conducts until the input voltage reaches to the value of [ V dd -│ V thp │]

Slide19:

Figure illustrates the short-circuit current effect in a CMOS inverter.

The time-averaged short-circuit current drawn from the power supply and the short-circuit current power dissipation of a CMOS inverter can be approximated by :

The time-averaged short-circuit current drawn from the power supply and the short-circuit current power dissipation of a CMOS inverter can be approximated by K is a constant that depends on the transistor sizes, as well as on the technology , V th is the threshold voltage of the nMOS and pMOS transistors, T is the rise or fall time of the input signal , N is the average number of transitions in the inverter’s output, and f is the clock frequency.

Leakage Power Dissipation-Importance:

Leakage Power Dissipation-Importance A CMOS integrated circuit, which encompasses a very large number of transistors, these currents can contribute to the total power dissipation even when the transistors are not performing any switching action .

Leakage Power Dissipation:

Leakage Power Dissipation The leakage power dissipation,P leakage , is caused by two types of leakage currents : the reverse-bias diode leakage current at the transistor drains the subthreshold current through a turned-off transistor channel

leakage current:

leakage current pMOS transistor with a negative gate bias in respect to its substrate. Hence, the diode formed by the drain diffusion and the substrate is reverse-biased

subthreshold current:

subthreshold current The second current component is the subthreshold leakage current, which occurs due to carrier diffusion between the source and the drain of MOS transistor. The magnitude of the subthreshold current may increase significantly when the gate- to-source voltage is smaller than, but very close to, the threshold voltage of the transistor.

Slide25:

sub-threshold cur- rent is exponentially dependent on the gate-source voltage The current in the subthreshold region is given by - Where K is a function of the technology , V T is the thermal voltage , V th is the threshold voltage and , where is the t ox gate oxide thickness, D is the channel depletion layer width, the quantity .

Static Power dissipation:

Static Power dissipation Ideally, in the steady state of CMOS circuits there is no static power dissipation However, the actual operation of a CMOS circuit is slightly different.

example:

example A pass nMOS transistor drives an inverter. From basic CMOS circuit theory we know that, the voltage value at the node A is , i.e. it is degraded. Since the inverter’s input is high, i.e . its output should be low. However, the pMOS transistor will be weakly ON and, thus, conducting static current from power supply to ground rails. The associated static power dissipation might be significant if the inverter operation frequency is low.

Slide28:

input signals OUT C L V dd nMOS-based logic function A pseudo- nMOS logic gate consists of a single pMOS transistor, whose gate is always grounded, and a complex block of nMOS transistors, which actually implements the boolean function. so It can easily be seen that there always exists a path from the power supply rail to the ground rail, because the pMOS transistor is always ON. Therefore , during the steady state there is static power dissipation .

Slide29:

In a pseudo- nMOS logic, the current flows from V dd to the ground only when the output is at the logic level’0 ’. In the opposite case , when the output is at the logic level’1 ’, then MOS transistor block are turned off and no static power is consumed, except leakage current . This characteristic may be useful in a low power design.If the output signal exhibits very high transition probability being at the logic ’1’, it may be a good choice to implement a logic function with pseudo- nMOS logic. In contrary, if the output signal has very a very low transition probability, we may eliminate the nMOS block of a pseudo- nMOS circuit and substitute it with a load transistor of nMOS type.

Slide30:

I hate slides Seriously, they’re boring. Let’s do questions instead. Any topic http://www.it.uom.gr/teaching/embedded/material/support.inf.uth.gr_courses_CE536/Related_Documents/3%20Synthesis,% 20estimation%20and%20power%20optimization%20of%20embedded%20systems/Low_power_circuit_design.pdf http://en.wikipedia.org/wiki/CMOS Question ???

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