EC6504 Microprocessor and Microcontroller Lecture Notes all 5 Units

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EC6504 Microprocessor and Microcontroller Lecture Notes PPT

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Sir, can you please send me manual for IT6411-Microprocessor lab 2013 regulation to mail logeshgupta@gmail.com

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EC6504 Microprocessors and Microcontrollers DEPARTMENTS: CSEITECEECEMECH Regulation : 2013 Presented by C.GOKULAP/EEE DEPARTMENTS: CSEITECEECEMECH Regulation : 2013 1

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Microprocessor • Microprocessor µP is the brain of a computer that has been implemented on one semiconductor chip. • The word comes from the combination micro and processor. • Processor means a device that processes whateverbinary numbers 0s and 1s To process means to manipulate. It describes all manipulation. Micro - extremely small • Microprocessor µP is the brain of a computer that has been implemented on one semiconductor chip. • The word comes from the combination micro and processor. • Processor means a device that processes whateverbinary numbers 0s and 1s To process means to manipulate. It describes all manipulation. Micro - extremely small 2

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Definition of a Microprocessor. The microprocessor is a programmable device that takes in numbers performs on them arithmetic or logical operations according to the program stored in memory and then produces other numbers as a result. The microprocessor is a programmable device that takes in numbers performs on them arithmetic or logical operations according to the program stored in memory and then produces other numbers as a result. 3

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Microprocessor A microprocessor is multi programmable clock driven register based semiconductor device that is used to fetch process execute a data within fraction of seconds. A microprocessor is multi programmable clock driven register based semiconductor device that is used to fetch process execute a data within fraction of seconds. 4

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Applications • Calculators • Accounting system • Games machine • Instrumentation • Traffic light Control • Multi user multi-function environments • Military applications • Communication systems • Calculators • Accounting system • Games machine • Instrumentation • Traffic light Control • Multi user multi-function environments • Military applications • Communication systems 5

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MICROPROCESSOR HISTORY 6

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DIFFERENT PROCESSORS AVAILABLE Socket Pinless Processor Processor Slot Processor Processor Slot 7

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Development of Intel Microprocessors • 8086 - 1979 • 286 - 1982 • 386 - 1985 • 486 - 1989 • Pentium - 1993 • Pentium Pro - 1995 • Pentium MMX -1997 • Pentium II - 1997 • Pentium II Celeron - 1998 • Pentium II Zeon - 1998 • Pentium III - 1999 • Pentium III Zeon - 1999 • Pentium IV - 2000 • Pentium IV Zeon - 2001 • 8086 - 1979 • 286 - 1982 • 386 - 1985 • 486 - 1989 • Pentium - 1993 • Pentium Pro - 1995 • Pentium MMX -1997 • Pentium II - 1997 • Pentium II Celeron - 1998 • Pentium II Zeon - 1998 • Pentium III - 1999 • Pentium III Zeon - 1999 • Pentium IV - 2000 • Pentium IV Zeon - 2001 8

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GENERATION OF PROCESSORS Processor Bits Speed 8080 8 2 MHz 8086 16 4.5 – 10 MHz 4.5 – 10 MHz 8088 16 4.5 – 10 MHz 80286 16 10 – 20 MHz 80386 32 20 – 40 MHz 80486 32 40 – 133 MHz 9

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GENERATION OF PROCESSORS Processor Bits Speed Pentium 32 60 – 233 MHz Pentium Pro 32 150 – 200 MHz Pentium II Celeron Xeon 32 233 – 450 MHz Pentium II Celeron Xeon 32 233 – 450 MHz Pentium III Celeron Xeon 32 450 MHz – 1.4 GHz Pentium IV Celeron Xeon 32 1.3 GHz – 3.8 GHz Itanium 64 800 MHz – 3.0 GHz 10

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Intel 4004 Introduced in 1971. It was the first microprocessor by Intel. It was a 4-bit µP . Its clock speed was 740KHz. It had 2300 transistors. It could execute around 60000 instructions per second. Introduced in 1971. It was the first microprocessor by Intel. It was a 4-bit µP . Its clock speed was 740KHz. It had 2300 transistors. It could execute around 60000 instructions per second. 11

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Intel 4040 Introduced in 1971. It was also 4-bit µP . 12

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8-bit Microprocessors 13

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Intel 8008 Introduced in 1972. It was first 8-bit µP . Its clock speed was 500 KHz. Could execute 50000 instructions per second. Introduced in 1972. It was first 8-bit µP . Its clock speed was 500 KHz. Could execute 50000 instructions per second. 14

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Intel 8080 Introduced in 1974. It was also 8-bit µP . Its clock speed was 2 MHz. It had 6000 transistors. Introduced in 1974. It was also 8-bit µP . Its clock speed was 2 MHz. It had 6000 transistors. 15

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Intel 8085 Introduced in 1976. It was also 8-bit µP . Its clock speed was 3 MHz. Its data bus is 8-bit and address bus is 16-bit. It had 6500 transistors. Could execute 769230 instructions per second. It could access 64 KB of memory. It had 246 instructions. Introduced in 1976. It was also 8-bit µP . Its clock speed was 3 MHz. Its data bus is 8-bit and address bus is 16-bit. It had 6500 transistors. Could execute 769230 instructions per second. It could access 64 KB of memory. It had 246 instructions. 16

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16-bit Microprocessors 17

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INTEL 8086 Introduced in 1978. It was first 16-bit µP. Its clock speed is 4.77 MHz 8 MHz and 10 MHz depending on the version. Its data bus is 16-bit and address bus is 20-bit. It had 29000 transistors. Could execute 2.5 million instructions per second. It could access 1 MB of memory. It had 22000 instructions. It hadMultiply andDivide instructions. Introduced in 1978. It was first 16-bit µP. Its clock speed is 4.77 MHz 8 MHz and 10 MHz depending on the version. Its data bus is 16-bit and address bus is 20-bit. It had 29000 transistors. Could execute 2.5 million instructions per second. It could access 1 MB of memory. It had 22000 instructions. It hadMultiply andDivide instructions. 18

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INTEL 8088 Introduced in 1979. It was also 16-bit µP. It was created as a cheaper version of Intels 8086. It was a 16-bit processor with an 8-bit external bus. Introduced in 1979. It was also 16-bit µP. It was created as a cheaper version of Intels 8086. It was a 16-bit processor with an 8-bit external bus. 19

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INTEL 80186 80188 Introduced in 1982. They were 16-bit µPs. Clock speed was 6 MHz. 80188 was a cheaper version of 80186 with an 8-bit external data bus. Introduced in 1982. They were 16-bit µPs. Clock speed was 6 MHz. 80188 was a cheaper version of 80186 with an 8-bit external data bus. 20

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INTEL 80286 Introduced in 1982. It was 16-bit µP. Its clock speed was 8 MHz. Its data bus is 16-bit and address bus is 24- bit. It could address 16 MB of memory. It had 134000 transistors. Introduced in 1982. It was 16-bit µP. Its clock speed was 8 MHz. Its data bus is 16-bit and address bus is 24- bit. It could address 16 MB of memory. It had 134000 transistors. 21

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32-BIT MICROPROCESSORS 22

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INTEL 80386 Introduced in 1986. It was first 32-bit µP. Its data bus is 32-bit and address bus is 32- bit. It could address 4 GB of memory. It had 275000 transistors. Its clock speed varied from 16 MHz to 33 MHz depending upon the various versions. Introduced in 1986. It was first 32-bit µP. Its data bus is 32-bit and address bus is 32- bit. It could address 4 GB of memory. It had 275000 transistors. Its clock speed varied from 16 MHz to 33 MHz depending upon the various versions. 23

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INTEL 80486 Introduced in 1989. It was also 32-bit µP. It had 1.2 million transistors. Its clock speed varied from 16 MHz to 100 MHz depending upon the various versions. 8 KB of cache memory was introduced. Introduced in 1989. It was also 32-bit µP. It had 1.2 million transistors. Its clock speed varied from 16 MHz to 100 MHz depending upon the various versions. 8 KB of cache memory was introduced. 24

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INTEL PENTIUM Introduced in 1993. It was also 32-bit µP. It was originally named 80586. Its clock speed was 66 MHz. Its data bus is 32-bit and address bus is 32- bit. Introduced in 1993. It was also 32-bit µP. It was originally named 80586. Its clock speed was 66 MHz. Its data bus is 32-bit and address bus is 32- bit. 25

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INTEL PENTIUM PRO Introduced in 1995. It was also 32-bit µP. It had 21 million transistors. Cache memory: 8 KB for instructions. 8 KB for data. Introduced in 1995. It was also 32-bit µP. It had 21 million transistors. Cache memory: 8 KB for instructions. 8 KB for data. 26

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INTEL PENTIUM II Introduced in 1997. It was also 32-bit µP. Its clock speed was 233 MHz to 500 MHz. Could execute 333 million instructions per second. Introduced in 1997. It was also 32-bit µP. Its clock speed was 233 MHz to 500 MHz. Could execute 333 million instructions per second. 27

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INTEL PENTIUM II XEON Introduced in 1998. It was also 32-bit µP. It was designed for servers. Its clock speed was 400 MHz to 450 MHz. Introduced in 1998. It was also 32-bit µP. It was designed for servers. Its clock speed was 400 MHz to 450 MHz. 28

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INTEL PENTIUM III Introduced in 1999. It was also 32-bit µP. Its clock speed varied from 500 MHz to 1.4 GHz. It had 9.5 million transistors. Introduced in 1999. It was also 32-bit µP. Its clock speed varied from 500 MHz to 1.4 GHz. It had 9.5 million transistors. 29

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INTEL PENTIUM IV Introduced in 2000. It was also 32-bit µP. Its clock speed was from 1.3 GHz to 3.8 GHz. It had 42 million transistors. Introduced in 2000. It was also 32-bit µP. Its clock speed was from 1.3 GHz to 3.8 GHz. It had 42 million transistors. 30

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INTEL DUAL CORE Introduced in 2006. It is 32-bit or 64-bit µP. 31

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32

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64-BIT MICROPROCESSORS 33

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Intel Core 2 Intel Core i3 34

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INTEL CORE I5 INTEL CORE I7 35

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Basic Terms • Bit: A digit of the binary number 0 or 1 • Nibble: 4 bit Byte: 8 bit word: 16 bit • Double word: 32 bit • Data: binary number/code operated by an instruction • Address: Identification number for memory locations • Clock: square wave used to synchronize various devices in µP • Memory Capacity 2n n-no. of address lines • Bit: A digit of the binary number 0 or 1 • Nibble: 4 bit Byte: 8 bit word: 16 bit • Double word: 32 bit • Data: binary number/code operated by an instruction • Address: Identification number for memory locations • Clock: square wave used to synchronize various devices in µP • Memory Capacity 2n n-no. of address lines 36

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BUS CONCEPT • BUS: Group of conducting lines that carries data address control signals. CLASSIFICATION OF BUSES: 1.DATA BUS: group of conducting lines that carries data. 2. ADDRESS BUS: group of conducting lines that carries address. 3.CONTROL BUS: group of conducting lines that carries control signals RD WR etc CPU BUS: group of conducting lines that directly connected to µP SYSTEM BUS: group of conducting lines that carries data address control signals in a µP system • BUS: Group of conducting lines that carries data address control signals. CLASSIFICATION OF BUSES: 1.DATA BUS: group of conducting lines that carries data. 2. ADDRESS BUS: group of conducting lines that carries address. 3.CONTROL BUS: group of conducting lines that carries control signals RD WR etc CPU BUS: group of conducting lines that directly connected to µP SYSTEM BUS: group of conducting lines that carries data address control signals in a µP system 37

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TRISTATE LOGIC 3 logic levels are: • High State logic 1 • Low state logic 0 • High Impedance state High Impedance: output is not being driven to any defined logic level by the output circuit. 3 logic levels are: • High State logic 1 • Low state logic 0 • High Impedance state High Impedance: output is not being driven to any defined logic level by the output circuit. 38

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Basic Microprocessors System Input Devices Processing Data into Information Output Devices Control Control Unit Unit Arithmetic Arithmetic- - Logic Logic Unit Unit Central Processing Unit Input Devices Processing Data into Information Output Devices Secondary Storage Devices Primary Storage Primary Storage Unit Unit Keyboard Mouse etc Monitor Printer Disks Tapes Optical Disks 39

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UNIT UNIT 1 1 THE 8086 MICROPROCESSOR UNIT UNIT 1 1 40

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8086 Microprocessor-introduction INTEL launched 8086 in 1978 8086 is a 16-bit microprocessor with • 16-bit Data Bus D0-D15 • 20-bit Address Bus A0-A19 can access upto 220 1 MB memory locations . It has multiplexed address and data bus AD0-AD15 and A16–A19. It can support upto 64K I/O ports INTEL launched 8086 in 1978 8086 is a 16-bit microprocessor with • 16-bit Data Bus D0-D15 • 20-bit Address Bus A0-A19 can access upto 220 1 MB memory locations . It has multiplexed address and data bus AD0-AD15 and A16–A19. It can support upto 64K I/O ports 41

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8086 Microprocessor It provides 14 16-bit registers. 8086 requires one phase clock with a 33 duty cycle to provide optimized internal timing. – Range of clock: • 5 MHz for 8086 • 8Mhz for 8086-2 • 10Mhz for 8086-1 It provides 14 16-bit registers. 8086 requires one phase clock with a 33 duty cycle to provide optimized internal timing. – Range of clock: • 5 MHz for 8086 • 8Mhz for 8086-2 • 10Mhz for 8086-1 42

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INTEL 8086 - Pin Diagram/Signal Description 43

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INTEL 8086 - Pin Details Ground Power Supply 5V 10 Reset Registers seg regs flags CS: FFFFH IP: 0000H If high for minimum 4 clks Clock Duty cycle: 33 Reset Registers seg regs flags CS: FFFFH IP: 0000H If high for minimum 4 clks 44

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INTEL 8086 - Pin Details Address/Data Bus: Contains address bits A 15 -A 0 when ALE is 1 data bits D 15 D 0 when ALE is 0. Address Latch Enable: When high multiplexed address/data bus contains address information. Address/Data Bus: Contains address bits A 15 -A 0 when ALE is 1 data bits D 15 D 0 when ALE is 0. Address Latch Enable: When high multiplexed address/data bus contains address information. 45

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INTEL 8086 - Pin Details INTERRUPT Non - maskable interrupt Interrupt request Interrupt acknowledge 46

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INTEL 8086 - Pin Details Direct Memory Access Hold Hold acknowledge Hold 47

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INTEL 8086 - Pin Details Address/Status Bus Address bits A 19 A 16 Status bits S 6 S 3 48

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INTEL 8086 - Pin Details Bus High Enable/S7 Enables most significant data bits D 15 D 8 during read or write operation. S 7 : Always 1. BHE A 0 : 00: Whole word 16-bits 01: High byte to/from odd address 10: Low byte to/from even address 11: No selection Bus High Enable/S7 Enables most significant data bits D 15 D 8 during read or write operation. S 7 : Always 1. BHE A 0 : 00: Whole word 16-bits 01: High byte to/from odd address 10: Low byte to/from even address 11: No selection 49

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INTEL 8086 - Pin Details Min/Max mode Minimum Mode: +5V Maximum Mode: 0V Minimum Mode Pins Maximum Mode Pins 50

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Minimum Mode- Pin Details Read Signal Write Signal Write Signal Memory or I/0 Data Bus Enable Data Transmit/Receive 51

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Maximum Mode - Pin Details S2 S1 S0 000: INTA 001: read I/O port 010: write I/O port 011: halt 100: code access 101: read memory 110: write memory 111: none -passive Status Signal Inputs to 8288 to generate eliminated signals due to max mode. S2 S1 S0 000: INTA 001: read I/O port 010: write I/O port 011: halt 100: code access 101: read memory 110: write memory 111: none -passive 52

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Maximum Mode - Pin Details DMA Request/Grant Lock Output Used to lock peripherals off the system Activated by using the LOCK: prefix on any instruction DMA Request/Grant Lock Output Lock Output Used to lock peripherals off the system Activated by using the LOCK: prefix on any instruction 53

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Maximum Mode - Pin Details QS1 QS0 00: Queue is idle 01: First byte of opcode 10: Queue is empty 11: Subsequent byte of opcode Queue Status Used by numeric coprocessor 8087 QS1 QS0 00: Queue is idle 01: First byte of opcode 10: Queue is empty 11: Subsequent byte of opcode 54

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8086 Internal Architecture 8086 employs parallel processing 8086 CPU has two parts which operate at the same time • Bus Interface Unit • Execution Unit CPU functions 1. Fetch 2. Decode 3. Execute 8086 CPU 8086 employs parallel processing 8086 CPU has two parts which operate at the same time • Bus Interface Unit • Execution Unit CPU functions 1. Fetch 2. Decode 3. Execute Bus Interface Unit BIU Execution Unit EU 55

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Bus Interface Unit Sends out addresses for memory locations Fetches Instructions from memory Reads/Writes data to memory Sends out addresses for I/O ports Reads/Writes data to Input/Output ports Sends out addresses for memory locations Fetches Instructions from memory Reads/Writes data to memory Sends out addresses for I/O ports Reads/Writes data to Input/Output ports 56

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Execution Unit Tells BIU addresses where to fetch instructions or data Decodes Executes instructions Dividing the work between BIU EU speeds up processing Tells BIU addresses where to fetch instructions or data Decodes Executes instructions Dividing the work between BIU EU speeds up processing 57

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Architecture Diagram of 8086 Architecture Diagram of 8086 58

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EXTRA SEGMENT ES CODE SEGMENT CS STACK SEGMENT SS DATA SEGMENT DS INSTRUCTION POINTER IP 6 5 4 3 2 1 Instruction Queue Memory Interface BIU AH AL BH BL CH CL DH DL STACK POINTER SP BASE POINTER BP SOURCE INDEX SI DESTINATION INDEX DI CONTROL SYSTEM ARITHMETIC LOGIC UNIT FLAGS OPERANDS EU Instruction Decoder 59

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Execution Unit Main components are • Instruction Decoder • Control System • Arithmetic Logic Unit • General Purpose Registers • Flag Register • Pointer Index registers Main components are • Instruction Decoder • Control System • Arithmetic Logic Unit • General Purpose Registers • Flag Register • Pointer Index registers 60

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Instruction Decoder Translates instructions fetched from memory into a series of actions which EU carries out Control System Generates timing and control signals to perform the internal operations of the microprocessor Generates timing and control signals to perform the internal operations of the microprocessor Arithmetic Logic Unit EU has a 16-bit ALU which can ADD SUBTRACT AND OR increment decrement complement or shift binary numbers 61

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General Purpose Registers EU has 8 general purpose registers Can be individually used for storing 8-bit data AL register is also called Accumulator Two registers can also be combined to form 16-bit registers The valid register pairs are – AX BX CX DX AH AL BH BL CH CL DH DL EU has 8 general purpose registers Can be individually used for storing 8-bit data AL register is also called Accumulator Two registers can also be combined to form 16-bit registers The valid register pairs are – AX BX CX DX DH DL AH AL AX BH BL BX CH CL CX DH DL DX 62

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Flag Register 8086 has a 16-bit flag register Contains 9 active flags There are two types of flags in 8086 • Conditional flags – six flags set or reset by EU on the basis of results of some arithmetic operations • Control flags – three flags used to control certain operations of the processor 8086 has a 16-bit flag register Contains 9 active flags There are two types of flags in 8086 • Conditional flags – six flags set or reset by EU on the basis of results of some arithmetic operations • Control flags – three flags used to control certain operations of the processor 63

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U U U U OF DF IF TF SF ZF U AF U PF U CF Flag Register 1. CF CARRY FLAG Conditional Flags Compatible with 8085 except OF 2. PF PARITY FLAG 3. AF AUXILIARY CARRY Conditional Flags Compatible with 8085 except OF 3. AF AUXILIARY CARRY 4. ZF ZERO FLAG 5. SF SIGN FLAG 6. OF OVERFLOW FLAG 7. TF TRAP FLAG Control Flags 8. IF INTERRUPT FLAG 9. DF DIRECTION FLAG 64

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Flag Register Carry Flag This flag is set when there is a carry out of MSB in case of addition or a borrow in case of subtraction. Parity Flag This flag is set to 1 if the lower byte of the result contains even number of 1’s for odd number of 1’s set to zero. Auxiliary Carry Flag This is set if there is a carry from the lowest nibble i.e bit three during addition or borrow for the lowest nibble i.e bit three during subtraction. Zero Flag This flag is set if the result of the computation or comparison performed by an instruction is zero Sign Flag This flag is set when the result of any computation is negative 65 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF DF IF TF SF ZF AF PF CF Tarp Flag If this flag is set the processor enters the single step execution mode by generating internal interrupts after the execution of each instruction Interrupt Flag Causes the 8086 to recognize external mask interrupts clearing IF disables these interrupts. Direction Flag This is used by string manipulation instructions. If this flag bit is ‘0’ the string is processed beginning from the lowest address to the highest address i.e. auto incrementing mode. Otherwise the string is processed from the highest address towards the lowest address i.e. auto incrementing mode. Over flow Flag This flag is set if an overflow occurs i.e if the result of a signed operation is large enough to accommodate in a destination register. The result is of more than 7-bits in size in case of 8-bit signed operation and more than 15-bits in size in case of 16-bit sign operations then the overflow will be set.

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Registers Flag Sl.No. Type Register width Name of register 1 General purpose register 16 bit AX BX CX DX 8086 registers categorized into 4 groups 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF DF IF TF SF ZF AF PF CF 66 1 General purpose register 16 bit AX BX CX DX 8 bit AL AH BL BH CL CH DL DH 2 Pointer register 16 bit SP BP 3 Index register 16 bit SI DI 4 Instruction Pointer 16 bit IP 5 Segment register 16 bit CS DS SS ES 6 Flag PSW 16 bit Flag register

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Register Name of the Register Special Function AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations BX Base register Used to hold base value in base addressing mode to access memory data CX Count Register Used to hold the count value in SHIFT ROTATE and LOOP instructions Registers and Special Functions 67 Used to hold the count value in SHIFT ROTATE and LOOP instructions DX Data Register Used to hold data for multiplication and division operations SP Stack Pointer Used to hold the offset address of top stack memory BP Base Pointer Used to hold the base value in base addressing using SS register to access data from stack memory SI Source Index Used to hold index value of source operand data for string instructions DI Data Index Used to hold the index value of destination operand data for string operations

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Bus Interface Unit Main Components are • Instruction Queue • Segment Registers • Instruction Pointer Main Components are • Instruction Queue • Segment Registers • Instruction Pointer 68

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EXTRA SEGMENT ES CODE SEGMENT CS STACK SEGMENT SS DATA SEGMENT DS INSTRUCTION POINTER IP 6 5 4 3 2 1 Instruction Queue Memory Interface BIU AH AL BH BL CH CL DH DL STACK POINTER SP BASE POINTER BP SOURCE INDEX SI DESTINATION INDEX DI CONTROL SYSTEM ARITHMETIC LOGIC UNIT FLAGS OPERANDS EU Instruction Decoder 69

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Instruction Queue 8086 employs parallel processing When EU is busy decoding or executing current instruction the buses of 8086 may not be in use. At that time BIU can use buses to fetch upto six instruction bytes for the following instructions BIU stores these pre-fetched bytes in a FIFO register called Instruction Queue When EU is ready for its next instruction it simply reads the instruction from the queue in BIU 8086 employs parallel processing When EU is busy decoding or executing current instruction the buses of 8086 may not be in use. At that time BIU can use buses to fetch upto six instruction bytes for the following instructions BIU stores these pre-fetched bytes in a FIFO register called Instruction Queue When EU is ready for its next instruction it simply reads the instruction from the queue in BIU 70

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Pipelining EU of 8086 does not have to wait in between for BIU to fetch next instruction byte from memory So the presence of a queue in 8086 speeds up the processing Fetching the next instruction while the current instruction executes is called pipelining EU of 8086 does not have to wait in between for BIU to fetch next instruction byte from memory So the presence of a queue in 8086 speeds up the processing Fetching the next instruction while the current instruction executes is called pipelining 71

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Memory Segmentation 8086 has a 20-bit address bus So it can address a maximum of 1MB of memory 8086 can work with only four 64KB segments at a time within this 1MB range These four memory segments are called • Code segment • Stack segment • Data segment • Extra segment 8086 has a 20-bit address bus So it can address a maximum of 1MB of memory 8086 can work with only four 64KB segments at a time within this 1MB range These four memory segments are called • Code segment • Stack segment • Data segment • Extra segment 72

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1 2 3 4 5 6 7 8 Memory 00000H 1MB Address Range 64KB Memory Segment Only 4 such segments can be addressed at a time 4 5 6 7 8 9 10 11 12 13 14 15 16 FFFFFH 1MB Address Range 73

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Code Segment That part of memory from where BIU is currently fetching instruction code bytes Stack Segment A section of memory set aside to store addresses and data while a subprogram executes A section of memory set aside to store addresses and data while a subprogram executes Data Extra Segments Used for storing data values to be used in the program 74

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1 2 3 4 5 6 7 8 Memory 00000H 1MB Address Range Code Segment Data Extra Segments 8 9 10 11 12 13 14 15 16 FFFFFH 1MB Address Range Stack Segment 75

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Segment Registers hold the upper 16-bits of the starting address for each of the segments The four segment registers are • CS Code Segment register • DS Data Segment register • SS Stack Segment register • ES Extra Segment register hold the upper 16-bits of the starting address for each of the segments The four segment registers are • CS Code Segment register • DS Data Segment register • SS Stack Segment register • ES Extra Segment register 76

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1 Code Segment 3 4 Data Segment Extra Segment 7 8 Memory 00000H 1MB Address Range Starting Addresses of Segments 1000 0H 4000 0H 5000 0H CS DS ES 9 10 11 12 13 14 15 Stack Segment FFFFFH 1MB Address Range Starting Addresses of Segments F000 0H SS 77

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Address of a segment is of 20-bits A segment register stores only upper 16- bits BIU always inserts zeros for the lowest 4- bits of the 20-bit starting address. E.g. if CS 348AH then the code segment will start at 348A0H A 64-KB segment can be located anywhere in the memory but will start at an address with zeros in the lowest 4-bits Address of a segment is of 20-bits A segment register stores only upper 16- bits BIU always inserts zeros for the lowest 4- bits of the 20-bit starting address. E.g. if CS 348AH then the code segment will start at 348A0H A 64-KB segment can be located anywhere in the memory but will start at an address with zeros in the lowest 4-bits 78

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Instruction Pointer IP Register a 16-bit register Holds 16-bit offset of the next instruction byte in the code segment BIU uses IP and CS registers to generate the 20-bit address of the instruction to be fetched from memory a 16-bit register Holds 16-bit offset of the next instruction byte in the code segment BIU uses IP and CS registers to generate the 20-bit address of the instruction to be fetched from memory 79

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1 Data Segment 3 4 Code Segment Extra Segment 7 Memory 00000H 1MB Address Range Start of Code Segment 348A0H Code Byte MOV AL BL 38AB4H IP 4214H Physical Address Calculation 7 8 9 10 11 12 13 14 15 Stack Segment FFFFFH 1MB Address Range 348A H 4214 H 38AB4 H CS IP Physical Address + 0 80

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Stack Segment SS Register Stack Pointer SP Register Upper 16-bits of the starting address of stack segment is stored in SS register It is located in BIU SP register holds a 16-bit offset from the start of stack segment to the top of the stack It is located in EU Upper 16-bits of the starting address of stack segment is stored in SS register It is located in BIU SP register holds a 16-bit offset from the start of stack segment to the top of the stack It is located in EU 81

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Other Pointer Index Registers Base Pointer BP register Source Index SI register Destination Index DI register Can be used for temporary storage of data Main use is to hold a 16-bit offset of a data word in one of the segments Base Pointer BP register Source Index SI register Destination Index DI register Can be used for temporary storage of data Main use is to hold a 16-bit offset of a data word in one of the segments 82

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ADDRESSING MODES OF 8086 ADDRESSING MODES OF 8086 83

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Various Addressing Modes 1. Immediate Addressing Mode 2. Register Addressing Mode 3. Direct Addressing Mode 4. Register Indirect Addressing Mode 5. Index Addressing Mode 6. Based Addressing Mode 7. Based Indexed Addressing Mode 8. Based Indexed with displacement Addressing Mode 9. Strings Addressing Mode 1. Immediate Addressing Mode 2. Register Addressing Mode 3. Direct Addressing Mode 4. Register Indirect Addressing Mode 5. Index Addressing Mode 6. Based Addressing Mode 7. Based Indexed Addressing Mode 8. Based Indexed with displacement Addressing Mode 9. Strings Addressing Mode 84 Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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1. IMMEDIATE ADDRESSING MODE • The instruction will specify the name of the register which holds the data to be operated by the instruction. • Source data is within the instruction • Ex: MOV AX10ABH ALABH AH10H • The instruction will specify the name of the register which holds the data to be operated by the instruction. • Source data is within the instruction • Ex: MOV AX10ABH ALABH AH10H 85

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2.REGISTER ADDRESSING MODE • In immediate addressing mode an 8-bit or 16-bit data is specified as part of the instruction • Ex: MOV AXBLH MOV AXBLH • In immediate addressing mode an 8-bit or 16-bit data is specified as part of the instruction • Ex: MOV AXBLH MOV AXBLH 86

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3. DIRECT ADDRESSING MODE • Memory address is supplied with in the instruction • Mnemonic: MOV AHMEMBDS AH 1000H • But the memory address is not index or pointer register • Memory address is supplied with in the instruction • Mnemonic: MOV AHMEMBDS AH 1000H • But the memory address is not index or pointer register 87

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4. REGISTER INDIRECT ADDRESSING MODE • Memory address is supplied in an index or pointer register • EX: MOV AXSI AL SI AH SI+1 JMP DI IP DI+1: DI INC BYTE PTR BP BP BP+1 DEC WORD PTR BX BX+1:BX BX+1:BX-1 • Memory address is supplied in an index or pointer register • EX: MOV AXSI AL SI AH SI+1 JMP DI IP DI+1: DI INC BYTE PTR BP BP BP+1 DEC WORD PTR BX BX+1:BX BX+1:BX-1 88

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5.Indexed Addressing Mode • Memory address is the sum of index register plus displacement MOV AXSI+2 AL SI+2 AH SI+3 JMP DI+2 IP BX+3:BX+2 • Memory address is the sum of index register plus displacement MOV AXSI+2 AL SI+2 AH SI+3 JMP DI+2 IP BX+3:BX+2 89

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6. Based Addressing Mode • Memory address is the sum of the BX or BP base register plus a displacement within instruction • Ex: MOV AXBP+2 AL BP+2 AH BP+3 JMP BX+2 IP BX+3:BX+2 • Memory address is the sum of the BX or BP base register plus a displacement within instruction • Ex: MOV AXBP+2 AL BP+2 AH BP+3 JMP BX+2 IP BX+3:BX+2 90

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7.BASED INDEX ADDRESSING MODES • Memory address is the sum of the index register base register Ex: MOV AXBX+SI AL BX+SI AH BX+SI+1 JMP BX+DI IP BX+DI+1 : BX+DI INC BYTE PTR BP+SI BP BP+1 DEC WORD PTR BP+DI BX+1:BX BX+1:BX-1 • Memory address is the sum of the index register base register Ex: MOV AXBX+SI AL BX+SI AH BX+SI+1 JMP BX+DI IP BX+DI+1 : BX+DI INC BYTE PTR BP+SI BP BP+1 DEC WORD PTR BP+DI BX+1:BX BX+1:BX-1 91

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8. BASED INDEXED WITH DISPLACEMENT ADDRESSING MODE • Memory address is the sum of an index register base register and displacement within instruction MOV AXBX+SI+6 AL BX+SI+6 AH BX+SI+7 JMP BX+DI+6 IP BX+DI+7 : BX+DI+6 INC BYTE PTR BP+SI+5 DEC WORD PTR BP+DI+5 • Memory address is the sum of an index register base register and displacement within instruction MOV AXBX+SI+6 AL BX+SI+6 AH BX+SI+7 JMP BX+DI+6 IP BX+DI+7 : BX+DI+6 INC BYTE PTR BP+SI+5 DEC WORD PTR BP+DI+5 92 Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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9. Strings Addressing Mode • The memory source address is a register SI in the data segment and the memory destination address is register DI in the extra segment • Ex: MOVSB ES:DI DS:SI • If DF0 SI SI+1 DI DI+1 DF1 SI SI-1 DI DI-1 • The memory source address is a register SI in the data segment and the memory destination address is register DI in the extra segment • Ex: MOVSB ES:DI DS:SI • If DF0 SI SI+1 DI DI+1 DF1 SI SI-1 DI DI-1 93

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INSTRUCTION SET of 8086 INSTRUCTION SET of 8086 94

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• Instruction:- An instruction is a binary pattern designed inside a microprocessor to perform a specific function. • Opcode:- It stands for operational code. It specifies the type of operation to be performed by CPU. It is the first field in the machine language instruction format. • E.g. 08 is the opcode for instruction MOV XY. • Operand:- We can also say it as data on which operation should act. operands may be register values or memory values. The CPU executes the instructions using information present in this field. It may be 8-bit data or 16-bit data. Instruction set basics • Instruction:- An instruction is a binary pattern designed inside a microprocessor to perform a specific function. • Opcode:- It stands for operational code. It specifies the type of operation to be performed by CPU. It is the first field in the machine language instruction format. • E.g. 08 is the opcode for instruction MOV XY. • Operand:- We can also say it as data on which operation should act. operands may be register values or memory values. The CPU executes the instructions using information present in this field. It may be 8-bit data or 16-bit data. 95

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• Assembler:- it converts the instruction into sequence of binary bits so that this bits can be read by the processor. • Mnemonics:- these are the symbolic codes for either instructions or commands to perform a particular function. • E.g. MOV ADD SUB etc. Instruction set basics • Assembler:- it converts the instruction into sequence of binary bits so that this bits can be read by the processor. • Mnemonics:- these are the symbolic codes for either instructions or commands to perform a particular function. • E.g. MOV ADD SUB etc. 96

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T ypes of instruction set of 8086 T ypes of instruction set of 8086 microprocessor microprocessor 1. Data Copy/Transfer instructions. 2. Arithmetic Logical instructions. 3. Branch instructions. 4. Loop instructions. 5. Machine Control instructions. 6. Flag Manipulation instructions. 7. Shift Rotate instructions. 8. String instructions. 1. Data Copy/Transfer instructions. 2. Arithmetic Logical instructions. 3. Branch instructions. 4. Loop instructions. 5. Machine Control instructions. 6. Flag Manipulation instructions. 7. Shift Rotate instructions. 8. String instructions. 97

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1. Data copy/transfer instructions.1. Data copy/transfer instructions. 1. MOV Destination Source There will be transfer of data from source to destination. Source can be register memory location or immediate data. Destination can be register or memory operand. Both Source and Destination cannot be memory location or segment registers at the same time. E.g. 1. MOV CX 037A H 2. MOV AL BL 3. MOV BX 0301 H 1. MOV Destination Source There will be transfer of data from source to destination. Source can be register memory location or immediate data. Destination can be register or memory operand. Both Source and Destination cannot be memory location or segment registers at the same time. E.g. 1. MOV CX 037A H 2. MOV AL BL 3. MOV BX 0301 H 98

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BX 2000H AX 2000H BEFORE EXECUTION AFTER EXECUTION MOV BXAX BEFORE EXECUTION AFTER EXECUTION A H AL B H BL C H CL D H DL A H AL B H BL C H CL 40 D H DL MOV CLM 40 40 BEFORE EXECUTION AFTER EXECUTION 99

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Stack Pointer Stack Pointer It is a 16-bit register contains the address of the data item currently on top of the stack. Stack operation includes pushing providing data on to the stack and popping takingdata from the stack. Pushing operation decrements stack pointer and Popping operation increments stack pointer. i.e. there is a last in first outLIFO operation. It is a 16-bit register contains the address of the data item currently on top of the stack. Stack operation includes pushing providing data on to the stack and popping takingdata from the stack. Pushing operation decrements stack pointer and Popping operation increments stack pointer. i.e. there is a last in first outLIFO operation. 100

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2. Push Source2. Push Source Source can be register segment register or memory. This instruction pushes the contents of specified source on to the stack. In this stack pointer is decremented by 2. The higher byte data is pushed first SP-1. Then lower byte data is pushed SP-2. E.g.: 1. PUSH AX 2. PUSH DS 3. PUSH 5000H Source can be register segment register or memory. This instruction pushes the contents of specified source on to the stack. In this stack pointer is decremented by 2. The higher byte data is pushed first SP-1. Then lower byte data is pushed SP-2. E.g.: 1. PUSH AX 2. PUSH DS 3. PUSH 5000H 101

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INITIAL POSITION DECREMENTS SP STORES HIGHER BYTE 1 STACK POINTER 2 STACK POINTER HIGHER BYTE DECREMENTS SP STORES LOWER BYTE LOWER BYTE HIGHER BYTE 2 STACK POINTER 3 STACK POINTER 102

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BH BL CH 10 CL 50 DH DL SP 2002H BEFORE EXECUTION 2000H 2001H 2002H PUSH CX BH BL CH 10 CL 50 DH DL 50 10 SP 2000H AFTER EXECUTION 2000H 2001H 2002H PUSH CX 103

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3 POP Destination3 POP Destination Destination can be register segment register or memory. This instruction pops takes the contents of specified destination. In this stack pointer is incremented by 2. The lower byte data is popped first SP+1. Then higher byte data is popped SP+2. E.g. 1. POP AX 2. POP DS 3. POP 5000H Destination can be register segment register or memory. This instruction pops takes the contents of specified destination. In this stack pointer is incremented by 2. The lower byte data is popped first SP+1. Then higher byte data is popped SP+2. E.g. 1. POP AX 2. POP DS 3. POP 5000H 104

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INITIAL POSITION AND READS LOWER BYTE LOWER BYTE INCREMENTS SP READS HIGHER BYTE LOWER BYTE 1 STACK POINTER 2 STACK POINTER LOWER BYTE HIGHER BYTE INCREMENTS SP LOWER BYTE HIGHER BYTE 2 STACK POINTER 3 STACK POINTER 105

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BH BL SP 2000H 30 50 BEFORE EXECUTION POP BX 2000H 2001H 2002H BH 5 0 BL 30 SP 2002H 30 50 AFTER EXECUTION POP BX 2000H 2001H 2002H 106

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4. XCHG Destination source4. XCHG Destination source • This instruction exchanges contents of Source with destination. • It cannot exchange two memory locations directly. •The contents of AL are exchanged with BL. •The contents of AH are exchanged with BH. •E.g. 1. XCHG BX AX 2. XCHG 5000HAX • This instruction exchanges contents of Source with destination. • It cannot exchange two memory locations directly. •The contents of AL are exchanged with BL. •The contents of AH are exchanged with BH. •E.g. 1. XCHG BX AX 2. XCHG 5000HAX 107

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AH 20 AL 40 AH 70 AL 80 BEFORE EXECUTION AFTER EXECUTION BH 70 BL 80 BH 20 BL 40 XCHG AXBX 108

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5IN AL/AX 85IN AL/AX 8- -bit/16 bit/16- -bit port address bit port address It reads from the specified port address. It copies data to accumulator from a port with 8- bit or 16-bit address. DX is the only register is allowed to carry port address. E.g. 1. IN AL 80H 2. IN AXDX //DX contains address of 16-bit port. It reads from the specified port address. It copies data to accumulator from a port with 8- bit or 16-bit address. DX is the only register is allowed to carry port address. E.g. 1. IN AL 80H 2. IN AXDX //DX contains address of 16-bit port. 109

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10 AL BEFORE EXECUTION IN AL80H PORT 80H 10 AL 10 AFTER EXECUTION IN AL80H PORT 80H 110

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OUT 8 OUT 8- -bit/16 bit/16- -bit port address AL/AX bit port address AL/AX It writes to the specified port address. It copies contents of accumulator to the port with 8-bit or 16-bit address. DX is the only register is allowed to carry port address. E.g. 1. OUT 80HAL 2. OUT DXAX //DX contains address of 16-bit port. It writes to the specified port address. It copies contents of accumulator to the port with 8-bit or 16-bit address. DX is the only register is allowed to carry port address. E.g. 1. OUT 80HAL 2. OUT DXAX //DX contains address of 16-bit port. 111

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10 AL 40 BEFORE EXECUTION OUT 50HAL PORT 50H 40 AL 40 AFTER EXECUTION OUT 50HAL PORT 50H 112

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7 XLAT7 XLAT Also known as translate instruction. It is used to find out codes in case of code conversion. i.e. it translates code of the key pressed to the corresponding 7-segment code. After execution this instruction contents of AL register always gets replaced. E.g. XLAT Also known as translate instruction. It is used to find out codes in case of code conversion. i.e. it translates code of the key pressed to the corresponding 7-segment code. After execution this instruction contents of AL register always gets replaced. E.g. XLAT 113

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8. 8.LEA 16 LEA 16- -bit register source address dest. bit register source address dest. LEA Also known as Load Effective Address LEA. It loads effective address formed by the destination into the source register. E.g. 1. LEA BXAddress 2. LEA SIAddressBX LEA Also known as Load Effective Address LEA. It loads effective address formed by the destination into the source register. E.g. 1. LEA BXAddress 2. LEA SIAddressBX 114

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9. LDS 16-bit register source address dest. 10. LES 16-bit register source address dest. LDS Also known as Load Data Segment LDS. LES Also known as Load Extra Segment LES. It loads the contents of DS Data Segment or ES Extra Segment contents of the destination to the contents of source register. E.g. 1. LDS BX5000H 2. LES BX5000H LDS Also known as Load Data Segment LDS. LES Also known as Load Extra Segment LES. It loads the contents of DS Data Segment or ES Extra Segment contents of the destination to the contents of source register. E.g. 1. LDS BX5000H 2. LES BX5000H 115

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10 20 5000H 5001H 20 10 1. LDS BX5000H 2. LES BX5000H BX 0 7 0 15 30 40 5001H 5002H 5003H 40 30 DS/ES 116

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11. LAHF:- This instruction loads the AH register from the contents of lower byte of the flag register. This command is used to observe the status of the all conditional flags of flag register. E.g. LAHF 12. SAHF:- This instruction sets or resets all conditional flags of flag register with respect to the corresponding bit positions. If bit position in AH is 1 then related flag is set otherwise flag will be reset. E.g. SAHF 11. LAHF:- This instruction loads the AH register from the contents of lower byte of the flag register. This command is used to observe the status of the all conditional flags of flag register. E.g. LAHF 12. SAHF:- This instruction sets or resets all conditional flags of flag register with respect to the corresponding bit positions. If bit position in AH is 1 then related flag is set otherwise flag will be reset. E.g. SAHF 117

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PUSH POP PUSH POP 13. PUSH F:- This instruction decrements the stack pointer by 2. It copies contents of flag register to the memory location pointed by stack pointer. E.g. PUSH F 14. POP F:- This instruction increments the stack pointer by 2. It copies contents of memory location pointed by stack pointer to the flag register. E.g. POP F 13. PUSH F:- This instruction decrements the stack pointer by 2. It copies contents of flag register to the memory location pointed by stack pointer. E.g. PUSH F 14. POP F:- This instruction increments the stack pointer by 2. It copies contents of memory location pointed by stack pointer to the flag register. E.g. POP F 118

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2. Arithmetic Instructions2. Arithmetic Instructions These instructions perform the operations like: Addition Subtraction Increment Decrement. These instructions perform the operations like: Addition Subtraction Increment Decrement. 119

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2. Arithmetic Instructions2. Arithmetic Instructions 1. ADD destination source This instruction adds the contents of source operand with the contents of destination operand. The source may be immediate data memory location or register. The destination may be memory location or register. The result is stored in destination operand. AX is the default destination register. E.g. 1. ADD AX2020H 2. ADD AXBX 1. ADD destination source This instruction adds the contents of source operand with the contents of destination operand. The source may be immediate data memory location or register. The destination may be memory location or register. The result is stored in destination operand. AX is the default destination register. E.g. 1. ADD AX2020H 2. ADD AXBX 120

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AH 10 AL 10 AFTER EXECUTION BEFORE EXECUTION ADD AX2020H AH 30 AL 30 1010 +2020 3030 AH 10 AL 10 BH 20 BL 20 AFTER EXECUTION BEFORE EXECUTION ADD AXBX 1010 +2020 3030 AH 30 AL 30 BH 20 BL 20 121

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ADC destination source ADC destination source This instruction adds the contents of source operand with the contents of destination operand with carry flag bit. The source may be immediate data memory location or register. The destination may be memory location or register. The result is stored in destination operand. AX is the default destination register. E.g. 1. ADC AX2020H 2. ADC AXBX This instruction adds the contents of source operand with the contents of destination operand with carry flag bit. The source may be immediate data memory location or register. The destination may be memory location or register. The result is stored in destination operand. AX is the default destination register. E.g. 1. ADC AX2020H 2. ADC AXBX 122

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3 INC source3 INC source This instruction increases the contents of source operand by 1. The source may be memory location or register. The source can not be immediate data. The result is stored in the same place. E.g. 1. INC AX 2. INC 5000H This instruction increases the contents of source operand by 1. The source may be memory location or register. The source can not be immediate data. The result is stored in the same place. E.g. 1. INC AX 2. INC 5000H 123

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AFTER EXECUTION BEFORE EXECUTION INC AX AH 10 AL 10 AH 10 AL 11 5000H AFTER EXECUTION BEFORE EXECUTION INC 5000H 1010 5000H 1011 124

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4. DEC source 4. DEC source This instruction decreases the contents of source operand by 1. The source may be memory location or register. The source can not be immediate data. The result is stored in the same place. E.g. 1. DEC AX 2. DEC 5000H This instruction decreases the contents of source operand by 1. The source may be memory location or register. The source can not be immediate data. The result is stored in the same place. E.g. 1. DEC AX 2. DEC 5000H 125

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AFTER EXECUTION BEFORE EXECUTION DEC AX AH 10 AL 10 AH 10 AL 09 5000H AFTER EXECUTION BEFORE EXECUTION DEC 5000H 1010 5000H 1009 126

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5 SUB destination source5 SUB destination source This instruction subtracts the contents of source operand from contents of destination. The source may be immediate data memory location or register. The destination may be memory location or register. The result is stored in the destination place. E.g. 1. SUB AX1000H 2. SUB AXBX This instruction subtracts the contents of source operand from contents of destination. The source may be immediate data memory location or register. The destination may be memory location or register. The result is stored in the destination place. E.g. 1. SUB AX1000H 2. SUB AXBX 127

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AFTER EXECUTION BEFORE EXECUTION SUB AX1000H AH 20 AL 00 AH 10 AL 00 2000 -1000 1000 AFTER EXECUTION BEFORE EXECUTION SUB AXBX 2000 -1000 1000 AH 20 AL 00 BH 10 BL 00 AH 10 AL 00 BH 10 BL 00 128

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6. SBB destination source6. SBB destination source Also known as Subtract with Borrow. This instruction subtracts the contents of source operand borrow from contents of destination operand. The source may be immediate data memory location or register. The destination may be memory location or register. The result is stored in the destination place. E.g. 1. SBB AX1000H 2. SBB AXBX Also known as Subtract with Borrow. This instruction subtracts the contents of source operand borrow from contents of destination operand. The source may be immediate data memory location or register. The destination may be memory location or register. The result is stored in the destination place. E.g. 1. SBB AX1000H 2. SBB AXBX 129

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AH 20 AL 20 AFTER EXECUTION BEFORE EXECUTION SBB AX1000H AH 10 AL 19 2020 - 1000 1020- 11019 B 1 AH 20 AL 20 BH 10 BL 10 AFTER EXECUTION BEFORE EXECUTION SBB AXBX 2050 2020 - 1000 1020- 11019 AH 10 AL 19 BH 10 BL 10 B 1 130

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7. CMP destination source7. CMP destination source Also known as Compare. This instruction compares the contents of source operand with the contents of destination operands. The source may be immediate data memory location or register. The destination may be memory location or register. Then resulting carry zero flag will be set or reset. E.g. 1. CMP AX1000H 2. CMP AXBX Also known as Compare. This instruction compares the contents of source operand with the contents of destination operands. The source may be immediate data memory location or register. The destination may be memory location or register. Then resulting carry zero flag will be set or reset. E.g. 1. CMP AX1000H 2. CMP AXBX 131

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AFTER EXECUTION CMP AXBX BEFORE EXECUTION CY 0 Z 1 AFTER EXECUTION BEFORE EXECUTION DS: CY0Z1 DS: CY0Z0 DS: CY1Z0 AH 10 AL 00 BH 10 BL 00 CMP AXBX CY 0 Z 0 AH 10 AL 00 CMP AXBX CY 0 Z 0 AH 10 AL 00 BH 00 BL 10 AFTER EXECUTION BEFORE EXECUTION CMP AXBX CY 1 Z 0 AH 10 AL 00 BH 20 BL 00 132

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AAA ASCII Adjust after Addition: The data entered from the terminal is in ASCII format. In ASCII 0 9 are represented by 30H 39H. This instruction allows us to add the ASCII codes. This instruction does not have any operand. Other ASCII Instructions: AASASCII Adjust after Subtraction AAMASCII Adjust after Multiplication AADASCII Adjust Before Division AAA ASCII Adjust after Addition: The data entered from the terminal is in ASCII format. In ASCII 0 9 are represented by 30H 39H. This instruction allows us to add the ASCII codes. This instruction does not have any operand. Other ASCII Instructions: AASASCII Adjust after Subtraction AAMASCII Adjust after Multiplication AADASCII Adjust Before Division 133

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DAA Decimal Adjust after Addition It is used to make sure that the result of adding two BCD numbers is adjusted to be a correct BCD number. It only works on AL register. DAS Decimal Adjust after Subtraction It is used to make sure that the result of subtracting two BCD numbers is adjusted to be a correct BCD number. It only works on AL register. DAA Decimal Adjust after Addition It is used to make sure that the result of adding two BCD numbers is adjusted to be a correct BCD number. It only works on AL register. DAS Decimal Adjust after Subtraction It is used to make sure that the result of subtracting two BCD numbers is adjusted to be a correct BCD number. It only works on AL register. 134

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MUL operand MUL operand Unsigned Multiplication. Operand contents are positively signed. Operand may be general purpose register or memory location. If operand is of 8-bit then multiply it with contents of AL. If operand is of 16-bit then multiply it with contents of AX. Result is stored in accumulator AX. E.g. 1. MUL BH // AX ALBH // +3 +4 +12. 2. MUL CX // AXAXCX Unsigned Multiplication. Operand contents are positively signed. Operand may be general purpose register or memory location. If operand is of 8-bit then multiply it with contents of AL. If operand is of 16-bit then multiply it with contents of AX. Result is stored in accumulator AX. E.g. 1. MUL BH // AX ALBH // +3 +4 +12. 2. MUL CX // AXAXCX 135

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IMUL operand IMUL operand Signed Multiplication. Operand contents are negatively signed. Operand may be general purpose register memory location or index register. If operand is of 8-bit then multiply it with contents of AL. If operand is of 16-bit then multiply it with contents of AX. Result is stored in accumulator AX. E.g. 1. IMUL BH // AX ALBH // -3 -4 12. 2. IMUL CX // AXAXCX Signed Multiplication. Operand contents are negatively signed. Operand may be general purpose register memory location or index register. If operand is of 8-bit then multiply it with contents of AL. If operand is of 16-bit then multiply it with contents of AX. Result is stored in accumulator AX. E.g. 1. IMUL BH // AX ALBH // -3 -4 12. 2. IMUL CX // AXAXCX 136

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DIV operand DIV operand Unsigned Division. Operand may be register or memory. Operand contents are positively signed. Operand may be general purpose register or memory location. ALAX/Operand 8-bit/16-bit AHRemainder. E.g. MOV AX 0203 // AX0203 MOV BL 04 // BL04 IDIV BL // AL0203/0450 i.e. AL50 AH03 Unsigned Division. Operand may be register or memory. Operand contents are positively signed. Operand may be general purpose register or memory location. ALAX/Operand 8-bit/16-bit AHRemainder. E.g. MOV AX 0203 // AX0203 MOV BL 04 // BL04 IDIV BL // AL0203/0450 i.e. AL50 AH03 137

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IDIV operand IDIV operand Signed Division. Operand may be register or memory. Operand contents are negatively signed. Operand may be general purpose register or memory location. ALAX/Operand 8-bit/16-bit AHRemainder. E.g. MOV AX -0203 // AX-0203 MOV BL 04 // BL04 DIV BL // AL-0203/04-50 i.e. AL-50 AH03 Signed Division. Operand may be register or memory. Operand contents are negatively signed. Operand may be general purpose register or memory location. ALAX/Operand 8-bit/16-bit AHRemainder. E.g. MOV AX -0203 // AX-0203 MOV BL 04 // BL04 DIV BL // AL-0203/04-50 i.e. AL-50 AH03 138

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Multiplication and Division Examples Multiplication and Division Examples 139

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LOGICAL or Bit Manipulation Instructions These instructions are used at the bit level. These instructions can be used for: T esting a zero bit Set or reset a bit Shift bits across registers These instructions are used at the bit level. These instructions can be used for: T esting a zero bit Set or reset a bit Shift bits across registers 143

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Bit Manipulation InstructionsLOGICAL Instructions • AND – Especially used in clearing certain bits masking xxxx xxxx AND 0000 1111 0000 xxxx clear the first four bits – Examples: AND BL 0FH • OR – Used in setting certain bits xxxx xxxx OR 0000 1111 xxxx 1111 Set the upper four bits • AND – Especially used in clearing certain bits masking xxxx xxxx AND 0000 1111 0000 xxxx clear the first four bits – Examples: AND BL 0FH • OR – Used in setting certain bits xxxx xxxx OR 0000 1111 xxxx 1111 Set the upper four bits 144

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XOR – Used in Inverting bits xxxx xxxx XOR 0000 1111 xxxxx’x’x’x’ -Example: Clear bits 0 and 1 set bits 6 and 7 invert bit 5 of register CL: AND CL FCH 1111 1100B OR CL C0H 1100 0000B XOR CL 20H 0010 0000B XOR – Used in Inverting bits xxxx xxxx XOR 0000 1111 xxxxx’x’x’x’ -Example: Clear bits 0 and 1 set bits 6 and 7 invert bit 5 of register CL: AND CL FCH 1111 1100B OR CL C0H 1100 0000B XOR CL 20H 0010 0000B 145

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SHL Instruction The SHL shift left instruction performs a logical left shift on the destination operand filling the lowest bit with 0. CF 0 CF 0 mov dl5d shl dl1 146

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SHR Instruction The SHR shift right instruction performs a logical right shift on the destination operand. The highest bit position is filled with a zero. C F 0 C F 0 MOV DL80d SHR DL1 DL 40 SHR DL2 DL 10 147

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SAR Instruction SAR shift arithmetic right performs a right arithmetic shift on the destination operand. CF CF An arithmetic shift preserves the numbers sign. MOV DL-80 SAR DL1 DL -40 SAR DL2 DL -10 148

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Shifting left n bits multiplies the operand by 2 n For example 5 2 2 20 Shifting right n bits divides the operand by 2 n For example 80 / 2 3 10 mov dl5 shl dl1 Shifting left n bits multiplies the operand by 2 n For example 5 2 2 20 Shifting right n bits divides the operand by 2 n For example 80 / 2 3 10 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 5 10 Before: After: 149

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ROL Instruction ROL rotate shifts each bit to the left The highest bit is copied into both the Carry flag and into the lowest bit No bits are lost CF CF MOV Al11110000b ROL Al1 AL 11100001b MOV Dl3Fh ROL Dl4 DL F3h 150

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ROR Instruction ROR rotate right shifts each bit to the right The lowest bit is copied into both the Carry flag and into the highest bit No bits are lost CF CF MOV AL11110000b ROR AL1 AL 01111000b MOV DL3Fh ROR DL4 DL F3h 151

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RCL Instruction RCL rotate carry left shifts each bit to the left Copies the Carry flag to the least significant bit Copies the most significant bit to the Carry flag CF CF CLC CF 0 MOV BL88H CFBL 0 10001000b RCL BL1 CFBL 1 00010000b RCL BL1 CFBL 0 00100001b 152

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RCR Instruction RCR rotate carry right shifts each bit to the right Copies the Carry flag to the most significant bit Copies the least significant bit to the Carry flag CF STC CF 1 MOV AH10H CFAH 00010000 1 RCR AH1 CFAH 10001000 0 CF 153

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Branching Instructionsor Program Execution Transfer Instructions These instructions cause change in the sequence of the execution of instruction. This change can be through a condition or sometimes unconditional. The conditions are represented by flags. These instructions cause change in the sequence of the execution of instruction. This change can be through a condition or sometimes unconditional. The conditions are represented by flags. 154

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CALL Des: This instruction is used to call a subroutine or function or procedure. The address of next instruction after CALL is saved onto stack. RET: It returns the control from procedure to calling program. Every CALL instruction should have a RET . CALL Des: This instruction is used to call a subroutine or function or procedure. The address of next instruction after CALL is saved onto stack. RET: It returns the control from procedure to calling program. Every CALL instruction should have a RET . 155

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SUBROUTINE SUBROUTINE HANDILING INSTRUCTIONS Call subroutine A Next instruction Main program Subroutine A First Instruction Call subroutine A Next instruction Return 156

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JMP Des: This instruction is used for unconditional jump from one place to another. Jxx Des Conditional Jump: All the conditional jumps follow some conditional statements or any instruction that affects the flag. JMP Des: This instruction is used for unconditional jump from one place to another. Jxx Des Conditional Jump: All the conditional jumps follow some conditional statements or any instruction that affects the flag. 157

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Conditional Jump Table Mnemonic Meaning JA Jump if Above JAE Jump if Above or Equal JB Jump if Below JBE Jump if Below or Equal JBE Jump if Below or Equal JC Jump if Carry JE Jump if Equal JNC Jump if Not Carry JNE Jump if Not Equal JNZ Jump if Not Zero JPE Jump if Parity Even JPO Jump if Parity Odd JZ Jump if Zero 158

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Loop Des: This is a looping instruction. The number of times looping is required is placed in the CX register. With each iteration the contents of CX are decremented. ZF is checked whether to loop again or not. Loop Des: This is a looping instruction. The number of times looping is required is placed in the CX register. With each iteration the contents of CX are decremented. ZF is checked whether to loop again or not. 159

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String Instructions String in assembly language is just a sequentially stored bytes or words. There are very strong set of string instructions in 8086. By using these string instructions the size of the program is considerably reduced. String in assembly language is just a sequentially stored bytes or words. There are very strong set of string instructions in 8086. By using these string instructions the size of the program is considerably reduced. 160

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CMPS Des Src: It compares the string bytes or words. SCAS String: It scans a string. It compares the String with byte in AL or with word in AX. CMPS Des Src: It compares the string bytes or words. SCAS String: It scans a string. It compares the String with byte in AL or with word in AX. 161

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MOVS / MOVSB / MOVSW: It causes moving of byte or word from one string to another. In this instruction the source string is in Data Segment and destination string is in Extra Segment. SI and DI store the offset values for source and destination index. MOVS / MOVSB / MOVSW: It causes moving of byte or word from one string to another. In this instruction the source string is in Data Segment and destination string is in Extra Segment. SI and DI store the offset values for source and destination index. 162

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REP Repeat: This is an instruction prefix. It causes the repetition of the instruction until CX becomes zero. E.g.: REP MOVSB STR1 STR2 It copies byte by byte contents. REP repeats the operation MOVSB until CX becomes zero. REP Repeat: This is an instruction prefix. It causes the repetition of the instruction until CX becomes zero. E.g.: REP MOVSB STR1 STR2 It copies byte by byte contents. REP repeats the operation MOVSB until CX becomes zero. 163

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Processor Control Instructions These instructions control the processor itself. 8086 allows to control certain control flags that: causes the processing in a certain direction processor synchronization if more than one microprocessor attached. These instructions control the processor itself. 8086 allows to control certain control flags that: causes the processing in a certain direction processor synchronization if more than one microprocessor attached. 164

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STC It sets the carry flag to 1. CLC It clears the carry flag to 0. CMC It complements the carry flag. STC It sets the carry flag to 1. CLC It clears the carry flag to 0. CMC It complements the carry flag. 165

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STD: It sets the direction flag to 1. If it is set string bytes are accessed from higher memory address to lower memory address. CLD: It clears the direction flag to 0. If it is reset the string bytes are accessed from lower memory address to higher memory address. STD: It sets the direction flag to 1. If it is set string bytes are accessed from higher memory address to lower memory address. CLD: It clears the direction flag to 0. If it is reset the string bytes are accessed from lower memory address to higher memory address. 166

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HLT instruction HALT processing The HLT instruction will cause the 8086 to stop fetching and executing instructions. NOP instruction this instruction simply takes up three clock cycles and does no processing. LOCK instruction this is a prefix to an instruction. This prefix makes sure that during execution of the instruction control of system bus is not taken by other microprocessor. W AIT instruction this instruction takes 8086 to an idle condition. The CPU will not do any processing during this. HLT instruction HALT processing The HLT instruction will cause the 8086 to stop fetching and executing instructions. NOP instruction this instruction simply takes up three clock cycles and does no processing. LOCK instruction this is a prefix to an instruction. This prefix makes sure that during execution of the instruction control of system bus is not taken by other microprocessor. W AIT instruction this instruction takes 8086 to an idle condition. The CPU will not do any processing during this. 167

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INSTRUCTION SET-summary 1.DATA TRANSFER INSTRUCTIONS Mnemonic Meaning Format Operation MOV Move Mov DS SD XCHG Exchange XCHG DS SD LEA Load Effective Address LEA Reg16EA EAReg16 PUSH pushes the operand into top of stack. PUSH BX PUSH pushes the operand into top of stack. PUSH BX POP pops the operand from top of stack to Des. POP BX IN transfers the operand from specified port to accumulator register. IN AX0028 OUT transfers the operand from accumulator to specified port. OUT 0028BX 168

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2. ARITHMETIC INSTRUCTIONS Mnemonic Meaning Format Operation SUB Subtract SUB DS D -SD BorrowCF SBB Subtract with borrow SBB DS D -S -CFD DEC Decrement by one DEC D D - 1D NEG Negate NEG D DAS Decimal adjust for subtraction DAS Convert the result in AL to packed decimal format DAS Decimal adjust for subtraction DAS Convert the result in AL to packed decimal format AAS ASCII adjust for subtraction AASAL difference AH dec by 1 if borrow ADD Addition ADD DS S+DD carryCF ADC Add with carry ADC DS S+D+CFD carryCF INC Increment by one INC D D+1D AAA ASCII adjust for addition AAA If the sum is 9 AH is incremented by 1 DAA Decimal adjust for addition DAA Adjust AL for decimal Packed BCD 169

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Mnemonic Meaning Format Operation AND OR XOR NOT Logical AND Logical Inclusive OR Logical Exclusive OR LOGICAL NOT AND DS OR DS XOR DS NOT D S · D →DS+D →DSD→DD →D + 3. Bit Manipulation InstructionsLogical Instructions AND OR XOR NOT Logical AND Logical Inclusive OR Logical Exclusive OR LOGICAL NOT AND DS OR DS XOR DS NOT D S · D →DS+D →DSD→DD →D 170 Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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Shift Rotate Instructions Mnemonic Meaning Format SAL/SHL SHR SAR Shift arithmetic Left/ Shift Logical left Shift logical right Shift arithmetic right SAL/SHL D Count SHR D Count SAR D Count Mnemonic Meaning Format ROL Rotate Left ROL DCount ROR Rotate Right ROR DCount RCL Rotate Left through Carry RCL DCount RCR Rotate right through Carry RCR DCount 171

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4. Branching or PROGRAM EXECUTION TRANSFER INSTRUCTIONS • CALL - call a subroutine • RET - returns the control from procedure to calling program • JMP Des Unconditional Jump • Jxx Des conditional Jump ex: JC 8000 • Loop Des • CALL - call a subroutine • RET - returns the control from procedure to calling program • JMP Des Unconditional Jump • Jxx Des conditional Jump ex: JC 8000 • Loop Des 172

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5. STRING INSTRUCTIONS • CMPS Des Src - compares the string bytes • SCAS String - scans a string • MOVS / MOVSB / MOVSW - moving of byte or word • REP Repeat - repetition of the instruction • CMPS Des Src - compares the string bytes • SCAS String - scans a string • MOVS / MOVSB / MOVSW - moving of byte or word • REP Repeat - repetition of the instruction 173

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6. PROCESSOR CONTROL INSTRUCTIONS • STC set the carry flag CF1 • CLC clear the carry flag CF0 • STD set the direction flag DF1 • CLD clear the direction flag DF0 • HLT stop fetching execution • NOP no operationno processing • LOCK - control of system bus is not taken by other µP • WAIT - CPU will not do any processing • ESC - µP does NOP or access a data from memory for coprocessor • STC set the carry flag CF1 • CLC clear the carry flag CF0 • STD set the direction flag DF1 • CLD clear the direction flag DF0 • HLT stop fetching execution • NOP no operationno processing • LOCK - control of system bus is not taken by other µP • WAIT - CPU will not do any processing • ESC - µP does NOP or access a data from memory for coprocessor 174

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Assembler Directives Assembler Directives 175

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Directives Expansion 176

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• ASSUME Directive - The ASSUME directive is used to tell the assembler that the name of the logical segment should be used for a specified segment. • DBdefine byte - DB directive is used to declare a byte type variable or to store a byte in memory location. • DWdefine word - The DW directive is used to define a variable of type word or to reserve storage location of type word in memory. • ASSUME Directive - The ASSUME directive is used to tell the assembler that the name of the logical segment should be used for a specified segment. • DBdefine byte - DB directive is used to declare a byte type variable or to store a byte in memory location. • DWdefine word - The DW directive is used to define a variable of type word or to reserve storage location of type word in memory. 177 Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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• DDdefine double word :This directive is used to declare a variable of type double word or restore memory locations which can be accessed as type double word. • DQ define quadword :This directive is used to tell the assembler to declare a variable 4 words in length or to reserve 4 words of storage in memory . • DT define ten bytes:It is used to inform the assembler to define a variable which is 10 bytes in length or to reserve 10 bytes of storage in memory. • DDdefine double word :This directive is used to declare a variable of type double word or restore memory locations which can be accessed as type double word. • DQ define quadword :This directive is used to tell the assembler to declare a variable 4 words in length or to reserve 4 words of storage in memory . • DT define ten bytes:It is used to inform the assembler to define a variable which is 10 bytes in length or to reserve 10 bytes of storage in memory. 178

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• END- End program .This directive indicates the assembler that this is the end of the program module. The assembler ignores any statements after an END directive. • ENDP- End procedure: It indicates the end of the procedure subroutine to the assembler. • ENDS-End Segment: This directive is used with the name of the segment to indicate the end of that logical segment. • EQU - This EQU directive is used to give a name to some value or to a symbol. • END- End program .This directive indicates the assembler that this is the end of the program module. The assembler ignores any statements after an END directive. • ENDP- End procedure: It indicates the end of the procedure subroutine to the assembler. • ENDS-End Segment: This directive is used with the name of the segment to indicate the end of that logical segment. • EQU - This EQU directive is used to give a name to some value or to a symbol. 179

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• PROC - The PROC directive is used to identify the start of a procedure. • PTR -This PTR operator is used to assign a specific type of a variable or to a label. • ORG -Originate : The ORG statement changes the starting offset address of the data. • PROC - The PROC directive is used to identify the start of a procedure. • PTR -This PTR operator is used to assign a specific type of a variable or to a label. • ORG -Originate : The ORG statement changes the starting offset address of the data. 180

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Directives examples • ASSUME CS:CODE cs code segment • ORG 3000 • NAME DB THOMAS • POINTER DD 12341234H • FACTOR EQU 03H • ASSUME CS:CODE cs code segment • ORG 3000 • NAME DB THOMAS • POINTER DD 12341234H • FACTOR EQU 03H 181

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Assembly Language ProgrammingALP 8086 Assembly Language ProgrammingALP 8086 182

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Program 1: Increment an 8-bit number • MOV AL 05H Move 8-bit data to AL. • INC AL Increment AL. Program 2: Increment an 16-bit number Program 2: Increment an 16-bit number • MOV AX 0005H Move 16-bit data to AX. • INC AX Increment AX. 183 Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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Program 3: Decrement an 8-bit number • MOV AL 05H Move 8-bit data to AL. • DEC AL Decrement AL. Program 4: Decrement an 16-bit number Program 4: Decrement an 16-bit number • MOV AX 0005H Move 16-bit data to AX. • DEC AX Decrement AX. 184

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Program 5: 1s complement of an 8 -bit number. • MOV AL 05H Move 8-bit data to AL. • NOT AL Complement AL. Program 6: 1s complement of a 16 -bit number. Program 6: 1s complement of a 16 -bit number. • MOV AX 0005H Move 16-bit data to AX. • NOT AX Complement AX. 185

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Program 7: 2s complement of an 8 -bit number. • MOV AL 05H Move 8-bit data to AL. • NOT AL Complement AL. • INC AL Increment AL Program 8: 2s complement of a 16 -bit number. Program 8: 2s complement of a 16 -bit number. • MOV AX 0005H Move 16-bit data to AX. • NOT AX Complement AX. • INC AX Increment AX 186

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Program 7: 2s complement of an 8 -bit number. • MOV AL 05H Move 8-bit data to AL. • NOT AL Complement AL. • INC AL Increment AL Program 8: 2s complement of a 16 -bit number. Program 8: 2s complement of a 16 -bit number. • MOV AX 0005H Move 16-bit data to AX. • NOT AX Complement AX. • INC AX Increment AX 187

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Program 9: Add two 8-bit numbers MOV AL 05H Move 1 st 8-bit number to AL. MOV BL 03H Move 2 nd 8-bit number to BL. ADD AL BL Add BL with AL. Program 10: Add two 16-bit numbers Program 10: Add two 16-bit numbers MOV AX 0005H Move 1 st 16-bit number to AX. MOV BX 0003H Move 2 nd 16-bit number to BX. ADD AX BX Add BX with AX. 188

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Program 11: subtract two 8-bit numbers MOV AL 05H Move 1 st 8-bit number to AL. MOV BL 03H Move 2 nd 8-bit number to BL. SUB AL BL subtract BL from AL. Program 12: subtract two 16-bit numbers Program 12: subtract two 16-bit numbers MOV AX 0005H Move 1 st 16-bit number to AX. MOV BX 0003H Move 2 nd 16-bit number to BX. SUB AX BX subtract BX from AX. 189

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Program 13: Multiply two 8-bit unsigned numbers. MOV AL 04H Move 1 st 8-bit number to AL. MOV BL 02H Move 2 nd 8-bit number to BL. MUL BL Multiply BL with AL and the result will be in AX. Program 14: Multiply two 8-bit signed numbers. Program 14: Multiply two 8-bit signed numbers. MOV AL 04H Move 1 st 8-bit number to AL. MOV BL 02H Move 2 nd 8-bit number to BL. IMUL BL Multiply BL with AL and the result will be in AX. 190

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Program 15: Multiply two 16-bit unsigned numbers. MOV AX 0004H Move 1 st 16-bit number to AL. MOV BX 0002H Move 2 nd 16-bit number to BL. MUL BX Multiply BX with AX and the result will be in DX:AX 420008 08 AX 00 DX Program 16: Divide two 16-bit unsigned numbers. Program 16: Divide two 16-bit unsigned numbers. MOV AX 0004H Move 1 st 16-bit number to AL. MOV BX 0002H Move 2 nd 16-bit number to BL. DIV BX Divide BX from AX and the result will be in AX DX 4/20002 02 AX 00DX ie: Quotient AX Reminder DX 191 Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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Detailed coding 16 BIT ADDITION 192

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Detailed coding 16 BIT SUBTRACTION 193

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16 BIT MULTIPLICATION 194

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16 BIT DIVISION 195

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SUM of N numbers MOV AX0000 MOV SI1100 MOV DI1200 MOV CX0005 5 NUMBERS TO BE TAKEN SUM MOV DX0000 L1: ADD AXSI INC SI INC DX CMP CXDX JNZ L1 MOV 1200AX HLT MOV AX0000 MOV SI1100 MOV DI1200 MOV CX0005 5 NUMBERS TO BE TAKEN SUM MOV DX0000 L1: ADD AXSI INC SI INC DX CMP CXDX JNZ L1 MOV 1200AX HLT 196

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Average of N numbers MOV AX0000 MOV SI1100 MOV DI1200 MOV CX0005 5 NUMBERS TO BE TAKEN AVERAGE MOV DX0000 L1: ADD AXSI INC SI INC DX CMP CXDX JNZ L1 DIV CX AXAX/5AVERAGE OF 5 NUMBERS MOV 1200AX HLT MOV AX0000 MOV SI1100 MOV DI1200 MOV CX0005 5 NUMBERS TO BE TAKEN AVERAGE MOV DX0000 L1: ADD AXSI INC SI INC DX CMP CXDX JNZ L1 DIV CX AXAX/5AVERAGE OF 5 NUMBERS MOV 1200AX HLT 197 Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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FACTORIAL of N MOV CX0005 5 Factorial54321120 MOV DX0000 MOV AX0001 L1: MUL CX DEC DX CMP CXDX JNZ L1 MOV 1200AX HLT MOV CX0005 5 Factorial54321120 MOV DX0000 MOV AX0001 L1: MUL CX DEC DX CMP CXDX JNZ L1 MOV 1200AX HLT 198

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ASCENDING ORDER 199

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DECENDING ORDER Note: change the coding JNB L1 into JB L1 in the LINE 10 201

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LARGEST smallest NUMBER IN AN ARRAY 202

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LARGEST NUMBER 203

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SMALLEST NUMBER 204

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Modular Programming Modular Programming 205

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• Generally industry-programming projects consist of thousands of lines of instructions or operation code. • The size of the modules are reduced to a humanly comprehensible and manageable level. • Program is composed from several smaller modules. Modules could be developed by separate teams concurrently.OBJ modules Object modules. • The .OBJ modules so produced are combined using a LINK program. • Modular programming techniques simplify the software development process • Generally industry-programming projects consist of thousands of lines of instructions or operation code. • The size of the modules are reduced to a humanly comprehensible and manageable level. • Program is composed from several smaller modules. Modules could be developed by separate teams concurrently.OBJ modules Object modules. • The .OBJ modules so produced are combined using a LINK program. • Modular programming techniques simplify the software development process 206

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CHARACTERISTICS of module: 1. Each module is independent of other modules. 2. Each module has one input and one output. 3. A module is small in size. 4. Programming a single function per module is a goal Advantages of Modular Programming: • It is easy to write test and debug a module. • Code can be reused. • The programmer can divide tasks. • Re-usable Modules can be re-used within a program DRAWBACKS: Modular programming requires extra time and memory CHARACTERISTICS of module: 1. Each module is independent of other modules. 2. Each module has one input and one output. 3. A module is small in size. 4. Programming a single function per module is a goal Advantages of Modular Programming: • It is easy to write test and debug a module. • Code can be reused. • The programmer can divide tasks. • Re-usable Modules can be re-used within a program DRAWBACKS: Modular programming requires extra time and memory 207

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MODULAR PROGRAMMING: 1.LINKING RELOCATION 2.STACKS 3.Procedures 4.Interrupts Interrupt Routines 5.Macros MODULAR PROGRAMMING: 1.LINKING RELOCATION 2.STACKS 3.Procedures 4.Interrupts Interrupt Routines 5.Macros 208

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LINKING RELOCATION LINKING RELOCATION 209

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LINKER • A linker is a program used to join together several object files into one large object file. • The linker produces a link file which contains the binary codes for all the combined modules. The linker program is invoked using the following options. C LINK or CLINK MS.OBJ • A linker is a program used to join together several object files into one large object file. • The linker produces a link file which contains the binary codes for all the combined modules. The linker program is invoked using the following options. C LINK or CLINK MS.OBJ 210

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• The loader is a part of the operating system and places codes into the memory after reading the .exe file • A program called locator reallocates the linked file and creates a file for permanent location of codes in a standard format. 211

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Creation and execution of a program 212

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Loader -Loader is a utility program which takes object code as input prepares it for execution and loads the executable code into the memory . -Loader is actually responsible for initializing the process of execution. Functions of loaders: 1.It allocates the space for program in the memoryAllocation 2.It resolves the code between the object modulesLinking 3. some address dependent locations in the program address constants must be adjusted according to allocated spaceRelocation 4. It also places all the machine instructions and data of corresponding programs and subroutines into the memory .Loading Loader -Loader is a utility program which takes object code as input prepares it for execution and loads the executable code into the memory . -Loader is actually responsible for initializing the process of execution. Functions of loaders: 1.It allocates the space for program in the memoryAllocation 2.It resolves the code between the object modulesLinking 3. some address dependent locations in the program address constants must be adjusted according to allocated spaceRelocation 4. It also places all the machine instructions and data of corresponding programs and subroutines into the memory .Loading 213

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Relocating loader BSS Loader • When a single subroutine is changed then all the subroutine needs to be reassembled. • The binary symbolic subroutine BSS loader used in IBM 7094 machine is relocating loader. • In BSS loader there are many procedure segments • The assembler reads one sourced program and assembles each procedure segment independently • When a single subroutine is changed then all the subroutine needs to be reassembled. • The binary symbolic subroutine BSS loader used in IBM 7094 machine is relocating loader. • In BSS loader there are many procedure segments • The assembler reads one sourced program and assembles each procedure segment independently 214

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• The output of the relocating loader is the object program • The assembler takes the source program as input this source program may call some external routines. SEGMENT COMBINATION: ASM-86 assembler regulating the way segments with the same name are concatenated sometimes they are overlaid. Form of segment directive: Segment name SEGEMENT Combine-type Possible combine-type are: • PUBLIC • COMMON • STACK • AT • MEMORY • The output of the relocating loader is the object program • The assembler takes the source program as input this source program may call some external routines. SEGMENT COMBINATION: ASM-86 assembler regulating the way segments with the same name are concatenated sometimes they are overlaid. Form of segment directive: Segment name SEGEMENT Combine-type Possible combine-type are: • PUBLIC • COMMON • STACK • AT • MEMORY 215

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Procedures Procedures 216

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• Procedure is a part of code that can be called from your program in order to make some specific task. Procedures make program more structural and easier to understand. • syntax for procedure declaration: name PROC . here goes the code . of the procedure ... RET name ENDP here PROC is the procedure name.used in top bottom RET - used to return from OS. CALL-call a procedure PROC ENDP complier directives CALL RET - instructions • Procedure is a part of code that can be called from your program in order to make some specific task. Procedures make program more structural and easier to understand. • syntax for procedure declaration: name PROC . here goes the code . of the procedure ... RET name ENDP here PROC is the procedure name.used in top bottom RET - used to return from OS. CALL-call a procedure PROC ENDP complier directives CALL RET - instructions 217

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EXAMPLE 1 call a procedure ORG 100h CALL m1 MOV AX 2 RET return to operating system. m1 PROC MOV BX 5 RET return to caller. m1 ENDP END • The above example calls procedure m1 does MOV BX 5 returns to the next instruction after CALL: MOV AX 2. ORG 100h CALL m1 MOV AX 2 RET return to operating system. m1 PROC MOV BX 5 RET return to caller. m1 ENDP END • The above example calls procedure m1 does MOV BX 5 returns to the next instruction after CALL: MOV AX 2. 218 Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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Example 2 : several ways to pass parameters to procedure ORG 100h MOV AL 1 MOV BL 2 CALL m2 CALL m2 CALL m2 CALL m2 RET return to operating system. m2 PROC MUL BL AX AL BL. RET return to caller. m2 ENDP END ORG 100h MOV AL 1 MOV BL 2 CALL m2 CALL m2 CALL m2 CALL m2 RET return to operating system. m2 PROC MUL BL AX AL BL. RET return to caller. m2 ENDP END value of AL register is update every time the procedure is called. final result in AX register is 16 or 10h 219

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• Stack is an area of memory for keeping temporary data. • STACK is used by CALL RET instructions. PUSH -stores 16 bit value in the stack. POP -gets 16 bit value from the stack. • PUSH and POP instruction are especially useful because we dont have too much registers to operate 1. Store original value of the register in stack using PUSH. 2. Use the register for any purpose. 3. Restore the original value of the register from stack using POP. • Stack is an area of memory for keeping temporary data. • STACK is used by CALL RET instructions. PUSH -stores 16 bit value in the stack. POP -gets 16 bit value from the stack. • PUSH and POP instruction are especially useful because we dont have too much registers to operate 1. Store original value of the register in stack using PUSH. 2. Use the register for any purpose. 3. Restore the original value of the register from stack using POP. 221

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Example-1 store value in STACK using PUSH POP ORG 100h MOV AX 1234h PUSH AX store value of AX in stack. MOV AX 5678h modify the AX value. POP AX restore the original value of AX. RET END ORG 100h MOV AX 1234h PUSH AX store value of AX in stack. MOV AX 5678h modify the AX value. POP AX restore the original value of AX. RET END 222

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Example 2: use of the stack is for exchanging the values ORG 100h MOV AX 1212h store 1212h in AX. MOV BX 3434h store 3434h in BX PUSH AX store value of AX in stack. PUSH BX store value of BX in stack. POP AX set AX to original value of BX. POP BX set BX to original value of AX. RET END ORG 100h MOV AX 1212h store 1212h in AX. MOV BX 3434h store 3434h in BX PUSH AX store value of AX in stack. PUSH BX store value of BX in stack. POP AX set AX to original value of BX. POP BX set BX to original value of AX. RET END push 1212h and then 3434h on pop we will first get 3434h and only after it 1212h 223

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MACROS MACROS 224

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• Macros are just like procedures but not really. • Macros exist only until your code is compiled • After compilation all macros are replaced with real instructions • several macros to make coding easierReduce large complex programs ExampleMacro definition name MACRO parameters... instructions ENDM • Macros are just like procedures but not really. • Macros exist only until your code is compiled • After compilation all macros are replaced with real instructions • several macros to make coding easierReduce large complex programs ExampleMacro definition name MACRO parameters... instructions ENDM 225

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Example1 : Macro Definitions SAVE MACRO definition of MACRO name SAVE PUSH AX PUSH BX PUSH CX ENDM RETREIVE MACRO Another definition of MACRO name RETREIVE POP CX POP BX POP AX ENDM SAVE MACRO definition of MACRO name SAVE PUSH AX PUSH BX PUSH CX ENDM RETREIVE MACRO Another definition of MACRO name RETREIVE POP CX POP BX POP AX ENDM 226

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MACROS with Parameters Example: COPY MACRO x y macro named COPY with 2 parametersx y PUSH AX MOV AX x MOV y AX POP AX ENDM Example: COPY MACRO x y macro named COPY with 2 parametersx y PUSH AX MOV AX x MOV y AX POP AX ENDM 228

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INTERRUPTS INTERRUPT SERVICE ROUTINEISR INTERRUPTS INTERRUPT SERVICE ROUTINEISR 229

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INTERRUPT ISR • Interrupts is to break the sequence of operation. • While the CPU is executing a program on interrupt breaks the normal sequence of execution of instructions diverts its execution to some other program called Interrupt Service Routine ISR • Interrupts is to break the sequence of operation. • While the CPU is executing a program on interrupt breaks the normal sequence of execution of instructions diverts its execution to some other program called Interrupt Service Routine ISR 230

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• Maskable Interrupt: An Interrupt that can be disabled or ignored by the instructions of CPU are called as Maskable Interrupt. • Non- Maskable Interrupt: An interrupt that cannot be disabled or ignored by the instructions of CPU are called as Non- Maskable Interrupt. • Software interrupts are machine instructions that amount to a call to the designated interrupt subroutine usually identified by interrupt number. Ex: INT0 - INT255 • Maskable Interrupt: An Interrupt that can be disabled or ignored by the instructions of CPU are called as Maskable Interrupt. • Non- Maskable Interrupt: An interrupt that cannot be disabled or ignored by the instructions of CPU are called as Non- Maskable Interrupt. • Software interrupts are machine instructions that amount to a call to the designated interrupt subroutine usually identified by interrupt number. Ex: INT0 - INT255 234

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INTERRUPT VECTOR TABLE 256 INTERRUPTS OF 8086 ARE DIVIDED IN TO 3 GROUPS 1. TYPE 0 TO TYPE 4 INTERRUPTS- These Are Used For Fixed Operations And Hence Are Called Dedicated Interrupts 2. TYPE 5 TO TYPE 31 INTERRUPTS Not Used By 8086reserved For Higher Processors Like 80286 80386 Etc 3. TYPE 32 TO 255 INTERRUPTS Available For User called User Defined Interrupts These Can Be H/W Interrupts And Activated Through Intr Line Or Can Be S/W Interrupts. 1. TYPE 0 TO TYPE 4 INTERRUPTS- These Are Used For Fixed Operations And Hence Are Called Dedicated Interrupts 2. TYPE 5 TO TYPE 31 INTERRUPTS Not Used By 8086reserved For Higher Processors Like 80286 80386 Etc 3. TYPE 32 TO 255 INTERRUPTS Available For User called User Defined Interrupts These Can Be H/W Interrupts And Activated Through Intr Line Or Can Be S/W Interrupts. 240

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Type– 0 Divide Error Interrupt Quotient is too large cant be fit in AL/AX or Divide By Zero AX/0∞ Type–1 Single Step Interrupt used for executing the program in single step mode by setting Trap Flag To Set Trap Flag PUSHF MOV BPSP OR BP+00100HSET BIT8 POPF Type– 2 Non Maskable Interrupt This Interrupt is used for executing ISR of NMI Pin Positive Egde Signal. NMI cant be masked by S/W Type– 3 Break Point Interrupt used for providing BREAK POINTS in the program Type– 4 Over Flow Interrupt used to handle any Overflow Error after signed arithmetic Type– 0 Divide Error Interrupt Quotient is too large cant be fit in AL/AX or Divide By Zero AX/0∞ Type–1 Single Step Interrupt used for executing the program in single step mode by setting Trap Flag To Set Trap Flag PUSHF MOV BPSP OR BP+00100HSET BIT8 POPF Type– 2 Non Maskable Interrupt This Interrupt is used for executing ISR of NMI Pin Positive Egde Signal. NMI cant be masked by S/W Type– 3 Break Point Interrupt used for providing BREAK POINTS in the program Type– 4 Over Flow Interrupt used to handle any Overflow Error after signed arithmetic 241

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PRIORITY OF INTERRUPTS Interrupt Type Priority INT0 INT3-INT 255 Highest NMIINT2 NMIINT2 INTR SINGLE STEP Lowest 242

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Byte String Manipulation Byte String Manipulation 243

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Move compare store load scan Refer String Instructions in Instruction Set Slide No: 160-163 244

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Byte Manipulation Example 1: MOV AX1000 MOV BX1002 AND AXBX MOV 2000AX HLT Example 2: MOV AX1000 MOV BX1002 OR AXBX MOV 2000AX HLT Example 3: MOV AX1000 MOV BX1002 XOR AXBX MOV 2000AX HLT Example 4: MOV AX1000 NOT AX MOV 2000AX HLT Example 1: MOV AX1000 MOV BX1002 AND AXBX MOV 2000AX HLT Example 2: MOV AX1000 MOV BX1002 OR AXBX MOV 2000AX HLT Example 3: MOV AX1000 MOV BX1002 XOR AXBX MOV 2000AX HLT Example 4: MOV AX1000 NOT AX MOV 2000AX HLT 245 Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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STRING MANIPULATION 1. Copying a string MOV SB MOV CX0003 copy 3 memory locations MOV SI1000 MOV DI2000 L1 CLD MOV SB DEC CX decrement CX JNZ L1 HLT MOV CX0003 copy 3 memory locations MOV SI1000 MOV DI2000 L1 CLD MOV SB DEC CX decrement CX JNZ L1 HLT 246

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2. Find Replace 247

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UNIT-2 8086 SYSTEM BUS STRUCTURE DEPARTMENTS: CSEITECEECEMECH Regulation : 2013 UNIT-2 8086 SYSTEM BUS STRUCTURE 248

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8086 signals or Pin Diagram Refer UNIT-1 Slide No: 43-54 Refer UNIT-1 Slide No: 43-54 249

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GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND Vcc AD15 A16/S3 A17/S4 A18/S5 A19/S6 ___ BHE/S7HIGH ___ MN/MX ___ RD ___ ____ HOLDRQ/GT0 ___ ____ HLDARQ/GT1 ___ ______ WRLOCK __ __ IO/MS2 __ __ DT/RS1 ____ __ DENS0 ALEQS0 _____ INTAQS1 _____ TEST READY RESET 1 40 INTEL 8086 20 21 Minmode operation signals MN/MX1 Maxmode operation signals MN/MX0 Time-multiplexed Address / Data Bus bidirectional 0V“0” reference for all voltages 5V±10 Time- multiplexed Address Bus /Status signals outputs Operation Mode input: 1 minmode 8088 generates all the needed control signals for a small system 0 maxmode 8288 Bus Controller expands the status signals to generate more control signals Control Bus inout GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND Vcc AD15 A16/S3 A17/S4 A18/S5 A19/S6 ___ BHE/S7HIGH ___ MN/MX ___ RD ___ ____ HOLDRQ/GT0 ___ ____ HLDARQ/GT1 ___ ______ WRLOCK __ __ IO/MS2 __ __ DT/RS1 ____ __ DENS0 ALEQS0 _____ INTAQS1 _____ TEST READY RESET 1 40 INTEL 8086 20 21 Time-multiplexed Address / Data Bus bidirectional Hardware interrupt requests inputs 2...5MHz 1/3 duty cycle input Status signals outputs Operation Mode input: 1 minmode 8088 generates all the needed control signals for a small system 0 maxmode 8288 Bus Controller expands the status signals to generate more control signals Interrupt acknowledge output Control Bus inout 250

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MINIMUM MODE SIGNALS 251

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MAXIMUM MODE SIGNALS 252

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SYSTEM BUS TIMING SYSTEM BUS TIMING 253

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System Timing Diagrams T-State: One clock period is referred to as a T-State T-State An operation takes an integer number of T-States An operation takes an integer number of T-States CPU Bus Cycle: A bus cycle consists of 4 or more T-States T1 T2 T3 T4 254

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Memory Read Timing Diagrams • Dump address on address bus. • Issue a read RD and set M/ IO to 1. • Wait for memory access cycle. 255

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• Dump address on address bus. • Dump data on data bus. • Issue a write WR and set M/ IO to 1. Memory Write Timing Diagrams 256

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Bus Timing During T 1 : • The address is placed on the Address/Data bus. • Control signals M/ IO ALE and DT/ R specify memory or I/O latch the address onto the address bus and set the direction of data transfer on data bus. During T 2 : • 8086 issues the RD or WR signal DEN and for a write the data. • DEN enables the memory or I/O device to receive the data for writes and the 8086 to receive the data for reads. During T 3 : • This cycle is provided to allow memory to access data. • READY is sampled at the end of T 2 . • If low T 3 becomes a wait state. • Otherwise the data bus is sampled at the end of T 3 . During T 4 : • All bus signals are deactivated in preparation for next bus cycle. • Data is sampled for reads writes occur for writes. During T 1 : • The address is placed on the Address/Data bus. • Control signals M/ IO ALE and DT/ R specify memory or I/O latch the address onto the address bus and set the direction of data transfer on data bus. During T 2 : • 8086 issues the RD or WR signal DEN and for a write the data. • DEN enables the memory or I/O device to receive the data for writes and the 8086 to receive the data for reads. During T 3 : • This cycle is provided to allow memory to access data. • READY is sampled at the end of T 2 . • If low T 3 becomes a wait state. • Otherwise the data bus is sampled at the end of T 3 . During T 4 : • All bus signals are deactivated in preparation for next bus cycle. • Data is sampled for reads writes occur for writes. 257

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Setup Hold Time Setup time The time before the rising edge of the clock while the data must be valid and constant Hold time The time after the rising edge of the clock during which the data must remain valid and constant 258

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WAIT State • A wait stateT w is an extra clocking period inserted between T2 and T3 to lengthen the bus cycle allowing slower memory and I/O components to respond. • The READY input is sampled at the end of T2 and again if necessary in the middle of Tw. If READY is 0 then a Tw is inserted. • A wait stateT w is an extra clocking period inserted between T2 and T3 to lengthen the bus cycle allowing slower memory and I/O components to respond. • The READY input is sampled at the end of T2 and again if necessary in the middle of Tw. If READY is 0 then a Tw is inserted. 259

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Basic configurations Basic configurations 260

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BASIC CONFIGURATIONS- 1.Minimum Mode 2.Maximum Mode – Minimum modeMN/MXVcc • Pin 33 MN/MX connect to +5V • Pin 24-31 are used as memory and I/O control signal • The control signals are generated internally by the 8086/88 • More cost-efficient – Maximum modeMN/MXGND • Pin 33 MN/MX connect to Ground • Some control signals are generated externally by the 8288 bus controller chip • Max mode is used when math processor is used. – Minimum modeMN/MXVcc • Pin 33 MN/MX connect to +5V • Pin 24-31 are used as memory and I/O control signal • The control signals are generated internally by the 8086/88 • More cost-efficient – Maximum modeMN/MXGND • Pin 33 MN/MX connect to Ground • Some control signals are generated externally by the 8288 bus controller chip • Max mode is used when math processor is used. 261

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Minimum Mode 8086 System • 8086 is operated in minimum mode by MN/MX pin to logic 1 Vcc. • In this mode all the control signals are given out by the microprocessor chip itself. • 8086 is operated in minimum mode by MN/MX pin to logic 1 Vcc. • In this mode all the control signals are given out by the microprocessor chip itself. 262

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263

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Explain Minimum mode Signals also: Refer Slide No 47-54 264

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265

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266

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MAXIMUM MODE 267

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8288 BUS CONTROLLER Explain Maximum mode Signals also: Refer Slide No 47-54 268

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269

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270

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MULTIPROCESSOR CONFIGURATIONS MULTIPROCESSOR CONFIGURATIONS 271

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Multiprocessor configuration Coprocessor 8087 Multiprocessor configuration 272

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Multiprocessor configuration • Multiprocessor Systems refer to the use of multiple processors that executes instructions simultaneously and communicate with each other using mail boxes and Semaphores. • Maximum mode of 8086 is designed to implement 3 basic multiprocessor configurations: 1. Coprocessor8087 2. Closely coupled8089 3. Loosely coupledMultibus • Multiprocessor Systems refer to the use of multiple processors that executes instructions simultaneously and communicate with each other using mail boxes and Semaphores. • Maximum mode of 8086 is designed to implement 3 basic multiprocessor configurations: 1. Coprocessor8087 2. Closely coupled8089 3. Loosely coupledMultibus 273

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• Coprocessors and Closely coupled configurations are similar in that both the 8086 and the external processor shares the: - Memory - I/O system - Bus bus control logic - Clock generator • Coprocessors and Closely coupled configurations are similar in that both the 8086 and the external processor shares the: - Memory - I/O system - Bus bus control logic - Clock generator 274

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Co-processor – Intel 8087 8087 instructions are inserted in the 8086 program 8086 and 8087 reads instruction bytes and puts them in the respective queues NOP 8087 instructions have 11011 as the MSB of their first code byte 275

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Coprocessor / Closely Coupled Configuration 276

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TEST pin of 8086 • Used in conjunction with the WAIT instruction in multiprocessing environments. • This is input from the 8087 coprocessor. • During execution of a wait instruction the CPU checks this signal. • If it is low execution of the signal will continue if not it will stop executing. • Used in conjunction with the WAIT instruction in multiprocessing environments. • This is input from the 8087 coprocessor. • During execution of a wait instruction the CPU checks this signal. • If it is low execution of the signal will continue if not it will stop executing. 277

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1.Coprocessor Execution Example Coprocessor cannot take control of the bus it does everything through the CPU 278

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2.Closely Coupled Execution Example • Closely Coupled processor may take control of the bus independently. • Two 8086s cannot be closely coupled. • Closely Coupled processor may take control of the bus independently. • Two 8086s cannot be closely coupled. 279

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3.Loosely Coupled Configuration • has shared system bus system memory and system I/O. • each processor has its own clock as well as its own memoryin addition to access to the system resources. • Used for medium to large multiprocessor systems. • Each module is capable of being the bus master. • Any module could be a processor capable of being a bus master a coprocessor configuration or a closely coupled configuration. • has shared system bus system memory and system I/O. • each processor has its own clock as well as its own memoryin addition to access to the system resources. • Used for medium to large multiprocessor systems. • Each module is capable of being the bus master. • Any module could be a processor capable of being a bus master a coprocessor configuration or a closely coupled configuration. 280

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281

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Loosely Coupled Configuration • No direct connections between the modules. • Each share the system bus and communicate through shared resources. • Processor in their separate modules can simultaneously access their private subsystems through their local busses and perform their local data references and instruction fetches independently. This results in improved degree of concurrent processing. • Excellent for real time applications as separate modules can be assigned specialized tasks • No direct connections between the modules. • Each share the system bus and communicate through shared resources. • Processor in their separate modules can simultaneously access their private subsystems through their local busses and perform their local data references and instruction fetches independently. This results in improved degree of concurrent processing. • Excellent for real time applications as separate modules can be assigned specialized tasks 282

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Advantages of Multiprocessor Configuration 1. High system throughput can be achieved by having more than one CPU. 2. The system can be expanded in modular form. Each bus master module is an independent unit and normally resides on a separate PC board. One can be added or removed without affecting the others in the system. 3. A failure in one module normally does not affect the breakdown of the entire system and the faulty module can be easily detected and replaced 4. Each bus master has its own local bus to access dedicated memory or IO devices. So a greater degree of parallel processing can be achieved. 1. High system throughput can be achieved by having more than one CPU. 2. The system can be expanded in modular form. Each bus master module is an independent unit and normally resides on a separate PC board. One can be added or removed without affecting the others in the system. 3. A failure in one module normally does not affect the breakdown of the entire system and the faulty module can be easily detected and replaced 4. Each bus master has its own local bus to access dedicated memory or IO devices. So a greater degree of parallel processing can be achieved. 283

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INTRODUCTION TO ADVANCED PROCESSORS INTRODUCTION TO ADVANCED PROCESSORS 284

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Intel family of microprocessor bus and memory sizes Microproces sor Data bus width Address bus width Memory size 80186 16 20 1M 80286 16 24 16M 80286 16 24 16M 80386 DX 32 32 4G 80486 32 32 4G Pentium 4 core 2 64 40 1T 285 Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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80186 286

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80286 287

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80386 288

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TEXT BOOK References Main Book: 1. Microprocessors and Interfacing Programming and Hardware by Doughlas V.Hall Other Authors: 2. Microcomputer Systems: The 8086 / 8088 Family -Architecture Programming and Design by Yu-Cheng Liu Glenn A.Gibson 3. INTEL Microprocessors 8086/8088 80186/80188 80286 80386 80486 Pentium Prentium ProProcessor Pentium II III 4 by Barry B. Bery 4. Advanced microprocessor and peripherals by A K RAY 5. 8085 Microprocessor - Ramesh GaonkarMP history Basics LOCAL AUTHOR: 6.8086 Microprocessor by Nagoor Kani Main Book: 1. Microprocessors and Interfacing Programming and Hardware by Doughlas V.Hall Other Authors: 2. Microcomputer Systems: The 8086 / 8088 Family -Architecture Programming and Design by Yu-Cheng Liu Glenn A.Gibson 3. INTEL Microprocessors 8086/8088 80186/80188 80286 80386 80486 Pentium Prentium ProProcessor Pentium II III 4 by Barry B. Bery 4. Advanced microprocessor and peripherals by A K RAY 5. 8085 Microprocessor - Ramesh GaonkarMP history Basics LOCAL AUTHOR: 6.8086 Microprocessor by Nagoor Kani 289

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Documents References • 8086 SYSTEM BUS STRUCTURE by Prof.L.PETER STANLEY BEBINGTON PROFESSOR AND DEANACADEMICVCETErode • I/O Interfacing by Prof.P.JAYACHANDAR ASSOCIATE PROFESSOR and DEANSAVCETErode • 8086 Microprocessor by Dr. M. Gopikrishna Assistant Professor of PhysicsMaharajas College Ernakulam • 8086 architecture By Er. Swapnil Kaware • 8086 presentations by Gursharan Singh TatlaEazynotes.com • Microprocessor - Ramesh Gaonkar • 8086 micro processor prasadpawaskar • 8086 class notes-Y .N.M by MURTHY Y .N • Introduction to 8086 Microprocessor by Rajvir Singh • 8086 micro processor by Poojith Chowdhary • 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar Cutajar • Intel microprocessor history by Ramzi_Alqrainy • 8086 SYSTEM BUS STRUCTURE by Prof.L.PETER STANLEY BEBINGTON PROFESSOR AND DEANACADEMICVCETErode • I/O Interfacing by Prof.P.JAYACHANDAR ASSOCIATE PROFESSOR and DEANSAVCETErode • 8086 Microprocessor by Dr. M. Gopikrishna Assistant Professor of PhysicsMaharajas College Ernakulam • 8086 architecture By Er. Swapnil Kaware • 8086 presentations by Gursharan Singh TatlaEazynotes.com • Microprocessor - Ramesh Gaonkar • 8086 micro processor prasadpawaskar • 8086 class notes-Y .N.M by MURTHY Y .N • Introduction to 8086 Microprocessor by Rajvir Singh • 8086 micro processor by Poojith Chowdhary • 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar Cutajar • Intel microprocessor history by Ramzi_Alqrainy 290

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Website References • http://80864beginner.com/ • www.eazynotes.com • www.slideshare.net • www.scribd.com • www.docstoc.com • www.slideworld.com • www.nptel.ac.in • http://opencourses.emu.edu.tr/ • http://engineeringppt.blogspot.in/ • http://www.pptsearchengine.net/ • www.4shared.com • http://8085projects.info/ • http://80864beginner.com/ • www.eazynotes.com • www.slideshare.net • www.scribd.com • www.docstoc.com • www.slideworld.com • www.nptel.ac.in • http://opencourses.emu.edu.tr/ • http://engineeringppt.blogspot.in/ • http://www.pptsearchengine.net/ • www.4shared.com • http://8085projects.info/ 291

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NPTEL Lecture Materials References • Microprocessor and Peripheral Devices by Dr. Pramod Agarwal IIT Roorkee Link: http://nptel.ac.in/courses/108107029/ • Microprocessors and Microcontrollers by Prof. Krishna Kumar IISc Bangalore link: http://nptel.ac.in/courses/106108100/ • Microprocessor and Peripheral Devices by Dr. Pramod Agarwal IIT Roorkee Link: http://nptel.ac.in/courses/108107029/ • Microprocessors and Microcontrollers by Prof. Krishna Kumar IISc Bangalore link: http://nptel.ac.in/courses/106108100/ 292

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UNIT UNIT- -3 3 I/O I/O INTERFACING INTERFACING EC6504 Microprocessors and Microcontrollers Dept: CSEITECEMECH Regulation : 2013 293 UNIT UNIT- -3 3 I/O I/O INTERFACING INTERFACING Presented by C.GOKULAP/EEE

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Data Transfers Data Transfers Synchronous ----- Usually occur when peripherals are located within the same computer as the CPU. Close proximity allows all state bits change at same time on a common clock. Asynchronous ----- Do not require that the source and destination use the same system clock. 294 Synchronous ----- Usually occur when peripherals are located within the same computer as the CPU. Close proximity allows all state bits change at same time on a common clock. Asynchronous ----- Do not require that the source and destination use the same system clock.

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295 MEMORY DEVICES I/O DEVICES Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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interface memory RAM ROM EPROM... or I/O devices to 8086 microprocessor. Several memory chips or I/O devices can connected to a microprocessor. An address decoding circuit is used to select the required I/O device or a memory chip. 296 interface memory RAM ROM EPROM... or I/O devices to 8086 microprocessor. Several memory chips or I/O devices can connected to a microprocessor. An address decoding circuit is used to select the required I/O device or a memory chip.

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IO mapped IO V/s Memory Mapped IO mapped IO V/s Memory Mapped IO IO Memory Mapped IO IO is treated as memory. 16-bit addressing. More Decoder Hardware. Can address 2 16 64k locations. Less memory is available. IO Mapped IO IO is treated IO. 8- bit addressing. Less Decoder Hardware. Can address 2 8 256 locations. Whole memory address space is available. 297 IO is treated as memory. 16-bit addressing. More Decoder Hardware. Can address 2 16 64k locations. Less memory is available. IO is treated IO. 8- bit addressing. Less Decoder Hardware. Can address 2 8 256 locations. Whole memory address space is available.

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Memory Mapped IO • Memory Instructions are used. • Memory control signals are used. • Arithmetic and logic operations can be performed on data. • Data transfer b/w register and IO. IO Mapped IO • Special Instructions are used like IN OUT. • Special control signals are used. • Arithmetic and logic operations can not be performed on data. • Data transfer b/w accumulator and IO. 298 • Memory Instructions are used. • Memory control signals are used. • Arithmetic and logic operations can be performed on data. • Data transfer b/w register and IO. • Special Instructions are used like IN OUT. • Special control signals are used. • Arithmetic and logic operations can not be performed on data. • Data transfer b/w accumulator and IO.

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Parallel communication interface INTEL 8255 INTEL 8255 299 Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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8255 PPI 8255 PPI • The 8255 chip is also called as Programmable Peripheral Interface. • The Intels 8255 is designed for use with Intels 8-bit 16-bit and higher capability microprocessors • The 8255 is a 40 pin integrated circuit IC designed to perform a variety of interface functions in a computer environment. • It is flexible and economical. 300 • The 8255 chip is also called as Programmable Peripheral Interface. • The Intels 8255 is designed for use with Intels 8-bit 16-bit and higher capability microprocessors • The 8255 is a 40 pin integrated circuit IC designed to perform a variety of interface functions in a computer environment. • It is flexible and economical.

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PIN DIAGRAM OF 8255 PIN DIAGRAM OF 8255 301

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Signals of 8085 Signals of 8085 302

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8255 PIO/PPI 8255 PIO/PPI It has 24 input/output lines which may be individually programmed. 2 groups of I/O pins are named as Group A Port-A Port C Upper Group B Port-B Port C Lower 3 portseach port has 8 bit Port A lines are identified by symbols PA0-PA7 Port B lines are identified by symbols PB0-PB7 Port C lines are identified by PC0-PC7 PC3-PC0 ie: PORT C UPPERPC7-PC4 PORT C LOWERPC3-PC0 303 It has 24 input/output lines which may be individually programmed. 2 groups of I/O pins are named as Group A Port-A Port C Upper Group B Port-B Port C Lower 3 portseach port has 8 bit Port A lines are identified by symbols PA0-PA7 Port B lines are identified by symbols PB0-PB7 Port C lines are identified by PC0-PC7 PC3-PC0 ie: PORT C UPPERPC7-PC4 PORT C LOWERPC3-PC0

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D0 - D7: data input/output lines for the device. All information read from and written to the 8255 occurs via these 8 data lines. CSChip Select. If this line is a logical 0 the microprocessor can read and write to the 8255. RESET : The 8255 is placed into its reset state if this input line is a logical 1 304 D0 - D7: data input/output lines for the device. All information read from and written to the 8255 occurs via these 8 data lines. CSChip Select. If this line is a logical 0 the microprocessor can read and write to the 8255. RESET : The 8255 is placed into its reset state if this input line is a logical 1

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• RD : This is the input line driven by the microprocessor and should be low to indicate read operation to 8255. • WR : This is an input line driven by the microprocessor. A low on this line indicates write operation. • A1-A0 : These are the address input lines and are driven by the microprocessor. 305 • RD : This is the input line driven by the microprocessor and should be low to indicate read operation to 8255. • WR : This is an input line driven by the microprocessor. A low on this line indicates write operation. • A1-A0 : These are the address input lines and are driven by the microprocessor.

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Control Logic Control Logic CS signal is the master Chip Select A0 and A1 specify one of the two I/O Ports CS A1 A0 Selected 0 0 0 Port A 306 0 0 0 Port A 0 0 1 Port B 0 1 0 Port C 0 1 1 Control Register 1 X X 8255 is not selected

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Block Diagram of 8255A Block Diagram of 8255A 307

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Block Diagram of 8255 Block Diagram of 8255 ArchitectureArchitecture It has a 40 pins of 4 parts. 1. Data bus buffer 2. Read/Write control logic 3. Group A and Group B controls 4. Port A B and C 308 It has a 40 pins of 4 parts. 1. Data bus buffer 2. Read/Write control logic 3. Group A and Group B controls 4. Port A B and C

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1. Data bus buffer 1. Data bus buffer This is a tristate bidirectional buffer used to interface the 8255 to system data bus. Data is transmitted or received by the buffer on execution of input or output instruction by the CPU. 309 This is a tristate bidirectional buffer used to interface the 8255 to system data bus. Data is transmitted or received by the buffer on execution of input or output instruction by the CPU.

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2. Read/Write control logic 2. Read/Write control logic This unit accepts control signals RD WR and also inputs from address bus and issues commands to individual group of control blocks Group A Group B. It has the following pins. CS RD WR RESET A1 A0 310 This unit accepts control signals RD WR and also inputs from address bus and issues commands to individual group of control blocks Group A Group B. It has the following pins. CS RD WR RESET A1 A0

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3. Group A and Group B controls 3. Group A and Group B controls • These block receive control from the CPU and issues commands to their respective ports. Group A - PA and PCU PC7 PC4 Group B PB and PCL PC3 PC0 a Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be programmed in 3 modes mode 0 mode 1 mode 2. 311 • These block receive control from the CPU and issues commands to their respective ports. Group A - PA and PCU PC7 PC4 Group B PB and PCL PC3 PC0 a Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be programmed in 3 modes mode 0 mode 1 mode 2.

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b Port B: It can be programmed in mode 0 mode1 c Port C : It can be programmed in mode 0 312

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313

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Modes of Operation of 8255 Modes of Operation of 8255 Bit Set/ResetBSR Mode Set/Reset bits in Port C I/O Mode Mode 0 Simple input/output Mode 1 Handshake mode Mode 2 Bidirectional Data Transfer 314 Bit Set/ResetBSR Mode Set/Reset bits in Port C I/O Mode Mode 0 Simple input/output Mode 1 Handshake mode Mode 2 Bidirectional Data Transfer

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1. BSR Mode 1. BSR Mode 315

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B3 B2 B1 Bit/pin of port C selected 0 0 0 PC 0 0 0 1 PC 1 0 1 0 PC 2 0 1 1 PC 3 1 0 0 PC 4 316 1 0 0 PC 4 1 0 1 PC 5 1 1 0 PC 6 1 1 1 PC 7 Concerned only with the 8-bits of Port C. Set or Reset by control word Ports A and B are not affected

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a Mode 0 Simple Input or Output: a Mode 0 Simple Input or Output: • Ports A and B are used as Simple I/O Ports • Port C as two 4-bit ports • Features – Outputs are latched – Inputs are not latched – Ports do not have handshake or interrupt capability 2. I/O MODE 2. I/O MODE 317 • Ports A and B are used as Simple I/O Ports • Port C as two 4-bit ports • Features – Outputs are latched – Inputs are not latched – Ports do not have handshake or interrupt capability

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318

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b b Mode 1: Mode 1: Input or Output with Input or Output with Handshake Handshake • Handshake signals are exchanged between MPU Peripherals • Features – Ports A and B are used as Simple I/O Ports – Each port uses 3 lines from Port C as handshake signals – Input Output data are latched – interrupt logic supported 319 • Handshake signals are exchanged between MPU Peripherals • Features – Ports A and B are used as Simple I/O Ports – Each port uses 3 lines from Port C as handshake signals – Input Output data are latched – interrupt logic supported

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c Mode 2: Bidirectional Data Transfer • Used primarily in applications such as data transfer between two computers • Features – Ports A can be configured as the bidirectional Port – Port B in Mode 0 or Mode 1. – Port A uses 5 Signals from Port C as handshake signals for data transfer – Remaining 3 Signals from Port C Used as Simple I/O or handshake for Port B 320 • Used primarily in applications such as data transfer between two computers • Features – Ports A can be configured as the bidirectional Port – Port B in Mode 0 or Mode 1. – Port A uses 5 Signals from Port C as handshake signals for data transfer – Remaining 3 Signals from Port C Used as Simple I/O or handshake for Port B

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Write a program to initialize 8255 in the configuration below.assume address of the CW register as 23H. 1 Port A: output with handshake 2 Port B: input with handshake 3 Port CL: output 4Port CU: input Solution: 1 0 1 0 1 1 1 0 AEH 321 1 0 1 0 1 1 1 0 AEH MVI AAEH LOAD CONTROL WORD OUT 23H SEND CONTROL WORD Program:

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Port A: Output Port B: Output Port CU: Output Port CL: Output Solution: 322 Solution: 1 0 0 0 0 0 0 0 80H The control word register for the above ports of Intel 8255 is 80H.

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Port A: Input Port B: Input Port CU: Input Port CL: Input Solution: 323 Solution: 1 0 0 1 1 0 1 1 9BH The control word register for the above ports of intel 8255 is 9BH.

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Basics of serial communication Basics of serial communication 1. Transmitter: - A parallel-in serial-out shift register 2. Receiver: - A serial-in parallel-out shift register. - 1. Transmitter: - A parallel-in serial-out shift register 2. Receiver: - A serial-in parallel-out shift register. - 324 Parallel Transfer

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TRANSMITTER Receiver 325 Receiver

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Serial communication interface INTEL 8251 USART INTEL 8251 USART 326

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U UNIVERSAL NIVERSAL S SYNCHRONOUS YNCHRONOUS A ASYNCHRONOUS SYNCHRONOUS R RECEIVER ECEIVER T TRANSMITTER USART RANSMITTER USART Programmable chip designed for synchronous and asynchronous serial data transmission 28 pin DIP Coverts the parallel data into a serial stream of bits suitable for serial transmission. Receives a serial stream of bits and convert it into parallel data bytes to be read by a microprocessor. 327 Programmable chip designed for synchronous and asynchronous serial data transmission 28 pin DIP Coverts the parallel data into a serial stream of bits suitable for serial transmission. Receives a serial stream of bits and convert it into parallel data bytes to be read by a microprocessor.

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328

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BLOCK DIAGRAM BLOCK DIAGRAM 329

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Five Sections Five Sections – Read/Write Control Logic • Interfaces the chip with MPU • Determine the functions according to the control word • Monitors data flow – Transmitter • Converts parallel word received from MPU into serial bits • Transmits serial bits over TXD line to a peripheral. – Receiver • Receives serial bits from peripheral • Converts serial bits into parallel word • Transfers the parallel word to the MPU – Data Bus Buffer- 8 bit Bidirectional bus. – Modem Controller • Used to establish data communication modems over telephone line 330 – Read/Write Control Logic • Interfaces the chip with MPU • Determine the functions according to the control word • Monitors data flow – Transmitter • Converts parallel word received from MPU into serial bits • Transmits serial bits over TXD line to a peripheral. – Receiver • Receives serial bits from peripheral • Converts serial bits into parallel word • Transfers the parallel word to the MPU – Data Bus Buffer- 8 bit Bidirectional bus. – Modem Controller • Used to establish data communication modems over telephone line

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Input Signals Input Signals CS Chip Select When this signal goes low 8251 is selected by MPU for communication C/D Control/Data When this signal is high the control register or status register is addressed When it is low the data buffer is addressed Control and Status register is differentiated by WR and RD signals respectively 331 CS Chip Select When this signal goes low 8251 is selected by MPU for communication C/D Control/Data When this signal is high the control register or status register is addressed When it is low the data buffer is addressed Control and Status register is differentiated by WR and RD signals respectively

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• WR Write – writes in the control register or sends outputs to the data buffer. – This connected to IOW or MEMW • RD Read – Either reads a status from status register or accepts data from the data buffer – This is connected to either IOR or MEMR • RESET - Reset • CLK - Clock – Connected to system clock – Necessary for communication with microprocessor. 332 • WR Write – writes in the control register or sends outputs to the data buffer. – This connected to IOW or MEMW • RD Read – Either reads a status from status register or accepts data from the data buffer – This is connected to either IOR or MEMR • RESET - Reset • CLK - Clock – Connected to system clock – Necessary for communication with microprocessor.

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CS C/D RD WR Function 0 1 1 0 MPU writes instruction in the control register 0 1 0 1 MPU reads status from the status register MPU outputs the data to the Data Buffer 333 MPU reads status from the status register 0 0 1 0 MPU outputs the data to the Data Buffer 0 0 0 1 MPU accepts data from the Data Buffer 1 X X X USART is not Selected

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• Control Register – 16-bit register – This register can be accessed an output port when the C/D pin is high • Status Register – Checks ready status of a peripheral • Data Buffer 334 • Control Register – 16-bit register – This register can be accessed an output port when the C/D pin is high • Status Register – Checks ready status of a peripheral • Data Buffer

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Transmitter Section Transmitter Section Accepts parallel data and converts it into serial data Two registers Buffer Register To hold eight bits Output Register Converts eight bits into a stream of serial bits Transmits data on TxD pin with appropriate framing bitsStart and Stop 335 Accepts parallel data and converts it into serial data Two registers Buffer Register To hold eight bits Output Register Converts eight bits into a stream of serial bits Transmits data on TxD pin with appropriate framing bitsStart and Stop

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Signals Associated with Transmitter Signals Associated with Transmitter Section Section • TxD Transmit Data – Serial bits are transmitted on this line • TxC Transmitter Clock – Controls the rate at which bits are transmitted • TxRDY Transmitter Ready – Can be used either to interrupt the MPU or indicate the status • TxE Transmitter Empty – Logic 1 on this line indicate that the output register is empty 336 • TxD Transmit Data – Serial bits are transmitted on this line • TxC Transmitter Clock – Controls the rate at which bits are transmitted • TxRDY Transmitter Ready – Can be used either to interrupt the MPU or indicate the status • TxE Transmitter Empty – Logic 1 on this line indicate that the output register is empty

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Receiver Section Receiver Section Accepts serial data from peripheral and converts it into parallel data The section has two registers Input Register Buffer Register 337 Accepts serial data from peripheral and converts it into parallel data The section has two registers Input Register Buffer Register

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Signals Associated with Receiver Signals Associated with Receiver Section Section RxD Receive Data Bits are received serially on this line and converted into parallel byte in the receiver input RxC Receiver Clock RxRDY Receiver Ready It goes high when the USART has a character in the buffer register and is ready to transfer it to the MPU 338 RxD Receive Data Bits are received serially on this line and converted into parallel byte in the receiver input RxC Receiver Clock RxRDY Receiver Ready It goes high when the USART has a character in the buffer register and is ready to transfer it to the MPU

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Signals Associated with Modem Signals Associated with Modem Control Control • DSR- Data Set Ready – Normally used to check if the Data Set is ready when communicating with a modem • DTR – Data Terminal Ready – device is ready to accept data when the 8251 is communicating with a modem. • RTS – Request to send Data – the receiver is ready to receive a data byte from modem • CTS – Clear to Send 339 • DSR- Data Set Ready – Normally used to check if the Data Set is ready when communicating with a modem • DTR – Data Terminal Ready – device is ready to accept data when the 8251 is communicating with a modem. • RTS – Request to send Data – the receiver is ready to receive a data byte from modem • CTS – Clear to Send

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Control words Control words 340

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Interfacing of 8255PPI with 8085 processor: 345

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11- 347 Programming 8251 8251 mode register 7 6 5 4 3 2 1 0 Mode register Number of Stop bits Parity enable 0: disable 1: enable Baud Rate Number of Stop bits 00: invalid 01: 1 bit 10: 1.5 bits 11: 2 bits Parity 0: odd 1: even Parity enable 0: disable 1: enable Character length 00: 5 bits 01: 6 bits 10: 7 bits 11: 8 bits Baud Rate 00: Syn. Mode 01: x1 clock 10: x16 clock 11: x64 clock

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11- 348 8251 command register EH IR RTS ER SBRK RxE DTR TxE command register TxE: transmit enable DTR: data terminal ready DTR pin will be low RxE: receiver enable SBPRK: send break character TxD pin will be low ER: error reset RTS: request to send CTS pin will be low IR: internal reset EH: enter hunt mode 1enable search for SYN character TxE: transmit enable DTR: data terminal ready DTR pin will be low RxE: receiver enable SBPRK: send break character TxD pin will be low ER: error reset RTS: request to send CTS pin will be low IR: internal reset EH: enter hunt mode 1enable search for SYN character

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11- 349 8251 status register DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY status register TxRDY: transmit ready RxRDY: receiver ready TxEMPTY: transmitter empty PE: parity error OE: overrun error FE: framing error SYNDET: sync. character detected DSR: data set ready TxRDY: transmit ready RxRDY: receiver ready TxEMPTY: transmitter empty PE: parity error OE: overrun error FE: framing error SYNDET: sync. character detected DSR: data set ready

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The analog to digital converter chips 0808 and 0809 are 8-bit CMOSsuccessive approximation converters. Successive approximation technique is one of the fast techniques for analog to digital conversion. The conversion delay is 100 µs at a clock frequency of 640 kHz. 351 The analog to digital converter chips 0808 and 0809 are 8-bit CMOSsuccessive approximation converters. Successive approximation technique is one of the fast techniques for analog to digital conversion. The conversion delay is 100 µs at a clock frequency of 640 kHz.

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The digital to analog converters convert binary numbers into their analog equivalent voltages or currents. Techniques are employed for digital to analog conversion. i. Weighted resistor network ii. R-2R ladder network iii. Current output D/A converter 357 The digital to analog converters convert binary numbers into their analog equivalent voltages or currents. Techniques are employed for digital to analog conversion. i. Weighted resistor network ii. R-2R ladder network iii. Current output D/A converter

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The DAC find applications in areas like digitally controlled gains motor speed control programmable gain amplifiers digital voltmeters panel meters etc. In a compact disk audio player for example a 14 or16-bit D/A converter is used to convert the binary data read off the disk by a laser to an analog audio signal. Characteristics : 1. Resolution: It is a change in analog output for one LSB change in digital input. It is given by1/2n Vref. If n8 i.e.8-bit DAC 1/2565V39.06mV 2. Settling time: It is the time required for the DAC to settle for a full scale code change. 358 The DAC find applications in areas like digitally controlled gains motor speed control programmable gain amplifiers digital voltmeters panel meters etc. In a compact disk audio player for example a 14 or16-bit D/A converter is used to convert the binary data read off the disk by a laser to an analog audio signal. Characteristics : 1. Resolution: It is a change in analog output for one LSB change in digital input. It is given by1/2n Vref. If n8 i.e.8-bit DAC 1/2565V39.06mV 2. Settling time: It is the time required for the DAC to settle for a full scale code change.

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DAC 0800 8-bit Digital to Analog converter Features: i. DAC0800 is a monolithic 8-bit DAC manufactured by National semiconductor. ii. It has settling time around 100ms iii. It can operate on a range of power supply voltage i.e. from 4.5V to +18V. Usually the supply V+ is 5V or +12V. The V- pin can be kept at a minimum of -12V. iv. Resolution of the DAC is 39.06mV 359 DAC 0800 8-bit Digital to Analog converter Features: i. DAC0800 is a monolithic 8-bit DAC manufactured by National semiconductor. ii. It has settling time around 100ms iii. It can operate on a range of power supply voltage i.e. from 4.5V to +18V. Usually the supply V+ is 5V or +12V. The V- pin can be kept at a minimum of -12V. iv. Resolution of the DAC is 39.06mV

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TIMER/COUNTER TIMER/COUNTER 362

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RD: read signal WR: write signal CS: chip select signal A0 A1: address lines Clock :This is the clock input for the counter. The counter is 16 bits. Out :This single output line is the signal that is the final programmed output of the device. Gate :This input can act as a gate for the clock input line or it can act as a start pulse 364 RD: read signal WR: write signal CS: chip select signal A0 A1: address lines Clock :This is the clock input for the counter. The counter is 16 bits. Out :This single output line is the signal that is the final programmed output of the device. Gate :This input can act as a gate for the clock input line or it can act as a start pulse

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8254 Programming 11-367

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8254 Modes Gate is low the count will be paused Gate is high Will continue counting Mode 0: An events counter enabled with G. Gate is high Will continue counting Mode 1: One-shot mode. s Gate is High output will be high Counter will be reloaded After gate high. 368

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Mode 2: Counter generates a series of pulses 1 clock pulse wide cycle is repeated until reprogrammed or G pin set to 0 Mode 3: Generates a continuous square-wave with G set to 1 cycle is repeated until reprogrammed or G pin set to 0 If count is even 50 duty cycle otherwise OUT is high 1 cycle longer 369

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Mode 4: Software triggered one-shot. In the last counting Will be stop not repeated Mode 5: Hardware triggered one-shot. G controls similar to Mode 1. In the last count Out will be low 370

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Keyboard/Display Controller INTEL 8279 371 Keyboard/Display Controller INTEL 8279

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The INTEL 8279 is specially developed for interfacing keyboard and display devices to 8085/8086 microprocessor based system 372 The INTEL 8279 is specially developed for interfacing keyboard and display devices to 8085/8086 microprocessor based system

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Simultaneous keyboard and display operations Scanned keyboard mode Scanned sensor mode 8-character keyboard FIFO 1 6-character display 373 Simultaneous keyboard and display operations Scanned keyboard mode Scanned sensor mode 8-character keyboard FIFO 1 6-character display

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Keyboard section Display section Scan section CPU interface section 375 Keyboard section Display section Scan section CPU interface section

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The keyboard section consists of 8 return lines RL0 - RL7 that can be used to form the columns of a keyboard matrix. It has two additional input : shift and control/strobe. The keys are automatically debounced. The two operating modes of keyboard section are 2-key lockout and N-key rollover. 378 The keyboard section consists of 8 return lines RL0 - RL7 that can be used to form the columns of a keyboard matrix. It has two additional input : shift and control/strobe. The keys are automatically debounced. The two operating modes of keyboard section are 2-key lockout and N-key rollover.

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In the 2-key lockout mode if two keys are pressed simultaneously only the first key is recognized. In the N-key rollover mode simultaneous keys are recognized and their codes are stored in FIFO. The keyboard section also have an 8 x 8 FIFO First In First Out RAM. The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and control key are also stored along with key code. The 8279 generate an interrupt signal IRQwhen there is an entry in FIFO. 379 In the 2-key lockout mode if two keys are pressed simultaneously only the first key is recognized. In the N-key rollover mode simultaneous keys are recognized and their codes are stored in FIFO. The keyboard section also have an 8 x 8 FIFO First In First Out RAM. The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and control key are also stored along with key code. The 8279 generate an interrupt signal IRQwhen there is an entry in FIFO.

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The display section has eight output lines divided into two groups A0-A3 and B0-B3. The output lines can be used either as a single group of eight lines or as two groups of four lines in conjunction with the scan lines for a multiplexed display. The output lines are connected to the anodes through driver transistor in case of common cathode 7-segment LEDs. 380 The display section has eight output lines divided into two groups A0-A3 and B0-B3. The output lines can be used either as a single group of eight lines or as two groups of four lines in conjunction with the scan lines for a multiplexed display. The output lines are connected to the anodes through driver transistor in case of common cathode 7-segment LEDs.

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The cathodes are connected to scan lines through driver transistors. The display can be blanked by BD low line. The display section consists of 16 x 8 display RAM. The CPU can read from or write into any location of the display RAM. 381 The cathodes are connected to scan lines through driver transistors. The display can be blanked by BD low line. The display section consists of 16 x 8 display RAM. The CPU can read from or write into any location of the display RAM.

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The scan section has a scan counter and four scan lines SL0 to SL3. In decoded scan mode the output of scan lines will be similar to a 2-to-4 decoder. In encoded scan mode the output of scan lines will be binary count and so an external decoder should be used to convert the binary count to decoded output. The scan lines are common for keyboard and display. 382 The scan section has a scan counter and four scan lines SL0 to SL3. In decoded scan mode the output of scan lines will be similar to a 2-to-4 decoder. In encoded scan mode the output of scan lines will be binary count and so an external decoder should be used to convert the binary count to decoded output. The scan lines are common for keyboard and display.

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The CPU interface section takes care of data transfer between 8279 and the processor. This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and CPU. It requires two internal address A 0 for selecting data buffer and A 1 for selecting control register of8279. 383 The CPU interface section takes care of data transfer between 8279 and the processor. This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and CPU. It requires two internal address A 0 for selecting data buffer and A 1 for selecting control register of8279.

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The control signals WR low RD low CS low and A0 are used for read/write to 8279. It has an interrupt request line IRQ for interrupt driven data transfer with processor. The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the input clock by an internal prescaler. 384 The control signals WR low RD low CS low and A0 are used for read/write to 8279. It has an interrupt request line IRQ for interrupt driven data transfer with processor. The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the input clock by an internal prescaler.

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All the command words or status words are written or read with A0 1 and CS 0 to or from 8279. a Keyboard Display Mode Set : The format of the command word to select different modes of operation of 8279 is given below with its bit definitions. D7 D6 D5 D4 D3 D2 D1 D0 385 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 D D K K K

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386 SENSOR MATRIX SENSOR MATRIX

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B Programmable clock : The clock for operation of 8279 is obtained by dividing the external clock input signal by a programmable constant called prescaler. PPPPP is a 5-bit binary constant. The input frequency is divided by a decimal constant ranging from 2 to 31 decided by the bits of an internal prescaler PPPPP. 387 B Programmable clock : The clock for operation of 8279 is obtained by dividing the external clock input signal by a programmable constant called prescaler. PPPPP is a 5-bit binary constant. The input frequency is divided by a decimal constant ranging from 2 to 31 decided by the bits of an internal prescaler PPPPP. D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 P P P P P

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c Read FIFO / Sensor RAM : The format of this command is given below. AI Auto Increment Flag AAA Address pointer to 8 bit FIFO RAM X- Dont care This word is written to set up 8279 for reading FIFO/ sensor RAM. In scanned keyboard mode AI and AAA bits are of no use. The 8279 will automatically drive data bus for each subsequent read in the same sequence in which the data was entered. In sensor matrix mode the bits AAA select one of the 8 rows of RAM. If AI flag is set each successive read will be from the subsequent RAM location. D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 AI X A A A 388 c Read FIFO / Sensor RAM : The format of this command is given below. AI Auto Increment Flag AAA Address pointer to 8 bit FIFO RAM X- Dont care This word is written to set up 8279 for reading FIFO/ sensor RAM. In scanned keyboard mode AI and AAA bits are of no use. The 8279 will automatically drive data bus for each subsequent read in the same sequence in which the data was entered. In sensor matrix mode the bits AAA select one of the 8 rows of RAM. If AI flag is set each successive read will be from the subsequent RAM location.

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d Read Display RAM : This command enables a programmer to read the display RAM data. The CPU writes this command word to 8279 to prepare it for display RAM read operation. AI is auto increment flag and AAAA the 4-bit address points to the 16-byte display RAM that is to be read. If AI1 the address will be automatically incremented after each read or write to the Display RAM. The same address counter is used for reading and writing. D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 AI A A A A 389 d Read Display RAM : This command enables a programmer to read the display RAM data. The CPU writes this command word to 8279 to prepare it for display RAM read operation. AI is auto increment flag and AAAA the 4-bit address points to the 16-byte display RAM that is to be read. If AI1 the address will be automatically incremented after each read or write to the Display RAM. The same address counter is used for reading and writing.

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d Write Display RAM : This command enables a programmer to write the display RAM data. AI Auto increment Flag. AAAA 4 bit address for 16-bit display RAM to be written. e Display Write Inhibit/Blanking : D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 AI A A A A 390 d Write Display RAM : This command enables a programmer to write the display RAM data. AI Auto increment Flag. AAAA 4 bit address for 16-bit display RAM to be written. e Display Write Inhibit/Blanking : D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 X IW IW BL BL IW - inhibit write flag BL - blank display bit flags

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g Clear Display RAM : ENABLES CLEAR DISPLAY WHEN CD21 • CD2 must be 1 for enabling the clear display command. • If CD2 0 the clear display command is invoked by setting CACLEAR ALL 1 and maintaining CD1 CD0 bits exactly same as above. • If CFCLEAR FIFO RAM STATUS 1 FIFO status is cleared and IRQ line is pulled down and the sensor RAM pointer is set to row 0. •If CA1 this combines the effect of CD and CF bits. D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 CD2 CD1 CD0 CF CA CD2 CD1 CD0 0X - All zeros x dont care AB00 10 - A3-A0 2 0010 and B3-B000 0000 11 - All ones AB FF i.e. clear RAM 391 g Clear Display RAM : ENABLES CLEAR DISPLAY WHEN CD21 • CD2 must be 1 for enabling the clear display command. • If CD2 0 the clear display command is invoked by setting CACLEAR ALL 1 and maintaining CD1 CD0 bits exactly same as above. • If CFCLEAR FIFO RAM STATUS 1 FIFO status is cleared and IRQ line is pulled down and the sensor RAM pointer is set to row 0. •If CA1 this combines the effect of CD and CF bits. 0X - All zeros x dont care AB00 10 - A3-A0 2 0010 and B3-B000 0000 11 - All ones AB FF i.e. clear RAM

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h End Interrupt / Error mode Set : E- Error mode X- dont care For the sensor matrix mode this command lowers the IRQ line and enables further writing into the RAM. Otherwise if a change in sensor value is detected IRQ goes high that inhibits writing in the sensor RAM. For N-Key roll over mode if the E bit is programmed to be 1 the 8279 operates in special Error mode D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 E X X X 1 392 h End Interrupt / Error mode Set : E- Error mode X- dont care For the sensor matrix mode this command lowers the IRQ line and enables further writing into the RAM. Otherwise if a change in sensor value is detected IRQ goes high that inhibits writing in the sensor RAM. For N-Key roll over mode if the E bit is programmed to be 1 the 8279 operates in special Error mode

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INTERRUPT INTERRUPT CONTROLLER CONTROLLER 393 INTERRUPT INTERRUPT CONTROLLER CONTROLLER

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If we are working with an 8086 we have a problem here because the 8086 has only two interrupt inputs NMI and INTR. If we save NMI for a power failure interrupt this leaves only one interrupt for all the other applications. For applications where we have interrupts from multiple source we use an external device called a priority interrupt controller PIC to the interrupt signals into a single interrupt input on the processor. 394 If we are working with an 8086 we have a problem here because the 8086 has only two interrupt inputs NMI and INTR. If we save NMI for a power failure interrupt this leaves only one interrupt for all the other applications. For applications where we have interrupts from multiple source we use an external device called a priority interrupt controller PIC to the interrupt signals into a single interrupt input on the processor.

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Interrupt Request Register RR: The interrupts at IRQ input lines are handled by Interrupt Request internally. IRR stores all the interrupt request in it in order to serve them one by one on the priority basis. In-Service Register ISR: This stores all the interrupt requests those are being served i.e. ISR keeps a track of the requests being served. 396 Interrupt Request Register RR: The interrupts at IRQ input lines are handled by Interrupt Request internally. IRR stores all the interrupt request in it in order to serve them one by one on the priority basis. In-Service Register ISR: This stores all the interrupt requests those are being served i.e. ISR keeps a track of the requests being served.

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Priority Resolver : This unit determines the priorities of the interrupt requests appearing simultaneously. The highest priority is selected and stored into the corresponding bit of ISR during INTA pulse. The IR0 has the highest priority while the IR7 has the lowest one normally in fixed priority mode. The priorities however may be altered by programming the 8259A in rotating priority mode. Interrupt Mask Register IMR : This register stores the bits required to mask the interrupt inputs. IMR operates on IRR at the direction of the Priority Resolver. 397 Priority Resolver : This unit determines the priorities of the interrupt requests appearing simultaneously. The highest priority is selected and stored into the corresponding bit of ISR during INTA pulse. The IR0 has the highest priority while the IR7 has the lowest one normally in fixed priority mode. The priorities however may be altered by programming the 8259A in rotating priority mode. Interrupt Mask Register IMR : This register stores the bits required to mask the interrupt inputs. IMR operates on IRR at the direction of the Priority Resolver.

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Interrupt Control Logic: This block manages the interrupt and interrupt acknowledge signals to be sent to the CPU for serving one of the eight interrupt requests. This also accepts the interrupt acknowledge INTA signal from CPU that causes the 8259A to release vector address on to the data bus. Data Bus Buffer : This tristate bidirectional buffer interfaces internal 8259A bus to the microprocessor system data bus. Control words status and vector information pass through data buffer during read or write operations. 398 Interrupt Control Logic: This block manages the interrupt and interrupt acknowledge signals to be sent to the CPU for serving one of the eight interrupt requests. This also accepts the interrupt acknowledge INTA signal from CPU that causes the 8259A to release vector address on to the data bus. Data Bus Buffer : This tristate bidirectional buffer interfaces internal 8259A bus to the microprocessor system data bus. Control words status and vector information pass through data buffer during read or write operations.

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Read/Write Control Logic: This circuit accepts and decodes commands from the CPU. This block also allows the status of the 8259A to be transferred on to the data bus. Cascade Buffer/Comparator: This block stores and compares the IDs all the 8259A used in system. The three I/O pins CASO-2 are outputs when the 8259A is used as a master. The same pins act as inputs when the 8259A is in slave mode. The 8259A in master mode sends the ID of the interrupting slave device on these lines. The slave thus selected will send its preprogrammed vector address on the data bus during the next INTA pulse. 399 Read/Write Control Logic: This circuit accepts and decodes commands from the CPU. This block also allows the status of the 8259A to be transferred on to the data bus. Cascade Buffer/Comparator: This block stores and compares the IDs all the 8259A used in system. The three I/O pins CASO-2 are outputs when the 8259A is used as a master. The same pins act as inputs when the 8259A is in slave mode. The 8259A in master mode sends the ID of the interrupting slave device on these lines. The slave thus selected will send its preprogrammed vector address on the data bus during the next INTA pulse.

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8237DMA CONTROLLER 400

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Introduction: Direct Memory AccessDMA is a method of allowing data to be moved from one location to another in a computer without intervention from the central processorCPU. It is also a fast way of transferring data withinand sometimes between computer. The DMA I/O technique provides direct access to the memory while the microprocessor is temporarily disabled. The DMA controller temporarily borrows the address bus data bus and control bus from the microprocessor and transfers the data directly from the external devices to a series of memory locationsand vice versa. Direct Memory AccessDMA is a method of allowing data to be moved from one location to another in a computer without intervention from the central processorCPU. It is also a fast way of transferring data withinand sometimes between computer. The DMA I/O technique provides direct access to the memory while the microprocessor is temporarily disabled. The DMA controller temporarily borrows the address bus data bus and control bus from the microprocessor and transfers the data directly from the external devices to a series of memory locationsand vice versa. 401

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The 8237 DMA controller • Supplies memory and I/O with control signals and addresses during DMA transfer • 4-channels expandable – 0: DRAM refresh – 1: Free – 2: Floppy disk controller – 3: Free • 1.6MByte/sec transfer rate • 64 KByte section of memory address capability with single programming • “fly-by” controller data does not pass through the DMA-only memory to I/O transfer capability • Initialization involves writing into each channel: • i The address of the first byte of the block of data that must be transferred called the base address. • ii The number of bytes to be transferred called the word count. • Supplies memory and I/O with control signals and addresses during DMA transfer • 4-channels expandable – 0: DRAM refresh – 1: Free – 2: Floppy disk controller – 3: Free • 1.6MByte/sec transfer rate • 64 KByte section of memory address capability with single programming • “fly-by” controller data does not pass through the DMA-only memory to I/O transfer capability • Initialization involves writing into each channel: • i The address of the first byte of the block of data that must be transferred called the base address. • ii The number of bytes to be transferred called the word count. 402

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8237 pins • CLK: System clock • CS΄: Chip select decoder output • RESET: Clears registers sets mask register • READY: 0 for inserting wait states • HLDA: Signals that the μp has relinquished buses • DREQ3 – DREQ0: DMA request input for each channel • DB7-DB0: Data bus pins • IOR΄: Bidirectional pin used during programming and during a DMA write cycle • IOW΄: Bidirectional pin used during programming and during a DMA read cycle • EOP΄: End of process is a bidirectional signal used as input to terminate a DMA process or as output to signal the end of the DMA transfer • A3-A0: Address pins for selecting internal registers • A7-A4: Outputs that provide part of the DMA transfer address • HRQ: DMA request output • DACK3-DACK0: DMA acknowledge for each channel. • AEN: Address enable signal • ADSTB: Address strobe • MEMR΄: Memory read output used in DMA read cycle • MEMW΄: Memory write output used in DMA write cycle • CLK: System clock • CS΄: Chip select decoder output • RESET: Clears registers sets mask register • READY: 0 for inserting wait states • HLDA: Signals that the μp has relinquished buses • DREQ3 – DREQ0: DMA request input for each channel • DB7-DB0: Data bus pins • IOR΄: Bidirectional pin used during programming and during a DMA write cycle • IOW΄: Bidirectional pin used during programming and during a DMA read cycle • EOP΄: End of process is a bidirectional signal used as input to terminate a DMA process or as output to signal the end of the DMA transfer • A3-A0: Address pins for selecting internal registers • A7-A4: Outputs that provide part of the DMA transfer address • HRQ: DMA request output • DACK3-DACK0: DMA acknowledge for each channel. • AEN: Address enable signal • ADSTB: Address strobe • MEMR΄: Memory read output used in DMA read cycle • MEMW΄: Memory write output used in DMA write cycle 403

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8237 block diagram 404

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Block Diagram Description It containing Five main Blocks. 1. Data bus buffer 2. Read/Control logic 3. Control logic block 4. Priority resolver 5. DMA channels. It containing Five main Blocks. 1. Data bus buffer 2. Read/Control logic 3. Control logic block 4. Priority resolver 5. DMA channels. 405

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DATA BUS BUFFER: It contain tristate 8 bit bi-directional buffer. Slave mode it transfer data between microprocessor and internal data bus. Master mode the outputs A8-A15 bits of memory address on data lines Unidirectional. READ/CONTROL LOGIC: It control all internal Read/Write operation. Slave mode it accepts address bits and control signal from microprocessor. Master mode it generate address bits and control signal. DATA BUS BUFFER: It contain tristate 8 bit bi-directional buffer. Slave mode it transfer data between microprocessor and internal data bus. Master mode the outputs A8-A15 bits of memory address on data lines Unidirectional. READ/CONTROL LOGIC: It control all internal Read/Write operation. Slave mode it accepts address bits and control signal from microprocessor. Master mode it generate address bits and control signal. 406

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Control logic block It contains 1. Control logic 2. Mode set register and 3. Status Register. CONTROL LOGIC: Master mode It control the sequence of DMA operation during all DMA cycles. It generates address and control signals. It increments 16 bit address and decrement 14 bit counter registers. It activate a HRQ signal on DMA channel Request. Slave mode it is disabled. Control logic block It contains 1. Control logic 2. Mode set register and 3. Status Register. CONTROL LOGIC: Master mode It control the sequence of DMA operation during all DMA cycles. It generates address and control signals. It increments 16 bit address and decrement 14 bit counter registers. It activate a HRQ signal on DMA channel Request. Slave mode it is disabled. 407

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DMA controller details 408

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Programming and applications Case studies 1.Traffic Light control 2.LED display 3.LCD display 4.Keyboard display interface 5.Alarm Controller Programming and applications Case studies 1.Traffic Light control 2.LED display 3.LCD display 4.Keyboard display interface 5.Alarm Controller 409

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1. TRAFFIC LIGHT CONTROL 1. TRAFFIC LIGHT CONTROL 410

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Traffic lights which may also be known as stoplights traffic lamps traffic signals signal lights robots or semaphore are signaling devices positioned at road intersections pedestrian crossings and other locations to control competing flows of traffic. INTERFACING TRAFFIC LIGHT WITH 8086 The Traffic light controller section consists of 12 Nos. point leds arranged by 4Lanes in Traffic light interface card. Each lane has GoGreen ListenYellow and StopRed LED is being placed. Traffic lights which may also be known as stoplights traffic lamps traffic signals signal lights robots or semaphore are signaling devices positioned at road intersections pedestrian crossings and other locations to control competing flows of traffic. INTERFACING TRAFFIC LIGHT WITH 8086 The Traffic light controller section consists of 12 Nos. point leds arranged by 4Lanes in Traffic light interface card. Each lane has GoGreen ListenYellow and StopRed LED is being placed. 411

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LAN Direction 8086 LINES MODULES 412

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CIRCUIT DIAGRAM TO INTERFACE TRAFFIC LIGHT WITH 8086 413

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8086 ALP: 1100: START: MOV BX 1200H MOV CX 0008H MOV ALBX MOV DX CONTROL PORT OUT DX AL INC BX NEXT: MOV ALBX MOV DX PORT A OUT DXAL CALL DELAY INC BX LOOP NEXT JMP START DELAY: PUSH CX MOV CX0005H REPEAT: MOV DX0FFFFH LOOP2: DEC DX JNZ LOOP2 LOOP REPEAT POP CX RET 1100: START: MOV BX 1200H MOV CX 0008H MOV ALBX MOV DX CONTROL PORT OUT DX AL INC BX NEXT: MOV ALBX MOV DX PORT A OUT DXAL CALL DELAY INC BX LOOP NEXT JMP START DELAY: PUSH CX MOV CX0005H REPEAT: MOV DX0FFFFH LOOP2: DEC DX JNZ LOOP2 LOOP REPEAT POP CX RET 414

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Lookup Table 1200 80H 1201 21H09H10H00HSOUTH WAY 1205 0CH09H80H00HEAST WAY 1209 64H08H00H04HNOURTH WAY 120D 24H03H02H00HWEST WAY 1211 END 1200 80H 1201 21H09H10H00HSOUTH WAY 1205 0CH09H80H00HEAST WAY 1209 64H08H00H04HNOURTH WAY 120D 24H03H02H00HWEST WAY 1211 END 415

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2. LED DISPLAY 416

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Light Emitting DiodesLED is the most commonly used components usually for displaying pins digital states. Typical uses of LEDs include alarm devices timers and confirmation of user input such as a mouse click or keystroke. INTERFACING LED Anode is connected through a resistor to GND the Cathode is connected to the Microprocessor pin. So when the Port Pin is HIGH the LED is OFF when the Port Pin is LOW the LED is turned ON. Light Emitting DiodesLED is the most commonly used components usually for displaying pins digital states. Typical uses of LEDs include alarm devices timers and confirmation of user input such as a mouse click or keystroke. INTERFACING LED Anode is connected through a resistor to GND the Cathode is connected to the Microprocessor pin. So when the Port Pin is HIGH the LED is OFF when the Port Pin is LOW the LED is turned ON. 417

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PIN ASSIGNMENT WITH 8086 418

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INTERFACE LED WITH 8255 419

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8086 ALP LED interface 1100: START: MOV AL 80 MOV DX FF36 OUT DX AL BEGIN: MOV AL 00 MOV DX FF30 OUT DX AL CALL DELAY MOV AL FF OUT DX AL CALL DELAY JMP BEGIN DELAY: MOV CX FFFF PO: DEC CX JNE PO RET 1100: START: MOV AL 80 MOV DX FF36 OUT DX AL BEGIN: MOV AL 00 MOV DX FF30 OUT DX AL CALL DELAY MOV AL FF OUT DX AL CALL DELAY JMP BEGIN DELAY: MOV CX FFFF PO: DEC CX JNE PO RET 420

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3. LCD DISPLAY 421

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422

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HARDWARE CONFIGURATION OF LCD WITH 8051/8086/8085 423

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LCD INTERFACING WITH 8086 TRAINER KIT GPIO- I 8255 J1 Connector PORTS ADDRESS Control port FF26 PORT A FF20 PORT B FF22 PORT C FF24 GPIO- I 8255 J1 Connector PORTS ADDRESS Control port FF26 PORT A FF20 PORT B FF22 PORT C FF24 GPIO- I 8255 J4 Connector PORTS ADDRESS Control port FF36 PORT A FF30 PORT B FF32 PORT C FF34 424

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425

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LCD INTERFACING WITH 8051 TRAINER KIT GPIO- I 8255 J1 Connector PORTS ADDRESS Control port 4003 PORT A 4000 PORT B 4001 PORT C 4002 Used in UNIT 5 also GPIO- I 8255 J1 Connector PORTS ADDRESS Control port 4003 PORT A 4000 PORT B 4001 PORT C 4002 426

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427

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4. Keyboard display interface 428

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HARDW ARE DESCRIPTION OF 8279 INTERFACE CARD Keyboard and display is configured in the encoded mode. In the encoded mode a binary count sequence is put on the scan lines SL0-SL3.These lines must be externally decoded to provide the scan lines for keyboard and display. A 3 to 8 decoder 74LS138 is provided for this purpose. The S0-S1 output lines of this decoder are connected to the two rows of the keyboard. And QA0 to QA7 is connected to 7 Segment Display 429

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PIN DIAGRAM OF 8279 PIN DIAGRAMOF 74LS138 430 Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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431

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432

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MVI A 00H Initialize keyboard/display in encoded OUT 81H scan keyboard 2 key lockout mode MVI A 34H OUT 81H Initialize prescaler count MVI A 0BH Load mask pattern to enable RST 7.5 SIM mask other interrupts EI Enable Interrupt HERE: JMP HERE Wait for the interrupt Interrupt service routine MVI A 40H Initialize 8279 in read FIFO RAM mode OUT 81H IN 80H Get keycode MVI H 62H Initialize memory pointer to point MOV L A 7-Segment code MVI A 80H : Initialize 8279 in write display RAM mode OUT 81H MOV A M : Get the 7 segment code OUT 80H : Write 7-segment code in display RAM EI : Enable interrupt RET : Return to main program 433 MVI A 00H Initialize keyboard/display in encoded OUT 81H scan keyboard 2 key lockout mode MVI A 34H OUT 81H Initialize prescaler count MVI A 0BH Load mask pattern to enable RST 7.5 SIM mask other interrupts EI Enable Interrupt HERE: JMP HERE Wait for the interrupt Interrupt service routine MVI A 40H Initialize 8279 in read FIFO RAM mode OUT 81H IN 80H Get keycode MVI H 62H Initialize memory pointer to point MOV L A 7-Segment code MVI A 80H : Initialize 8279 in write display RAM mode OUT 81H MOV A M : Get the 7 segment code OUT 80H : Write 7-segment code in display RAM EI : Enable interrupt RET : Return to main program

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5. ALARM 5. ALARM CONTROLLER CONTROLLER Relevant Material Not exact 434 Relevant Material Not exact

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435

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GPIO- I J1 Connecter PORTS ADDRESS Control port FF26 PORT A FF20 PORT B FF22 PORT C FF24 436 GPIO- I J1 Connecter PORTS ADDRESS Control port FF26 PORT A FF20 PORT B FF22 PORT C FF24 GPIO- II J1 Connecter PORTS ADDRESS Control port FF36 PORT A FF30 PORT B FF32 PORT C FF34

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TEXT BOOK References Main Book: 1. Microprocessors and Interfacing Programming and Hardware by Doughlas V.Hall Other Authors: 2. Microcomputer Systems: The 8086 / 8088 Family -Architecture Programming and Design by Yu-Cheng Liu Glenn A.Gibson 3. INTEL Microprocessors 8086/8088 80186/80188 80286 80386 80486 Pentium Prentium ProProcessor Pentium II III 4 by Barry B. Bery 4. Advanced microprocessor and peripherals by A K RAY LOCAL AUTHOR: 5.8086 Microprocessor by Nagoor Kani ONLINE MATERILALS: www.vtulearning.com Main Book: 1. Microprocessors and Interfacing Programming and Hardware by Doughlas V.Hall Other Authors: 2. Microcomputer Systems: The 8086 / 8088 Family -Architecture Programming and Design by Yu-Cheng Liu Glenn A.Gibson 3. INTEL Microprocessors 8086/8088 80186/80188 80286 80386 80486 Pentium Prentium ProProcessor Pentium II III 4 by Barry B. Bery 4. Advanced microprocessor and peripherals by A K RAY LOCAL AUTHOR: 5.8086 Microprocessor by Nagoor Kani ONLINE MATERILALS: www.vtulearning.com 437

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Documents References • 8086 SYSTEM BUS STRUCTURE by Prof.L.PETER STANLEY BEBINGTON PROFESSOR AND DEANACADEMICVCETErode • I/O Interfacing by Prof.P.JAYACHANDAR ASSOCIATE PROFESSOR and DEANSAVCETErode • 8086 Microprocessor by Dr. M. Gopikrishna Assistant Professor of PhysicsMaharajas College Ernakulam • 8086 architecture By Er. Swapnil Kaware • 8086 presentations by Gursharan Singh TatlaEazynotes.com • Interfacing 8255 by Anuja Bhakuni in Technology • Microprocessor and-interfacing by Akshay Makadiya • Interfacing is for microprocessor by R-THANDAIAH PRABU M.E. Lecturer ECE • Microprocessor - Ramesh Gaonkar • 8086 micro processor prasadpawaskar • 8086 class notes-Y.N.M by MURTHY Y.N • Introduction to 8086 Microprocessor by Rajvir Singh • 8086 micro processor by Poojith Chowdhary • 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar Cutajar • Intel microprocessor history by Ramzi_Alqrainy • 8086 SYSTEM BUS STRUCTURE by Prof.L.PETER STANLEY BEBINGTON PROFESSOR AND DEANACADEMICVCETErode • I/O Interfacing by Prof.P.JAYACHANDAR ASSOCIATE PROFESSOR and DEANSAVCETErode • 8086 Microprocessor by Dr. M. Gopikrishna Assistant Professor of PhysicsMaharajas College Ernakulam • 8086 architecture By Er. Swapnil Kaware • 8086 presentations by Gursharan Singh TatlaEazynotes.com • Interfacing 8255 by Anuja Bhakuni in Technology • Microprocessor and-interfacing by Akshay Makadiya • Interfacing is for microprocessor by R-THANDAIAH PRABU M.E. Lecturer ECE • Microprocessor - Ramesh Gaonkar • 8086 micro processor prasadpawaskar • 8086 class notes-Y.N.M by MURTHY Y.N • Introduction to 8086 Microprocessor by Rajvir Singh • 8086 micro processor by Poojith Chowdhary • 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar Cutajar • Intel microprocessor history by Ramzi_Alqrainy 438

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Website References • http://80864beginner.com/ • www.eazynotes.com • www.slideshare.net • www.scribd.com • www.docstoc.com • www.slideworld.com • www.nptel.ac.in • http://opencourses.emu.edu.tr/ • http://engineeringppt.blogspot.in/ • http://www.pptsearchengine.net/ • www.4shared.com • http://8085projects.info/ • http://80864beginner.com/ • www.eazynotes.com • www.slideshare.net • www.scribd.com • www.docstoc.com • www.slideworld.com • www.nptel.ac.in • http://opencourses.emu.edu.tr/ • http://engineeringppt.blogspot.in/ • http://www.pptsearchengine.net/ • www.4shared.com • http://8085projects.info/ 439

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NPTEL Lecture Materials References • Microprocessor and Peripheral Devices by Dr. Pramod Agarwal IIT Roorkee Link: http://nptel.ac.in/courses/108107029/ • Microprocessors and Microcontrollers by Prof. Krishna Kumar IISc Bangalore link: http://nptel.ac.in/courses/106108100/ • Microprocessor and Peripheral Devices by Dr. Pramod Agarwal IIT Roorkee Link: http://nptel.ac.in/courses/108107029/ • Microprocessors and Microcontrollers by Prof. Krishna Kumar IISc Bangalore link: http://nptel.ac.in/courses/106108100/ 440

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Microcontrollers Introduction EC6504 Microprocessors and Microcontrollers Dept: CSEITECEMECH Regulation : R2013 441 Microcontrollers Introduction Presented by C.GOKULAP/EEE

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CPU for Computers No RAM ROM I/O on CPU chip itself Example: Intels x86 Motorolas 680x0 442

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A smaller computer On-chip RAM ROM I/O ports... Example: Motorolas 6811 Intels 8051 Zilogs Z8 and PIC 443 A smaller computer On-chip RAM ROM I/O ports... Example: Motorolas 6811 Intels 8051 Zilogs Z8 and PIC

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Microprocessor CPU is stand-alone RAM ROM I/O timer are separate Designer can decide on the amount of ROM RAM and I/O ports. Expansive General-purpose Microcontroller CPU RAM ROM I/O and timer are all on a single chip Fix amount of on-chip ROM RAM I/O ports For applications in which cost power and space are critical Not Expansive Single-purpose 444 Microprocessor CPU is stand-alone RAM ROM I/O timer are separate Designer can decide on the amount of ROM RAM and I/O ports. Expansive General-purpose Microcontroller CPU RAM ROM I/O and timer are all on a single chip Fix amount of on-chip ROM RAM I/O ports For applications in which cost power and space are critical Not Expansive Single-purpose

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Home Appliances intercom telephones security systems garage door openers answering machines fax machines home computers TVs cable TV tuner VCR camcorder remote controls video games cellular phones musical instruments sewing machines lighting control paging camera pinball machines toys exercise equipment etc. Office Telephones computers security systems fax machines microwave copier laser printer color printer paging etc. Auto Trip computer engine control air bag ABS instrumentation security system transmission control entertainment climate control cellular phone keyless entry 445 Home Appliances intercom telephones security systems garage door openers answering machines fax machines home computers TVs cable TV tuner VCR camcorder remote controls video games cellular phones musical instruments sewing machines lighting control paging camera pinball machines toys exercise equipment etc. Office Telephones computers security systems fax machines microwave copier laser printer color printer paging etc. Auto Trip computer engine control air bag ABS instrumentation security system transmission control entertainment climate control cellular phone keyless entry

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446

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EC6504 Microprocessors and Microcontrollers Dept: CSEITECEMECH 447

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8051 CPU Operation 1. Features 2. Pin Diagram 3. Block Diagram 1. Features 2. Pin Diagram 3. Block Diagram 448

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8051 Microcontroller Intel introduced 8051 developed in the year 1981. The 8051 is an 8-bit processor The CPU can work on only 8 bits of data at a time The 8051 became widely popular after allowing other manufactures to make and market any flavor of the 8051. Intel introduced 8051 developed in the year 1981. The 8051 is an 8-bit processor The CPU can work on only 8 bits of data at a time The 8051 became widely popular after allowing other manufactures to make and market any flavor of the 8051. 449

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8051 Family The 8051 is a subset of the 8052 The 8031 is a ROM-less 8051 Add external ROM to it You lose two ports and leave only 2 ports for I/O operations 450

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8051 Features 64KB Program Memory address space 64KB Data Memory address space 4K bytes of on-chip Program Memory 128 bytes of on-chip Data RAM 32 bidirectional and individually addressable I/0 lines Two 16-bit timer/counters 6-source/5-vector interrupt structure with two priority levels On-chip clock oscillator 64KB Program Memory address space 64KB Data Memory address space 4K bytes of on-chip Program Memory 128 bytes of on-chip Data RAM 32 bidirectional and individually addressable I/0 lines Two 16-bit timer/counters 6-source/5-vector interrupt structure with two priority levels On-chip clock oscillator 451

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Pin Description of the 8051 8051 family memberse.g. 8751 89C51 89C52 DS89C4x0 Have 40 pins dedicated for various functions such as I/O RD WR address data and interrupts. DIPdual in-line package Some companies provide a 20-pin version of the 8051 with a reduced number of I/O ports for less demanding applications 8051 family memberse.g. 8751 89C51 89C52 DS89C4x0 Have 40 pins dedicated for various functions such as I/O RD WR address data and interrupts. DIPdual in-line package Some companies provide a 20-pin version of the 8051 with a reduced number of I/O ports for less demanding applications 452

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Pin Diagram of the 8051 453

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XTAL1 and XTAL2 The 8051 has an on-chip oscillator but requires an external clock to run it A quartz crystal oscillator is connected to inputs XTAL1 pin19 and XTAL2 pin18 The quartz crystal oscillator also needs two capacitors of 30 pF value The 8051 has an on-chip oscillator but requires an external clock to run it A quartz crystal oscillator is connected to inputs XTAL1 pin19 and XTAL2 pin18 The quartz crystal oscillator also needs two capacitors of 30 pF value 454

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XTAL1 and XTAL2 .. If you use a frequency source other than a crystal oscillator such as a TTL oscillator: It will be connected to XTAL1 XTAL2 is left unconnected 455

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XTAL1 and XTAL2 .. The speed of 8051 refers to the maximum oscillator frequency connected to XTAL. We can observe the frequency on the XTAL2 pin using the oscilloscope. The speed of 8051 refers to the maximum oscillator frequency connected to XTAL. We can observe the frequency on the XTAL2 pin using the oscilloscope. 456

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RST RESET pin is an input and is active highnormally low Upon applying a high pulse to this pin the microcontroller will reset and terminate all activities 457

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EA EAexternal access is an input pin and must be connected to Vcc or GND Normally EA pin is connected to Vcc EA pin must be connected to GND to indicate that the code or data is stored externally. EAexternal access is an input pin and must be connected to Vcc or GND Normally EA pin is connected to Vcc EA pin must be connected to GND to indicate that the code or data is stored externally. 458

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PSEN and ALE PSENprogram store enable is an output pin This pin is connected to the OE pin of the external memory. For External Code Memory PSEN 0 For External Data Memory PSEN 1 ALE pin is used for demultiplexing the address and data. PSENprogram store enable is an output pin This pin is connected to the OE pin of the external memory. For External Code Memory PSEN 0 For External Data Memory PSEN 1 ALE pin is used for demultiplexing the address and data. 459

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I/O Port Pins The four 8-bit I/O ports P0 P1 P2 and P3 each uses 8 pins. 460

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Port 0 Port 0 is also designated as AD0-AD7. When connecting an 8051 to an external memory port 0 provides both address and data. The 8051 multiplexes address and data through port 0 to save pins. ALE indicates if P0 has address or data. When ALE0 it provides data D0-D7 When ALE1 it has address A0-A7 Port 0 is also designated as AD0-AD7. When connecting an 8051 to an external memory port 0 provides both address and data. The 8051 multiplexes address and data through port 0 to save pins. ALE indicates if P0 has address or data. When ALE0 it provides data D0-D7 When ALE1 it has address A0-A7 461

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Port 1 and Port 2 In 8051-based systems with no external memory connection: Both P1 and P2 are used as simple I/O. In 8051-based systems with external memory connections: Port 2 must be used along with P0 to provide the 16-bit address for the external memory. P0 provides the lower 8 bits via A0 A7. P2 is used for the upper 8 bits of the 16-bit address designated as A8 A15 and it cannot be used for I/O. In 8051-based systems with no external memory connection: Both P1 and P2 are used as simple I/O. In 8051-based systems with external memory connections: Port 2 must be used along with P0 to provide the 16-bit address for the external memory. P0 provides the lower 8 bits via A0 A7. P2 is used for the upper 8 bits of the 16-bit address designated as A8 A15 and it cannot be used for I/O. 462

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Port 3 Port 3 can be used as input or output. Port 3 has the additional function of providing some extremely important signals Port 3 can be used as input or output. Port 3 has the additional function of providing some extremely important signals 463

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Pin Description Summary PIN TYPE NAME AND FUNCTION Vss I Ground: 0 V reference. Vcc I Power Supply: This is the power supply voltage for normal idle and power-down operation. P0.0 - P0.7 I/O Port 0: Port 0 is an open-drain bi-directional I/O port. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. Port 0: Port 0 is an open-drain bi-directional I/O port. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. P1.0 - P1.7 I/O Port 1: Port I is an 8-bit bi-directional I/O port. P2.0 - P2.7 I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses. P3.0 - P3.7 I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also serves special features as explained. 464

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Pin Description Summary PIN TYPE NAME AND FUNCTION RST I Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. ALE O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. PSEN O Program Store Enable: The read strobe to external program memory. When executing code from the external program memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory. Program Store Enable: The read strobe to external program memory. When executing code from the external program memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory. EA/VPP I External Access Enable/Programming Supply Voltage: Vpp pin also receives the programming supply voltage Vpp during Flash programming.applies for 89c5x MCUs 465

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Interrupt Control CPU 4K ROM 128 B RAM Timer 1 Timer 0 General Block Diagram of 8051 CPU OSC Bus Control 4 I/O Ports Serial Port TXD RXD P0 P1 P2 P3 466

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Detailed Block Diagram 467

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8051 Memory Space 8051 Memory Space 468

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8051 Memory Structure External External 64K 64K 60K External EXT INT 128 SFR External Program Memory Data Memory 64K 64K EA 0 EA 1 4K 469

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Internal RAM Structure Direct Addressing Only SFR Special Function Registers Direct Indirect Addressing SFR Special Function Registers 128 Byte Internal RAM 470

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Special Function Register SFR Special Function Register SFR 471

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Special Function Registers SFR Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode 472

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SFR Registers their Addresses MOV MOV 0E0H55H 0E0H55H is the same as is the same as MOV MOV A55H A55H which means load 55H into A A55H which means load 55H into A A55H MOV MOV 0F0H25H 0F0H25H is the same as is the same as MOV B25H MOV B25H which means load 25H into B B25H which means load 25H into B B25H MOV MOV 0E0HR2 0E0HR2 is the same as is the same as MOV MOV AR2 AR2 which means copy R2 into A which means copy R2 into A MOV MOV 0F0HR0 0F0HR0 is the same as is the same as MOV MOV BR0 BR0 which means copy R0 into B which means copy R0 into B MOV MOV 0E0H55H 0E0H55H is the same as is the same as MOV MOV A55H A55H which means load 55H into A A55H which means load 55H into A A55H MOV MOV 0F0H25H 0F0H25H is the same as is the same as MOV B25H MOV B25H which means load 25H into B B25H which means load 25H into B B25H MOV MOV 0E0HR2 0E0HR2 is the same as is the same as MOV MOV AR2 AR2 which means copy R2 into A which means copy R2 into A MOV MOV 0F0HR0 0F0HR0 is the same as is the same as MOV MOV BR0 BR0 which means copy R0 into B which means copy R0 into B 473

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SFR Addresses 1 of 2 474

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SFR Addresses 2 of 2 475

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Example 476

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Program Status Word PSW C AC F0 RS1 RS0 OV F1 P Carry Parity Register Bank Select Carry Auxiliary Carry User Flag 0 Parity User Flag 1 Overflow 477

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8051 instructions that affects flag 478

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128 Byte RAM There are 128 bytes of RAM in the 8051. Assigned addresses 00 to 7FH The 128 bytes are divided into 3 different groups as follows: 1. A total of 32 bytes from locations 00 to 1F hex are set aside for register banks and the stack. 2. A total of 16 bytes from locations 20H to 2FH are set aside for bit-addressable read/write memory. 3. A total of 80 bytes from locations 30H to 7FH are used for read and write storage called scratch pad. BIT Addressable Area General Purpose Area There are 128 bytes of RAM in the 8051. Assigned addresses 00 to 7FH The 128 bytes are divided into 3 different groups as follows: 1. A total of 32 bytes from locations 00 to 1F hex are set aside for register banks and the stack. 2. A total of 16 bytes from locations 20H to 2FH are set aside for bit-addressable read/write memory. 3. A total of 80 bytes from locations 30H to 7FH are used for read and write storage called scratch pad. 128 BYTE INTERNAL RAM Register Banks Reg Bank 0 Reg Bank 1 Reg Bank 2 Reg Bank 3 BIT Addressable Area 479

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8051 RAM with addresses 480

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8051 Register Bank Structure R0 R1 R2 R3 R4 R5 R6 R7 Bank 3 R0 R1 R2 R3 R4 R5 R6 R7 Bank 2 Bank 0 R0 R1 R2 R3 R4 R5 R6 R7 Bank 2 R0 R1 R2 R3 R4 R5 R6 R7 Bank 1 R0 R1 R2 R3 R4 R5 R6 R7 481

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8051 Register Banks with address 482

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8051 Programming Model 483

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8051 Stack The stack is a section of RAM used by the CPU to store information temporarily. This information could be data or an address The register used to access the stack is called the SP stack pointer register The stack pointer in the 8051 is only 8 bit wide which means that it can take value of 00 to FFH The stack is a section of RAM used by the CPU to store information temporarily. This information could be data or an address The register used to access the stack is called the SP stack pointer register The stack pointer in the 8051 is only 8 bit wide which means that it can take value of 00 to FFH 484

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8051 Stack The storing of a CPU register in the stack is called a PUSH SP is pointing to the last used location of the stack As we push data onto the stack the SP is incremented by one This is different from many microprocessors Loading the contents of the stack back into a CPU register is called a POP With every pop the top byte of the stack is copied to the register specified by the instruction and the stack pointer is decremented once The storing of a CPU register in the stack is called a PUSH SP is pointing to the last used location of the stack As we push data onto the stack the SP is incremented by one This is different from many microprocessors Loading the contents of the stack back into a CPU register is called a POP With every pop the top byte of the stack is copied to the register specified by the instruction and the stack pointer is decremented once 485

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INSTRUCTION SET OF 8051 INSTRUCTION SET OF 8051 486

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8051 Instruction Set The instructions are grouped into 5 groups Arithmetic Logic Data Transfer Boolean Branching The instructions are grouped into 5 groups Arithmetic Logic Data Transfer Boolean Branching 487

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1. Arithmetic Instructions ADD 8-bit addition between the accumulator A and a second operand. The result is always in the accumulator. The CY flag is set/reset appropriately. ADDC 8-bit addition between the accumulator a second operand and the previous value of the CY flag. ADD 8-bit addition between the accumulator A and a second operand. The result is always in the accumulator. The CY flag is set/reset appropriately. ADDC 8-bit addition between the accumulator a second operand and the previous value of the CY flag. 488

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ADD Instruction ADD A source ADD the source operand to the accumulator MOV A 03H load 03H into A MOV B02H load 02H into B ADD AB add B register to accumulator A A + B 05 ADD A source ADD the source operand to the accumulator MOV A 03H load 03H into A MOV B02H load 02H into B ADD AB add B register to accumulator A A + B 05 489

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SUBB Subtract with Borrow. A A - operand - CY. The result is always saved in the accumulator. The CY flag is set/reset appropriately. SUBB Subtract with Borrow. A A - operand - CY. The result is always saved in the accumulator. The CY flag is set/reset appropriately. 490

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SUBB Instruction SUBB A source ADD the source operand to the accumulator MOV A 03H load 03H into A MOV B02H load 02H into B SUBB AB add B register to accumulator A A - B 01 SUBB A source ADD the source operand to the accumulator MOV A 03H load 03H into A MOV B02H load 02H into B SUBB AB add B register to accumulator A A - B 01 491

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INC Increment the operand by one. Ex: INC DPTR The operand can be a register a direct address an indirect address the data pointer. DEC Decrement the operand by one. Ex: DEC B The operand can be a register a direct address an indirect address. MUL AB / DIV AB Multiply A by B and place result in A:B. Divide A by B and place result in A:B. INC Increment the operand by one. Ex: INC DPTR The operand can be a register a direct address an indirect address the data pointer. DEC Decrement the operand by one. Ex: DEC B The operand can be a register a direct address an indirect address. MUL AB / DIV AB Multiply A by B and place result in A:B. Divide A by B and place result in A:B. 492

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Multiplication of Numbers MUL AB A B place 16-bit result in B and A MOV A05 MOV A05 load 05H to reg. A load 05H to reg. A MOV B03 MOV B03 load 03H in reg. B load 03H in reg. B MUL AB MUL AB 05 03 000F where 05 03 000F where B 00 B 00 and and A 0F A 0F Table 6-1:Unsigned Multiplication Summary MUL AB Multiplication Operand 1 Operand 2 Result byte byte A B Alow byte Bhigh byte 493

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Division of Numbers MOV A MOV A05 05 load load 05H 05H to reg. A to reg. A MOV B MOV B03 03 load load 03H 03H in reg. B in reg. B DIV AB 05/03 Quotient DIV AB 05/03 Quotient 01 01Reminder Reminder 02 02 where where B B 02 02 and and A A 01 01 Table 6-2:Unsigned Division Summary DIV AB Division Numerator Denominator Quotient Remainder byte / byte A B A B MOV A MOV A05 05 load load 05H 05H to reg. A to reg. A MOV B MOV B03 03 load load 03H 03H in reg. B in reg. B DIV AB 05/03 Quotient DIV AB 05/03 Quotient 01 01Reminder Reminder 02 02 where where B B 02 02 and and A A 01 01 494

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ADD ARn A A+ memory pointed to Rn DA A Decimal Adjust A BCD addition ADDC ARn SUBB ARn INC Ri ADD ARn A A+ memory pointed to Rn DA A Decimal Adjust A BCD addition ADDC ARn SUBB ARn INC Ri 495

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2. Logical instructions 2. Logical instructions 496

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ANL DS -Performs logical AND of destination source -Destination : A/memory -Source : data/register/memory - Eg: ANL A0FH ANL AR5 ORL DS -Performs logical OR of destination source -Destination : A/memory -Source : data/register/memory - Eg: ORL A28H ORL AR0 497 ANL DS -Performs logical AND of destination source -Destination : A/memory -Source : data/register/memory - Eg: ANL A0FH ANL AR5 ORL DS -Performs logical OR of destination source -Destination : A/memory -Source : data/register/memory - Eg: ORL A28H ORL AR0

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XRL DS -Performs logical XOR of destination source -Destination : A/memory -Source : data/register/memory - Eg: XRL A28H XRL AR0 • CPL A -Compliment accumulator -gives 1’s compliment of accumulator data • SWAP A -Exchange the upper lower nibbles of accumulator 498 XRL DS -Performs logical XOR of destination source -Destination : A/memory -Source : data/register/memory - Eg: XRL A28H XRL AR0 • CPL A -Compliment accumulator -gives 1’s compliment of accumulator data • SWAP A -Exchange the upper lower nibbles of accumulator

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RL A -Rotate data of accumulator towards left without carry RLC A - Rotate data of accumulator towards left with carry RR A -Rotate data of accumulator towards right without carry RRC A - Rotate data of accumulator towards right with carry RL A -Rotate data of accumulator towards left without carry RLC A - Rotate data of accumulator towards left with carry RR A -Rotate data of accumulator towards right without carry RRC A - Rotate data of accumulator towards right with carry 499

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3. Data Transfer Instructions 3. Data Transfer Instructions 500

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MOV Instruction MOV destination source copy source to destination. MOV A55H load value 55H into reg. A MOV R0A copy contents of A into R0 now AR055H MOV R1A copy contents of A into R1 now AR0R155H MOV R2A copy contents of A into R2 now AR0R1R255H MOV R395H load value 95H into R3 now R395H MOV AR3 copy contents of R3 into A now AR395H MOV destination source copy source to destination. MOV A55H load value 55H into reg. A MOV R0A copy contents of A into R0 now AR055H MOV R1A copy contents of A into R1 now AR0R155H MOV R2A copy contents of A into R2 now AR0R1R255H MOV R395H load value 95H into R3 now R395H MOV AR3 copy contents of R3 into A now AR395H 501

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MOVX Data transfer between the accumulator and a byte from external data memory. MOVX A Ri MOVX A DPTR MOVX Ri A MOVX DPTR A MOVX Data transfer between the accumulator and a byte from external data memory. MOVX A Ri MOVX A DPTR MOVX Ri A MOVX DPTR A Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode 502

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PUSH / POP Push and Pop a data byte onto the stack. The data byte is identified by a direct address from the internal RAM locations. PUSH DPL POP 40H PUSH / POP Push and Pop a data byte onto the stack. The data byte is identified by a direct address from the internal RAM locations. PUSH DPL POP 40H 503

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XCH Exchange accumulator and a byte variable XCH A Rn XCH A direct XCH A Ri XCH Exchange accumulator and a byte variable XCH A Rn XCH A direct XCH A Ri 504

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4.Boolean variable instructions 4.Boolean variable instructions 505

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CLR: The operation clears the specified bit indicated in the instruction Ex: CLR C clear the carry SETB: The operation sets the specified bit to 1. CPL: The operation complements the specified bit indicated in the instruction CLR: The operation clears the specified bit indicated in the instruction Ex: CLR C clear the carry SETB: The operation sets the specified bit to 1. CPL: The operation complements the specified bit indicated in the instruction 506

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ANL CSource-bit -Performs AND bit addressed with the carry bit. - Eg: ANL CP2.7 AND carry flag with bit 7 of P2 ORL CSource-bit -Performs OR bit addressed with the carry bit. - Eg: ORL CP2.1 OR carry flag with bit 1 of P2 507 ANL CSource-bit -Performs AND bit addressed with the carry bit. - Eg: ANL CP2.7 AND carry flag with bit 7 of P2 ORL CSource-bit -Performs OR bit addressed with the carry bit. - Eg: ORL CP2.1 OR carry flag with bit 1 of P2

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XORL CSource-bit -Performs XOR bit addressed with the carry bit. - Eg: XOL CP2.1 OR carry flag with bit 1 of P2 MOV P2.3C MOV CP3.3 MOV P2.0C XORL CSource-bit -Performs XOR bit addressed with the carry bit. - Eg: XOL CP2.1 OR carry flag with bit 1 of P2 MOV P2.3C MOV CP3.3 MOV P2.0C 508

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5. Branching instructions 5. Branching instructions 509

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Program branching instructions are used to control the flow of actions in a program Some instructions provide decision making capabilities and transfer control to other parts of the program. e.g. conditional and unconditional branches Program branching instructions are used to control the flow of actions in a program Some instructions provide decision making capabilities and transfer control to other parts of the program. e.g. conditional and unconditional branches 510

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Jump Instructions All conditional jumps are short jumps Target address within -128 to +127 of PC LJMPlong jump: 3-byte instruction 2-byte target address: 0000 to FFFFH Original 8051 has only 4KB on-chip ROM SJMPshort jump: 2-byte instruction 1-byte relative address: -128 to +127 All conditional jumps are short jumps Target address within -128 to +127 of PC LJMPlong jump: 3-byte instruction 2-byte target address: 0000 to FFFFH Original 8051 has only 4KB on-chip ROM SJMPshort jump: 2-byte instruction 1-byte relative address: -128 to +127 511

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Call Instructions LCALLlong call: 3-byte instruction 2-byte address Target address within 64K-byte range ACALLabsolute call: 2-byte instruction 11-bit address Target address within 2K-byte range LCALLlong call: 3-byte instruction 2-byte address Target address within 64K-byte range ACALLabsolute call: 2-byte instruction 11-bit address Target address within 2K-byte range 512

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The 8051 provides 2 forms for the return instruction: Return from subroutine RET Return from ISR RETI 513

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514

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8051 Addressing Modes 8051 Addressing Modes 515

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8051 Addressing Modes The CPU can access data in various ways which are called addressing modes 1. Immediate 2. Register 3. Direct 4. Register indirect 5. External Direct The CPU can access data in various ways which are called addressing modes 1. Immediate 2. Register 3. Direct 4. Register indirect 5. External Direct 516

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1. Immediate Addressing Mode The source operand is a constant. The immediate data must be preceded by the pound sign Can load information into any registers including 16-bit DPTR register DPTR can also be accessed as two 8-bit registers the high byte DPH and low byte DPL The source operand is a constant. The immediate data must be preceded by the pound sign Can load information into any registers including 16-bit DPTR register DPTR can also be accessed as two 8-bit registers the high byte DPH and low byte DPL 517

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2. Register Addressing Mode Use registers to hold the data to be manipulated. • The source and destination registers must match in size. MOV DPTRA will give an error • The source and destination registers must match in size. MOV DPTRA will give an error • The movement of data between Rn registers is not allowed MOV R4R7 is invalid 518

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3. Direct Addressing Mode It is most often used the direct addressing mode to access RAM locations 30 7FH. The entire 128 bytes of RAM can be accessed. Contrast this with immediate addressing mode there is no sign in the operand. It is most often used the direct addressing mode to access RAM locations 30 7FH. The entire 128 bytes of RAM can be accessed. Contrast this with immediate addressing mode there is no sign in the operand. 519

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Stack and Direct Addressing Mode Only direct addressing mode is allowed for pushing or popping the stack. PUSH A is invalid. Pushing the accumulator onto the stack must be coded as PUSH 0E0H. Only direct addressing mode is allowed for pushing or popping the stack. PUSH A is invalid. Pushing the accumulator onto the stack must be coded as PUSH 0E0H. 520

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4. Register Indirect Addressing Mode A register is used as a pointer to the data. Only register R0 and R1 are used for this purpose. R2 R7 cannot be used to hold the address of an operand located in RAM. When R0 and R1 hold the addresses of RAM locations they must be preceded by the sign. A register is used as a pointer to the data. Only register R0 and R1 are used for this purpose. R2 R7 cannot be used to hold the address of an operand located in RAM. When R0 and R1 hold the addresses of RAM locations they must be preceded by the sign. 521

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Register Indirect Addressing Mode Write a program to copy the value 55H into RAM memory locations 40H to 41H usinga direct addressing modeb register indirect addressing mode without a loop andc with a loop. 522

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Register Indirect Addressing Mode The advantage is that it makes accessing data dynamic rather than static as in direct addressing mode. Looping is not possible in direct addressing mode. Write a program to clear 16 RAM locations starting at RAM address 60H. The advantage is that it makes accessing data dynamic rather than static as in direct addressing mode. Looping is not possible in direct addressing mode. Write a program to clear 16 RAM locations starting at RAM address 60H. 523

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5. External Direct External Memory is accessed. There are only two commands that use External Direct addressing mode: MOVX A DPTR MOVX DPTR A DPTR must first be loaded with the address of external memory. External Memory is accessed. There are only two commands that use External Direct addressing mode: MOVX A DPTR MOVX DPTR A DPTR must first be loaded with the address of external memory. 524

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8051 Assembly Language ProgrammingALP 8051 Assembly Language ProgrammingALP 525

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ADDITION OF TWO 8 bit Numbers ADDRESS LABEL MNEMONICS 9100 START CLR C MOV R0 00 MOV A05 MOV B03 ADD AB ADD AB MOV DPTR9200 JNC AHEAD INC R0 AHEAD MOV X DPTRA INC DPTR MOV AR0 MOV X DPTRA HERE SJMP HERE 526

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SUBTRACTION OF TWO 8 bit Numbers ADDRESS LABEL MNEMONICS 9100 START CLR C MOV R0 00 MOV A05 MOV B03 SUBB AB SUBB AB MOV DPTR9200 JNC AHEAD INC R0 AHEAD MOV X DPTRA INC DPTR MOV AR0 MOV X DPTRA HERE SJMP HERE 527

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Multiplication Concept MUL AB A B place 16-bit result in B and A MOV A25H MOV A25H load 25H to reg. A load 25H to reg. A MOV B65H MOV B65H load 65H in reg. B load 65H in reg. B MUL AB MUL AB 25H 65H E99 where B 0EH and A 99H 25H 65H E99 where B 0EH and A 99H Table 6-1:Unsigned Multiplication Summary MUL AB Multiplication Operand 1 Operand 2 Result byte byte A B Alow byte Bhigh byte 528

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Division Concept DIV AB divide A by B MOV A95H load 95 into A MOV B10H load 10 into B DIV AB now A 09 quotient and B 05 remainder DIV AB divide A by B MOV A95H load 95 into A MOV B10H load 10 into B DIV AB now A 09 quotient and B 05 remainder Table 6-2:Unsigned Division Summary DIV AB Division Numerator Denominator Quotient Remainder byte / byte A B A B 529

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MULTIPLICATION OF TWO 8 bit Numbers Address Label Mnemonics 9000 START MOV A05 MOV F003 MUL AB MOV DPTR9200 Address Label Mnemonics 9000 START MOV A05 MOV F003 DIV AB MOV DPTR9200 DIVISION OF TWO 8 bit Numbers MOV DPTR9200 MOVX DPTRA INC DPTR MOV AF0 MOVX DPTRA HERE SJMP HERE MOV DPTR9200 MOVX DPTRA INC DPTR MOV AF0 MOVX DPTRA HERE SJMP HERE 530

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MOV 40H 05H store I st number in location 40H MOV 41H 04H MOV 42H 03H MOV 43H 02H MOV 44H 01H MOV R0 40H store I st number address 40H in R0 MOV R5 05H store the number 05H in R5 MOV BR5 store the number 05H in B CLR A Clear Acc LOOP: ADD AR0 INC R0 DJNZ R5LOOP DIV AB MOV 55HA Save the quotient in location 55H END Average of Fiveor N 8 bit Numbers MOV 40H 05H store I st number in location 40H MOV 41H 04H MOV 42H 03H MOV 43H 02H MOV 44H 01H MOV R0 40H store I st number address 40H in R0 MOV R5 05H store the number 05H in R5 MOV BR5 store the number 05H in B CLR A Clear Acc LOOP: ADD AR0 INC R0 DJNZ R5LOOP DIV AB MOV 55HA Save the quotient in location 55H END 531

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Checking an input bit JNB jump if no bit JB jump if bit 1 532

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Switch Register Banks 533

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Pushing onto Stack 534

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Popping from Stack 535

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Looping 536

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Loop inside a Loop Nested Loop 537

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Conditional Jump Example 538

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Conditional Jump Example 539

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EC6504 Microprocessors and Microcontrollers Dept: CSEITECEMECH 540 Presented by C.GOKULAP/EEE

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8051 TIMERS 8051 TIMERS 541

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8051 Timer/Counter OSC ÷12 TLx 8 Bit / 0 C T / 1 C T T PIN THx 8 Bit TFx 1 Bit INT PIN Gate TR T PIN INTERRUPT 542

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TMOD Register GATE: When set timer/counter x is enabled if INTx pin is high and TRx is set. When cleared timer/counter x is enabled if TRx bit set. C/T: When set counter operation input from Tx input pin. When cleared timer operation input from internal clock. GATE: When set timer/counter x is enabled if INTx pin is high and TRx is set. When cleared timer/counter x is enabled if TRx bit set. C/T: When set counter operation input from Tx input pin. When cleared timer operation input from internal clock. 543

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TMOD Register The TMOD byte is not bit addressable. 544

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TCON Register 545

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8051 Timer Modes Timer 0 Mode 0 Mode 0 Timer 1 8051 TIMERS Mode 3 Mode 2 Mode 1 Mode 0 Mode 2 Mode 1 Mode 0 546

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OSC ÷12 TL0 / 0 C T / 1 C T 0 T PIN TH0 TIMER 0 TF0 0 INT PIN Gate 0 TR 0 T PIN INTERRUPT 547

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TL0 5 Bit INTERRUPT TIMER 0 Mode 0 OSC ÷12 / 0 C T / 1 C T 0 T PIN TH0 8 Bit TF0 13 Bit Timer / Counter 0 INT PIN Gate 0 TR 0 T PIN Maximum Count 1FFFh 0001111111111111 548

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TL0 8 Bit INTERRUPT TIMER 0 Mode 1 OSC ÷12 / 0 C T / 1 C T 0 T PIN TH0 8 Bit TF0 16 Bit Timer / Counter 0 INT PIN Gate 0 TR 0 T PIN Maximum Count FFFFh 1111111111111111 549

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TIMER 0 Mode 2 8 Bit Timer / Counter with AUTORELOAD TL0 8 Bit OSC ÷12 / 0 C T / 1 C T 0 T PIN TH0 8 Bit TF0 INTERRUPT TH0 8 Bit Reload 0 INT PIN Gate 0 TR 0 T PIN Maximum Count FFh 11111111 550

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TL0 8 Bit INTERRUPT TIMER 0 Mode 3 OSC ÷12 / 0 C T / 1 C T 0 TR 0 T PIN TF0 Two - 8 Bit Timer / Counter 0 INT PIN Gate OSC ÷12 1 TR TH0 8 Bit INTERRUPT TF1 551

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OSC ÷12 TL1 / 0 C T / 1 C T TH1 INTERRUPT TIMER 1 TF1 1 T PIN Gate INTERRUPT 1 INT PIN 1 TR 1 T PIN 552

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TL1 5 Bit INTERRUPT TIMER 1 Mode 0 OSC ÷12 / 0 C T / 1 C T TH1 8 Bit TF1 13 Bit Timer / Counter 1 T PIN Gate Maximum Count 1FFFh 0001111111111111 1 INT PIN 1 TR 1 T PIN 553

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TL1 8 Bit INTERRUPT TIMER 1 Mode 1 OSC ÷12 / 0 C T / 1 C T TH1 8 Bit TF1 16 Bit Timer / Counter 1 T PIN Gate Maximum Count FFFFh 1111111111111111 1 INT PIN 1 TR 1 T PIN 554

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TIMER 1 Mode 2 8 Bit Timer / Counter with AUTORELOAD TL1 8 Bit OSC ÷12 / 0 C T / 1 C T TH1 8 Bit TF1 INTERRUPT 1 T PIN TH1 8 Bit Reload Gate Maximum Count FFh 11111111 1 INT PIN 1 TR 1 T PIN 555

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Programming Timers Example: Indicate which mode and which timer are selected for each of the following. a MOV TMOD 01Hb MOV TMOD 20Hc MOV TMOD 12H Solution: We convert the value from hex to binary. a TMOD 00000001 mode 1 of timer 0 is selected. b TMOD 00100000 mode 2 of timer 1 is selected. c TMOD 00010010 mode 2 of timer 0 and mode 1 of timer 1 are selected. Example: Indicate which mode and which timer are selected for each of the following. a MOV TMOD 01Hb MOV TMOD 20Hc MOV TMOD 12H Solution: We convert the value from hex to binary. a TMOD 00000001 mode 1 of timer 0 is selected. b TMOD 00100000 mode 2 of timer 1 is selected. c TMOD 00010010 mode 2 of timer 0 and mode 1 of timer 1 are selected. 556

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Programming Timers Find the timers clock frequency and its period for various 8051-based system with the crystal frequency 11.0592 MHz when C/T bit of TMOD is 0. Solution: Find the timers clock frequency and its period for various 8051-based system with the crystal frequency 11.0592 MHz when C/T bit of TMOD is 0. Solution: 1/12 × 11.0529 MHz 921.6 MHz T 1/921.6 kHz 1.085 us 557

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558 Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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8051 Serial Port 8051 Serial Port 559

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Basics of Serial Communication Computers transfer data in two ways: Parallel: Often 8 or more lineswire conductors are used to transfer data to a device that is only a few feet away. Serial: To transfer to a device located many meters away the serial method is used. The data is sent one bit at a time. Computers transfer data in two ways: Parallel: Often 8 or more lineswire conductors are used to transfer data to a device that is only a few feet away. Serial: To transfer to a device located many meters away the serial method is used. The data is sent one bit at a time. 560

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Basics of Serial Communication Serial data communication uses two methods Synchronous method transfers a block of data at a time Asynchronous method transfers a single byte at a time There are special ICs made by many manufacturers for serial communications. UARTuniversal asynchronous Receiver transmitter USARTuniversal synchronous-asynchronous Receiver- transmitter Serial data communication uses two methods Synchronous method transfers a block of data at a time Asynchronous method transfers a single byte at a time There are special ICs made by many manufacturers for serial communications. UARTuniversal asynchronous Receiver transmitter USARTuniversal synchronous-asynchronous Receiver- transmitter 561

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Asynchronous Start Stop Bit Asynchronous serial data communication is widely used for character-oriented transmissions Each character is placed in between start and stop bits this is called framing. Block-oriented data transfers use the synchronous method. The start bit is always one bit but the stop bit can be one or two bits The start bit is always a 0 low and the stop bits is 1 high Asynchronous serial data communication is widely used for character-oriented transmissions Each character is placed in between start and stop bits this is called framing. Block-oriented data transfers use the synchronous method. The start bit is always one bit but the stop bit can be one or two bits The start bit is always a 0 low and the stop bits is 1 high 562

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Asynchronous Start Stop Bit 563

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Data Transfer Rate The rate of data transfer in serial data communication is stated in bpsbits per second. Another widely used terminology for bps is baud rate. It is modem terminology and is defined as the number of signal changes per second In modems there are occasions when a single change of signal transfers several bits of data As far as the conductor wire is concerned the baud rate and bps are the same. The rate of data transfer in serial data communication is stated in bpsbits per second. Another widely used terminology for bps is baud rate. It is modem terminology and is defined as the number of signal changes per second In modems there are occasions when a single change of signal transfers several bits of data As far as the conductor wire is concerned the baud rate and bps are the same. 564

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8051 Serial Port Synchronous and Asynchronous SCON Register is used to Control Data Transfer through TXd RXd pins Some time - Clock through TXd Pin Four Modes of Operation: Synchronous and Asynchronous SCON Register is used to Control Data Transfer through TXd RXd pins Some time - Clock through TXd Pin Four Modes of Operation: Mode 0 :Synchronous Serial Communication Mode 1 :8-Bit UART with Timer Data Rate Mode 2 :9-Bit UART with Set Data Rate Mode 3 :9-Bit UART with Timer Data Rate 565

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Registers related to Serial Communication 1. SBUF Register 2. SCON Register 3. PCON Register 1. SBUF Register 2. SCON Register 3. PCON Register 566

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SBUF Register SBUF is an 8-bit register used solely for serial communication. For a byte data to be transferred via the TxD line it must be placed in the SBUF register. The moment a byte is written into SBUF it is framed with the start and stop bits and transferred serially via the TxD line. SBUF holds the byte of data when it is received by 8051 RxD line. When the bits are received serially via RxD the 8051 deframes it by eliminating the stop and start bits making a byte out of the data received and then placing it in SBUF. SBUF is an 8-bit register used solely for serial communication. For a byte data to be transferred via the TxD line it must be placed in the SBUF register. The moment a byte is written into SBUF it is framed with the start and stop bits and transferred serially via the TxD line. SBUF holds the byte of data when it is received by 8051 RxD line. When the bits are received serially via RxD the 8051 deframes it by eliminating the stop and start bits making a byte out of the data received and then placing it in SBUF. 567

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SBUF Register Sample Program: 568

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SCON Register SM0 SM1 SM2 REN TB8 RB8 TI RI Set when a Cha- ractor received Enable Multiprocessor Communication Mode Set to Enable Serial Data reception 9 th Data Bit Sent in Mode 23 9 th Data Bit Received in Mode 23 Set when Stop bit Txed Set when a Cha- ractor received 569

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8051 Serial Port Mode 0 The Serial Port in Mode-0 has the following features: 1. Serial data enters and exits through RXD 2. TXD outputs the clock 3. 8 bits are transmitted / received 4. The baud rate is fixed at 1/12 of the oscillator frequency The Serial Port in Mode-0 has the following features: 1. Serial data enters and exits through RXD 2. TXD outputs the clock 3. 8 bits are transmitted / received 4. The baud rate is fixed at 1/12 of the oscillator frequency 570

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8051 Serial Port Mode 1 The Serial Port in Mode-1 has the following features: 1. Serial data enters through RXD 2. Serial data exits through TXD 3. On receive the stop bit goes into RB8 in SCON 4. 10 bits are transmitted / received 1. Start bit 0 2. Data bits 8 3. Stop Bit 1 5. Baud rate is determined by the Timer 1 over flow rate. The Serial Port in Mode-1 has the following features: 1. Serial data enters through RXD 2. Serial data exits through TXD 3. On receive the stop bit goes into RB8 in SCON 4. 10 bits are transmitted / received 1. Start bit 0 2. Data bits 8 3. Stop Bit 1 5. Baud rate is determined by the Timer 1 over flow rate. 571

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8051 Serial Port Mode 2 The Serial Port in Mode-2 has the following features: 1. Serial data enters through RXD 2. Serial data exits through TXD 3. 9th data bit TB8 can be assign value 0 or 1 4. On receive the 9th data bit goes into RB8 in SCON 5. 11 bits are transmitted / received 1.Start bit 0 2.Data bits 9 3.Stop Bit 1 6. Baud rate is programmable The Serial Port in Mode-2 has the following features: 1. Serial data enters through RXD 2. Serial data exits through TXD 3. 9th data bit TB8 can be assign value 0 or 1 4. On receive the 9th data bit goes into RB8 in SCON 5. 11 bits are transmitted / received 1.Start bit 0 2.Data bits 9 3.Stop Bit 1 6. Baud rate is programmable 572

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8051 Serial Port Mode 3 The Serial Port in Mode-3 has the following features: 1. Serial data enters through RXD 2. Serial data exits through TXD 3. 9th data bit TB8 can be assign value 0 or 1 4. On receive the 9th data bit goes into RB8 in SCON 5. 11 bits are transmitted / received 1.Start bit 0 2.Data bits 9 3.Stop Bit 1 6. Baud rate is determined by Timer 1 overflow rate. The Serial Port in Mode-3 has the following features: 1. Serial data enters through RXD 2. Serial data exits through TXD 3. 9th data bit TB8 can be assign value 0 or 1 4. On receive the 9th data bit goes into RB8 in SCON 5. 11 bits are transmitted / received 1.Start bit 0 2.Data bits 9 3.Stop Bit 1 6. Baud rate is determined by Timer 1 overflow rate. 573

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Programming Serial Data Transmission 1. TMOD register is loaded with the value 20H indicating the use of timer 1 in mode 28-bit auto-reload to set baud rate. 2. The TH1 is loaded with one of the values to set baud rate for serial data transfer. 3. The SCON register is loaded with the value 50H indicating serial mode 1 where an 8- bit data is framed with start and stop bits. 4. TR1 is set to 1 to start timer 1 5. TI is cleared by CLR TI instruction 6. The character byte to be transferred serially is written into SBUF register. 7. The TI flag bit is monitored with the use of instruction JNB TI xx to see if the character has been transferred completely. 8. To transfer the next byte go to step 5 1. TMOD register is loaded with the value 20H indicating the use of timer 1 in mode 28-bit auto-reload to set baud rate. 2. The TH1 is loaded with one of the values to set baud rate for serial data transfer. 3. The SCON register is loaded with the value 50H indicating serial mode 1 where an 8- bit data is framed with start and stop bits. 4. TR1 is set to 1 to start timer 1 5. TI is cleared by CLR TI instruction 6. The character byte to be transferred serially is written into SBUF register. 7. The TI flag bit is monitored with the use of instruction JNB TI xx to see if the character has been transferred completely. 8. To transfer the next byte go to step 5 574

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Programming Serial Data Reception 1. TMOD register is loaded with the value 20H indicating the use of timer 1 in mode 28-bit auto-reload to set baud rate. 2. TH1 is loaded to set baud rate 3. The SCON register is loaded with the value 50H indicating serial mode 1 where an 8- bit data is framed with start and stop bits. 4. TR1 is set to 1 to start timer 1 5. RI is cleared by CLR RI instruction 6. The RI flag bit is monitored with the use of instruction JNB RI xx to see if an entire character has been received yet 7. When RI is raised SBUF has the byte its contents are moved into a safe place. 8. To receive the next character go to step 5. 1. TMOD register is loaded with the value 20H indicating the use of timer 1 in mode 28-bit auto-reload to set baud rate. 2. TH1 is loaded to set baud rate 3. The SCON register is loaded with the value 50H indicating serial mode 1 where an 8- bit data is framed with start and stop bits. 4. TR1 is set to 1 to start timer 1 5. RI is cleared by CLR RI instruction 6. The RI flag bit is monitored with the use of instruction JNB RI xx to see if an entire character has been received yet 7. When RI is raised SBUF has the byte its contents are moved into a safe place. 8. To receive the next character go to step 5. 575

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Doubling Baud Rate There are two ways to increase the baud rate of data transfer 1. By using a higher frequency crystal 2. By changing a bit in the PCON register PCON register is an 8-bit register. There are two ways to increase the baud rate of data transfer 1. By using a higher frequency crystal 2. By changing a bit in the PCON register PCON register is an 8-bit register. •When 8051 is powered up SMOD is zero •We can set it to high by software and thereby double the baud rate. 576

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Doubling Baud Rate cont 577

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8051 Interrupts 8051 Interrupts 578

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INTERRUPTS An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service A single microcontroller can serve several devices by two ways: 1. Interrupt 2. Polling An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service A single microcontroller can serve several devices by two ways: 1. Interrupt 2. Polling 579

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Interrupt Vs Polling 1. Interrupts Whenever any device needs its service the device notifies the microcontroller by sending it an interrupt signal. Upon receiving an interrupt signal the microcontroller interrupts whatever it is doing and serves the device. The program which is associated with the interrupt is called the interrupt service routineISR or interrupt handler. 2. Polling The microcontroller continuously monitors the status of a given device. When the conditions met it performs the service. After that it moves on to monitor the next device until every one is serviced. 1. Interrupts Whenever any device needs its service the device notifies the microcontroller by sending it an interrupt signal. Upon receiving an interrupt signal the microcontroller interrupts whatever it is doing and serves the device. The program which is associated with the interrupt is called the interrupt service routineISR or interrupt handler. 2. Polling The microcontroller continuously monitors the status of a given device. When the conditions met it performs the service. After that it moves on to monitor the next device until every one is serviced. 580

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Interrupt Vs Polling The polling method is not efficient since it wastes much of the microcontrollers time by polling devices that do not need service. The advantage of interrupts is that the microcontroller can serve many devicesnot all at the same time. Each devices can get the attention of the microcontroller based on the assigned priority. For the polling method it is not possible to assign priority since it checks all devices in a round-robin fashion. The microcontroller can also ignoremask a device request for service in Interrupt. The polling method is not efficient since it wastes much of the microcontrollers time by polling devices that do not need service. The advantage of interrupts is that the microcontroller can serve many devicesnot all at the same time. Each devices can get the attention of the microcontroller based on the assigned priority. For the polling method it is not possible to assign priority since it checks all devices in a round-robin fashion. The microcontroller can also ignoremask a device request for service in Interrupt. 581

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Steps in Executing an Interrupt 1. It finishes the instruction it is executing and saves the address of the next instructionPC on the stack. 2. It also saves the current status of all the interrupts internallyi.e: not on the stack. 3. It jumps to a fixed location in memory called the interrupt vector table that holds the address of the ISR. 4. The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it. 5. It starts to execute the interrupt service subroutine until it reaches the last instruction of the subroutine which is RETI return from interrupt. 6. Upon executing the RETI instruction the microcontroller returns to the place where it was interrupted. 1. It finishes the instruction it is executing and saves the address of the next instructionPC on the stack. 2. It also saves the current status of all the interrupts internallyi.e: not on the stack. 3. It jumps to a fixed location in memory called the interrupt vector table that holds the address of the ISR. 4. The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it. 5. It starts to execute the interrupt service subroutine until it reaches the last instruction of the subroutine which is RETI return from interrupt. 6. Upon executing the RETI instruction the microcontroller returns to the place where it was interrupted. 582

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Six Interrupts in 8051 Six interrupts are allocated as follows: 1. Reset power-up reset. 2. Two interrupts are set aside for the timers. one for timer 0 and one for timer 1 3. Two interrupts are set aside for hardware external interrupts. P3.2 and P3.3 are for the external hardware interrupts INT0 or EX1 and INT1or EX2 4. Serial communication has a single interrupt that belongs to both receive and transfer. Six interrupts are allocated as follows: 1. Reset power-up reset. 2. Two interrupts are set aside for the timers. one for timer 0 and one for timer 1 3. Two interrupts are set aside for hardware external interrupts. P3.2 and P3.3 are for the external hardware interrupts INT0 or EX1 and INT1or EX2 4. Serial communication has a single interrupt that belongs to both receive and transfer. 583

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What events can trigger Interrupts We can configure the 8051 so that any of the following events will cause an interrupt: Timer 0 Overflow. Timer 1 Overflow. Reception/Transmission of Serial Character. External Event 0. External Event 1. We can configure the 8051 so that when Timer 0 Overflows or when a character is sent/received the appropriate interrupt handler routines are called. We can configure the 8051 so that any of the following events will cause an interrupt: Timer 0 Overflow. Timer 1 Overflow. Reception/Transmission of Serial Character. External Event 0. External Event 1. We can configure the 8051 so that when Timer 0 Overflows or when a character is sent/received the appropriate interrupt handler routines are called. 584

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8051 Interrupt Vectors Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode 585

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8051 Interrupt related Registers The various registers associated with the use of interrupts are: TCON - Edge and Type bits for External Interrupts 0/1 SCON - RI and TI interrupt flags for RS232 IE - Enable interrupt sources IP - Specify priority of interrupts The various registers associated with the use of interrupts are: TCON - Edge and Type bits for External Interrupts 0/1 SCON - RI and TI interrupt flags for RS232 IE - Enable interrupt sources IP - Specify priority of interrupts 586

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Enabling and Disabling an Interrupt Upon reset all interrupts are disabledmasked meaning that none will be responded to by the microcontroller if they are activated. The interrupts must be enabled by software in order for the microcontroller to respond to them. There is a register called IEinterrupt enable that is responsible for enablingunmasking and disabling masking the interrupts. Upon reset all interrupts are disabledmasked meaning that none will be responded to by the microcontroller if they are activated. The interrupts must be enabled by software in order for the microcontroller to respond to them. There is a register called IEinterrupt enable that is responsible for enablingunmasking and disabling masking the interrupts. 587

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Interrupt Enable IE Register EA : Global enable/disable. --- : Reserved for additional interrupt hardware. ES : Enable Serial port interrupt. ET1 : Enable Timer 1 control bit. EX1 : Enable External 1 interrupt. ET0 : Enable Timer 0 control bit. EX0 : Enable External 0 interrupt. -- EA : Global enable/disable. --- : Reserved for additional interrupt hardware. ES : Enable Serial port interrupt. ET1 : Enable Timer 1 control bit. EX1 : Enable External 1 interrupt. ET0 : Enable Timer 0 control bit. EX0 : Enable External 0 interrupt. MOV IE08h or SETB ET1 588

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Enabling and Disabling an Interrupt Example: Show the instructions toa enable the serial interrupt timer 0 interrupt and external hardware interrupt 1 andb disablemask the timer 0 interrupt thenc show how to disable all the interrupts with a single instruction. Solution: a MOV IE10010110B enable serial timer 0 EX1 Another way to perform the same manipulation is: SETB IE.7 EA1 global enable SETB IE.4 enable serial interrupt SETB IE.1 enable Timer 0 interrupt SETB IE.2 enable EX1 b CLR IE.1 mask disable timer 0 interrupt only c CLR IE.7 disable all interrupts Example: Show the instructions toa enable the serial interrupt timer 0 interrupt and external hardware interrupt 1 andb disablemask the timer 0 interrupt thenc show how to disable all the interrupts with a single instruction. Solution: a MOV IE10010110B enable serial timer 0 EX1 Another way to perform the same manipulation is: SETB IE.7 EA1 global enable SETB IE.4 enable serial interrupt SETB IE.1 enable Timer 0 interrupt SETB IE.2 enable EX1 b CLR IE.1 mask disable timer 0 interrupt only c CLR IE.7 disable all interrupts 589

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Interrupt Priority When the 8051 is powered up the priorities are assigned according to the following. In reality the priority scheme is nothing but an internal polling sequence in which the 8051 polls the interrupts in the sequence listed and responds accordingly. When the 8051 is powered up the priorities are assigned according to the following. In reality the priority scheme is nothing but an internal polling sequence in which the 8051 polls the interrupts in the sequence listed and responds accordingly. 590

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Interrupt Priority We can alter the sequence of interrupt priority by assigning a higher priority to any one of the interrupts by programming a register called IP interrupt priority. To give a higher priority to any of the interrupts we make the corresponding bit in the IP register high. 591

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Interrupt Priority IP Register PS PT1 PX1 PT0 PX0 Reserved Serial Port Timer 1 Pin INT 1 Pin Timer 0 Pin INT 0 Pin Priority bit1 assigns high priority Priority bit0 assigns low priority 592

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KEYBOARD KEYBOARD INTERFACING INTERFACING 593 KEYBOARD KEYBOARD INTERFACING INTERFACING

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KEYBOARD INTERFACING Keyboards are organized in a matrix of rows and columns The CPU accesses both rows and columns through ports . Therefore with two 8-bit ports an 8 x 8 matrix of keys can be connected to a microprocessor When a key is pressed a row and a column make a contact Keyboards are organized in a matrix of rows and columns The CPU accesses both rows and columns through ports . Therefore with two 8-bit ports an 8 x 8 matrix of keys can be connected to a microprocessor When a key is pressed a row and a column make a contact 594

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Otherwise there is no connection between rows and columns In IBM PC keyboards a single microcontroller takes care of hardware and software interfacing A 4x4 matrix connected to two ports The rows are connected to an output port and the columns are connected to an input port Otherwise there is no connection between rows and columns In IBM PC keyboards a single microcontroller takes care of hardware and software interfacing A 4x4 matrix connected to two ports The rows are connected to an output port and the columns are connected to an input port 595

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4x4 matrix 596

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598

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Identify the row and column of the pressed key for each of the following. a D3 D0 1110 for the row D3 D0 1011 for the column b D3 D0 1101 for the row D3 D0 0111 for the column Solution: a The row belongs to D0 and the column belongs to D2 therefore key number 2 was pressed. b The row belongs to D1 and the column belongs to D3 therefore key number 7 was pressed. Identify the row and column of the pressed key for each of the following. a D3 D0 1110 for the row D3 D0 1011 for the column b D3 D0 1101 for the row D3 D0 0111 for the column Solution: a The row belongs to D0 and the column belongs to D2 therefore key number 2 was pressed. b The row belongs to D1 and the column belongs to D3 therefore key number 7 was pressed. 599

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Stepper Motor Interfacing Stepper Motor Interfacing 602

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Stepper Motor Interfacing Stepper motor is a widely used device that translates electrical pulses into mechanical movement. Stepper motor is used in applications such as disk drives dot matrix printer robotics etc It has a permanent magnet rotor called the shaft which is surrounded by a stator. Commonly used stepper motors have four stator windings Such motors are called as four-phase or unipolar stepper motor. Stepper motor is a widely used device that translates electrical pulses into mechanical movement. Stepper motor is used in applications such as disk drives dot matrix printer robotics etc It has a permanent magnet rotor called the shaft which is surrounded by a stator. Commonly used stepper motors have four stator windings Such motors are called as four-phase or unipolar stepper motor. 603

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604

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Step angle: Step angle is defined as the minimum degree of rotation with a single step. No of steps per revolution 360° / step angle Steps per second rpm x steps per revolution / 60 Example: step angle 2° No of steps per revolution 180 Step angle is defined as the minimum degree of rotation with a single step. No of steps per revolution 360° / step angle Steps per second rpm x steps per revolution / 60 Example: step angle 2° No of steps per revolution 180 606

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A switch is connected to pin P2.7. Write an ALP to monitor the status of the SW. If SW 0 motor moves clockwise and if SW 1 motor moves anticlockwise SETB P2.7 MOV A 66H MOV P1A TURN: JNB P2.7 CW RL A ACALL DELAY MOV P1A SJMP TURN CW: RR A ACALL DELAY MOV P1A SJMP TURN SETB P2.7 MOV A 66H MOV P1A TURN: JNB P2.7 CW RL A ACALL DELAY MOV P1A SJMP TURN CW: RR A ACALL DELAY MOV P1A SJMP TURN 607

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Full step 608

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LCD Interfacing before discussed in Unit 3 LCD interfacing using 8086 LCD Interfacing before discussed in Unit 3 LCD interfacing using 8086 Slide number 127128 in Unit 3 609

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Already discussed in UNIT 3 also 610

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HARDWARE CONFIGURATION OF LCD WITH 8051/8086/8085 611

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LCD INTERFACING WITH 8051 TRAINER KIT GPIO- I 8255 J1 Connector PORTS ADDRESS Control port 4003 PORT A 4000 PORT B 4001 PORT C 4002 GPIO- I 8255 J1 Connector PORTS ADDRESS Control port 4003 PORT A 4000 PORT B 4001 PORT C 4002 612

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A/D Interfacing before discussed in Unit 3 A/D interfacing using 8086 A/D Interfacing before discussed in Unit 3 A/D interfacing using 8086 614

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Interfacing ADC to 8051 ADC0804 is an 8 bit successive approximation analogue to digital converter from National semiconductors. The features of ADC0804 are differential analogue voltage inputs 0-5V input voltage range no zero adjustment built in clock generator reference voltage can be externally adjusted to convert smaller analogue voltage span to 8 bit resolution etc. 615

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Steps for converting the analogue input and reading the output from ADC0804 • Make CS0 and send a low to high pulse to WR pin to start the conversion. • Now keep checking the INTR pin. INTR will be 1 if conversion is not finished and INTR will be 0 if conversion is finished. • If conversion is not finished INTR1 poll until it is finished. • If conversion is finished INTR0 go to the next step. • Make CS0 and send a high to low pulse to RD pin to read the data from the ADC. • Make CS0 and send a low to high pulse to WR pin to start the conversion. • Now keep checking the INTR pin. INTR will be 1 if conversion is not finished and INTR will be 0 if conversion is finished. • If conversion is not finished INTR1 poll until it is finished. • If conversion is finished INTR0 go to the next step. • Make CS0 and send a high to low pulse to RD pin to read the data from the ADC. 616

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The circuit initiates the ADC to convert a given analogue input then accepts the corresponding digital data and displays it on the LED array connected at P0. For example if the analogue input voltage Vin is 5V then all LEDs will glow indicating 11111111 in binary which is the equivalent of 255 in decimal. AT89s51 is the microcontroller used here. Data out pins D0 to D7 of the ADC0804 are connected to the port pins P1.0 to P1.7 respectively. LEDs D1 to D8 are connected to the port pins P0.0 to P0.7 respectively. Resistors R1 to R8 are current limiting resistors. In simple words P1 of the microcontroller is the input port and P0 is the output port. Control signals for the ADC INTR WR RD and CS are available at port pins P3.4 to P3.7 respectively. Resistor R9 and capacitor C1 are associated with the internal clock circuitry of the ADC. Preset resistor R10 forms a voltage divider which can be used to apply a particular input analogue voltage to the ADC. Push button S1 resistor R11 and capacitor C4 forms a debouncing reset mechanism. Crystal X1 and capacitors C2C3 are associated with the clock circuitry of the microcontroller. The circuit initiates the ADC to convert a given analogue input then accepts the corresponding digital data and displays it on the LED array connected at P0. For example if the analogue input voltage Vin is 5V then all LEDs will glow indicating 11111111 in binary which is the equivalent of 255 in decimal. AT89s51 is the microcontroller used here. Data out pins D0 to D7 of the ADC0804 are connected to the port pins P1.0 to P1.7 respectively. LEDs D1 to D8 are connected to the port pins P0.0 to P0.7 respectively. Resistors R1 to R8 are current limiting resistors. In simple words P1 of the microcontroller is the input port and P0 is the output port. Control signals for the ADC INTR WR RD and CS are available at port pins P3.4 to P3.7 respectively. Resistor R9 and capacitor C1 are associated with the internal clock circuitry of the ADC. Preset resistor R10 forms a voltage divider which can be used to apply a particular input analogue voltage to the ADC. Push button S1 resistor R11 and capacitor C4 forms a debouncing reset mechanism. Crystal X1 and capacitors C2C3 are associated with the clock circuitry of the microcontroller. 618

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Program: MOV P111111111B // initiates P1 as the input port MAIN: CLR P3.7 // makes CS0 SETB P3.6 // makes RD high CLR P3.5 // makes WR low SETB P3.5 // low to high pulse to WR for starting conversion WAIT: JB P3.4WAIT // polls until INTR0 CLR P3.7 // ensures CS0 CLR P3.6 // high to low pulse to RD for reading the data from ADC MOV AP1 // moves the digital data to accumulator CPL A // complements the digital data MOV P0A // outputs the data to P0 for the LEDs SJMP MAIN // jumps back to the MAIN program END Program: MOV P111111111B // initiates P1 as the input port MAIN: CLR P3.7 // makes CS0 SETB P3.6 // makes RD high CLR P3.5 // makes WR low SETB P3.5 // low to high pulse to WR for starting conversion WAIT: JB P3.4WAIT // polls until INTR0 CLR P3.7 // ensures CS0 CLR P3.6 // high to low pulse to RD for reading the data from ADC MOV AP1 // moves the digital data to accumulator CPL A // complements the digital data MOV P0A // outputs the data to P0 for the LEDs SJMP MAIN // jumps back to the MAIN program END 619 Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode

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D/A Interfacing before discussed in Unit 3 D/A interfacing using 8086 D/A Interfacing before discussed in Unit 3 D/A interfacing using 8086 620

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Digital-to-analog DAC converter • The digital-to-analog converter DAC is a device widely used to convert digital pulses to analog signals. Two methods of creating a DAC: Binary weighted and R/2R ladder. The vast majority of integrated circuit DACs including the MC1408 DAC0808 used in this section use the R/2R method since it can achieve a much higher degree of precision. The first criterion for judging a DAC is its resolution which is a function of the number of binary inputs. The common ones are 8 10 and 12 bits. The number of data bit inputs decides the resolution of the DAC since the number of analog output levels is equal to 2 where n is the number of data bit inputs. Therefore an 8-input DAC such as the DAC0808 provides 256 discrete voltage or current levels of output. Similarly the 12-bit DAC provides 4096 discrete voltage levels. There are also 16-bit DACs but they are more expensive. • The digital-to-analog converter DAC is a device widely used to convert digital pulses to analog signals. Two methods of creating a DAC: Binary weighted and R/2R ladder. The vast majority of integrated circuit DACs including the MC1408 DAC0808 used in this section use the R/2R method since it can achieve a much higher degree of precision. The first criterion for judging a DAC is its resolution which is a function of the number of binary inputs. The common ones are 8 10 and 12 bits. The number of data bit inputs decides the resolution of the DAC since the number of analog output levels is equal to 2 where n is the number of data bit inputs. Therefore an 8-input DAC such as the DAC0808 provides 256 discrete voltage or current levels of output. Similarly the 12-bit DAC provides 4096 discrete voltage levels. There are also 16-bit DACs but they are more expensive. 621

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8051 Connection to DAC808 622

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program to send data to the DAC to generate a stair-step ramp 623

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SENSOR INTERFACING SENSOR INTERFACING take temperature sensor for example 624

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EXTERNAL MEMORY INTERFACING EXTERNAL MEMORY INTERFACING 627

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Access to External Memory • Port 0 acts as a multiplexed address/data bus. Sending the low byte of the program counter PCL as an address. • Port 2 sends the program counter high byte PCH directly to the external memory. • The signal ALE operates as in the 8051 to allow an external latch to store the PCL byte while the multiplexed bus is made ready to receive the code byte from the external memory. • Port 0 then switches function and becomes the data bus receiving the byte from memory. • Port 0 acts as a multiplexed address/data bus. Sending the low byte of the program counter PCL as an address. • Port 2 sends the program counter high byte PCH directly to the external memory. • The signal ALE operates as in the 8051 to allow an external latch to store the PCL byte while the multiplexed bus is made ready to receive the code byte from the external memory. • Port 0 then switches function and becomes the data bus receiving the byte from memory. 628

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Presented by C.GOKULAP/EEE Velalar College of Engg Tech Erode 629

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Books References Mohamed Ali Mazidi Janice Gillispie Mazidi Rolin McKinlay The 8051 Microcontroller and Embedded Systems: Using Assembly and C Programming and Interfacing the 8051 Microcontroller by SencerYeralan Ashutosh Ahluwalia The 8051 Microcontroller by by I. Scott MacKenzie Programming Customizing the 8051 Microcontroller by Michael Predko Microcontrollers by RajKamal Mohamed Ali Mazidi Janice Gillispie Mazidi Rolin McKinlay The 8051 Microcontroller and Embedded Systems: Using Assembly and C Programming and Interfacing the 8051 Microcontroller by SencerYeralan Ashutosh Ahluwalia The 8051 Microcontroller by by I. Scott MacKenzie Programming Customizing the 8051 Microcontroller by Michael Predko Microcontrollers by RajKamal 630

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Documents References • 8051 microcontroller by Suresh P . NairME PhD MIEEE ProfessorHead Department of Electronics and Communication Engineering Royal College of Engineering and Technology • 8051 Microcontroller by Dr. M. Gopikrishna Assistant Professor of PhysicsMaharajas College Ernakulam • 8051 Microcontroller By Er. Swapnil Kaware • 8051 MICROCONTROLLER by Prathyusha Institute of Technology Management in Education • 8051 MICROCONTROLLER by Prathyusha Institute of Technology Management in Education • www.pantechsolutions.net/ • Embedded systems 8051 microcontroller by Amandeep Alag in Education • 8051 microcontroller features by Tech_MX in Technology • 8051 microcontroller by Gaurav Verma in Engineering • 8051 microcontrollerclass1 by Nitin Ahire in Education • 8051 microcontroller by Bibek Kattel in Education • 8051 microcontroller by Jhemi22 in Education • 8051 microcontrollers by Chih-Hsiang Tang in Technology • Embedded systems 8051 microcontroller by Amandeep Alag • Embedded C programming based on 8051 microcontroller by Gaurav Verma • Microcontroller 8051 features application • MICROCONTROLLER-8051 Features Applications Dr. Y .Narasimha Murthy Ph.D. Sri Saibaba National College • 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar Cutajar • Intel microprocessor history by Ramzi_Alqrainy • 8051 microcontroller by Suresh P . NairME PhD MIEEE ProfessorHead Department of Electronics and Communication Engineering Royal College of Engineering and Technology • 8051 Microcontroller by Dr. M. Gopikrishna Assistant Professor of PhysicsMaharajas College Ernakulam • 8051 Microcontroller By Er. Swapnil Kaware • 8051 MICROCONTROLLER by Prathyusha Institute of Technology Management in Education • 8051 MICROCONTROLLER by Prathyusha Institute of Technology Management in Education • www.pantechsolutions.net/ • Embedded systems 8051 microcontroller by Amandeep Alag in Education • 8051 microcontroller features by Tech_MX in Technology • 8051 microcontroller by Gaurav Verma in Engineering • 8051 microcontrollerclass1 by Nitin Ahire in Education • 8051 microcontroller by Bibek Kattel in Education • 8051 microcontroller by Jhemi22 in Education • 8051 microcontrollers by Chih-Hsiang Tang in Technology • Embedded systems 8051 microcontroller by Amandeep Alag • Embedded C programming based on 8051 microcontroller by Gaurav Verma • Microcontroller 8051 features application • MICROCONTROLLER-8051 Features Applications Dr. Y .Narasimha Murthy Ph.D. Sri Saibaba National College • 8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar Cutajar • Intel microprocessor history by Ramzi_Alqrainy 631

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Website References http://amcmp.blogspot.in/2012/06/8051-micro-controller.html http://www.mikroe.com/chapters/view/65/chapter-2-8051-microcontroller-architecture/ https://www.pantechsolutions.net/project-kits/user-guide-for-lcd-interface-card LCD DIsplay http://www.slideshare.net/pantechsolutions/interfacing-stepper-motor-with-8051 stepper motor https://www.pantechsolutions.net/microcontroller-boards/adc-0809-interfacing-with-8086-ps2-lab-kit ADC interface https://www.pantechsolutions.net/microcontroller-boards/dac-0800-interfacing-with-8086-ps2-lab-kit DAC interface https://www.pantechsolutions.net/microcontroller-boards/led-interfacing-with-8086-ps2-lab-kit LED Interface • www.vtulearning.com • www.eazynotes.com • www.slideshare.net • www.scribd.com • www.docstoc.com • www.slideworld.com • www.nptel.ac.in • http://opencourses.emu.edu.tr/ • http://engineeringppt.blogspot.in/ • http://www.pptsearchengine.net/ • www.4shared.com • http://8085projects.info/ http://amcmp.blogspot.in/2012/06/8051-micro-controller.html http://www.mikroe.com/chapters/view/65/chapter-2-8051-microcontroller-architecture/ https://www.pantechsolutions.net/project-kits/user-guide-for-lcd-interface-card LCD DIsplay http://www.slideshare.net/pantechsolutions/interfacing-stepper-motor-with-8051 stepper motor https://www.pantechsolutions.net/microcontroller-boards/adc-0809-interfacing-with-8086-ps2-lab-kit ADC interface https://www.pantechsolutions.net/microcontroller-boards/dac-0800-interfacing-with-8086-ps2-lab-kit DAC interface https://www.pantechsolutions.net/microcontroller-boards/led-interfacing-with-8086-ps2-lab-kit LED Interface • www.vtulearning.com • www.eazynotes.com • www.slideshare.net • www.scribd.com • www.docstoc.com • www.slideworld.com • www.nptel.ac.in • http://opencourses.emu.edu.tr/ • http://engineeringppt.blogspot.in/ • http://www.pptsearchengine.net/ • www.4shared.com • http://8085projects.info/ 632

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NPTEL Lecture Materials References • Microprocessors and Microcontrollers by Prof. Krishna Kumar IISc Bangalore link: http://nptel.ac.in/courses/106108100/ 633

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