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Premium member Presentation Transcript DSP PROCESSORS-IV : DSP PROCESSORS-IV Module 4 : Module 4 Syllabus : Syllabus Typical DSP development systems- - support tools and files - compilers - assemblers - code compressor studio - codec DSP application examples in codec - voice scrambling PLL AI image processing FSK modems voice detection and reverse playback multi rate filters PID controllers. DSP Development System : DSP Development System The development system include - the Code Composer Studio (CCS)- which provides an integrated development environment (IDE) the DSP starter kit (DSK) with the TMS320C6711/13 floating-point processor onboard and complete support for input and output. Slide 5: DSK SUPPORT TOOLS To perform the experiments, the following tools are used: TI’s DSP starter kit (DSK) – it includes: Code Composer Studio (CCS) which provides the necessary software support tools. CCS provides an integrated development environment (IDE), bringing together the C compiler, assembler, linker, debugger, and so on. (b) A board that contains the TMS320C6711 (C6711), floating-point processor a 16-bit codec for input and output (I/O) support. (c) A parallel cable (DB25) that connects the DSK board to a PC. (d) A power supply for the DSK board. Slide 6: 2. An IBM-compatible PC. The DSK board connects to the parallel port of the PC through the DB25 cable included with the DSK package. 3. An oscilloscope, signal generator, and speakers. A signal/spectrum analyzer is optional. Slide 8: Block Diagram Slide 9: DSK Board It is a complete DSP system. The DSK package is powerful, relatively inexpensive with the necessary h/w and s/w support tools for real-time processing The DSK board, with an approx. dimension of 5 x 8 inches, includes the C6713 floating-point digital signal processor and a 16-bit codec for input and output. The onboard codec uses a sigma–delta technology that provides analog-to-digital conversion and digital-to-analog conversion A 4-MHz clock onboard the DSK connects to this codec to provide a fixed sampling rate of 8kHz. A daughter card expansion is also provided on the DSK board. Slide 10: The DSK board includes 16MB of synchronous dynamic RAM(SDRAM) and 128kB of flash ROM. Two connectors on the board provide input and output and are labeled IN (J7) and OUT (J6), respectively. Three of the four user dip switches on the DSK board can be read from a program The onboard clock is 150MHz. The onboard has voltage regulators that provide 1.8V for the C6711 core and 3.3V for its memory and peripherals. Slide 11: DSP Features Operating frequency – 150MHz. VLIW Core – VLIW is a processor architecture that allows many instructions to be issued (8) in a single clock while still allowing for very high clock rates.. Internal Memory – High speed internal memory for maximum performance. Slide 12: On-chip PLL – generates processor clock rate from slower external clock reference. Timers – generates periodic timer events as a function of the processor clock. Used by DSP/BIOS to create time slices for multitasking. EDMA Controller – Enhanced DMA controller allows high speed data transfers without intervention from the DSP. Slide 13: CODEC AIC23 Stereo codec. 32-bit Sample processing Independent Right and Left Channels. Sample rate 8 KHz to 96KHz Slide 14: The ADC circuitry on the codec converts the input analog signal to a digital representation to be processed by the digital signal processor. The maximum level of the input signal to be converted is determined by the specific ADC circuitry on the codec After the captured signal is processed, the result needs to be sent to the outside world. a DAC, which performs the reverse operation of the ADC. An output filter smooths out or reconstructs the output signal ADC, DAC, and all required filtering functions are performed by the single-chip codec Slide 15: block diagram of the codec Analog front end Delta-sigma modulator Digital Interpolation filter Serial interface And Mode control Digital Decimation filter Multi level delta –sigma modulator LPF and Output buffer Left channel in right channel in left channel out Right channel out Digital out Digital in Serial mode control System clock Slide 16: Sigma–delta converters can achieve high resolution with high oversampling ratios The onboard codec over samples by a factor of 64 times. A digital interpolation filter produces the oversampling. The quantization noise power in such devices is independent of the sampling rate. A modulator is included to shape the noise so that it is spread beyond the range of interest. Slide 17: A digital filter is also included to remove the out-of-band noise. A decimation filter reduces the digital data rate to the sampling rate. The DAC’s output is first passed through an internal low pass reconstruction filter to produce an output analog signal. Low noise performance for both ADC and DAC is achieved using oversampling techniques with noise shaping provided by sigma–delta modulators. Slide 18: Code Composer Studio v3.1 Slide 19: Code Composer studio v3.1 Code Composer is the DSP industry's first fully integrated development environment (IDE) with DSP-specific functionality. It can Edit, build, debug, profile and manage projects from a single unified environment. Unique features include – code generation such as a C compiler, an assembler, and a linker. graphical capabilities supports real-time debugging. an easy-to-use software tool to build and debug programs. Slide 20: Software Tool Flow Assembler Linker .obj .out .c Link.cmd .sa Compiler AsmOptimizer Text Editor .asm C6x runs all the code generation tools Slide 21: The C compiler compiles a C source program with extension .c to produce an assembly source file with extension .asm. The assembler assembles an .asm source file to produce a machine language object file with extension .obj. The linker combines object files and object libraries as input to produce an executable file with extension .out. This executable file can be loaded and run directly on the C6711 processor. Slide 22: To create an application project, one can “add” the appropriate files to the project. Compiler/linker options can readily be specified. A number of debugging features are available, includes - setting breakpoints and watching variables, viewing memory, registers, and mixed C and assembly code, graphing results, and monitoring execution time. Slide 23: Real-time analysis can be performed using real-time data exchange (RTDX) associated with DSP/BIOS RTDX allows for data exchange between the host and the target and analysis in real time without stopping the target. Key statistics and performance can be monitored in real time. through the Joint Test Action Group (JTAG), communication with on-chip emulation occurs The C6711 DSK board includes a JTAG emulator interface. Slide 24: CCS Installation and Support Use the parallel (printer) cable DB25 to connect the DSK board to the parallel port on the PC Use the 5V adapter included with the DSK package to connect to the power connector to turn on the DSK. Install CCS with the CD-ROM included with the DSK, When On power, the three LEDs located near the four user dip switches should count from 1 to 7 (binary). Slide 25: CCS provides useful documentations included with the DSK package - 1. Code generation tools (compiler, assembler, linker, etc.) 2. Tutorials on CCS, compiler, RTDX, advanced DSP/BIOS 3. DSP instructions and registers 4. Tools on RTDX, DSP/BIOS, and so on. Slide 26: Useful Types of Files They include: 1. file.pjt : to create and build a project named file. 2. file.c : C source program. 3. file.asm : assembly source program created by the user, by the C compiler,or by the linear optimizer. 4. file.sa : linear assembly source program. The linear optimizer uses file.sa as input to produce an assembly program file.asm. 5. file.h : header support file. 6. file.lib : library file, such as the run-time support library file 7. file.cmd : linker command file that maps sections to memory. 8. file.obj : object file created by the assembler. 9.file.out : executable file created by the linker to be loaded and run on the processor Voice Scrambler : Voice Scrambler Voice scrambling is an analog method that transposes or inverts signals at the transmitter to make the message unintelligible at a receiver not equipped with an appropriately set descrambling device The simplest form of voice inversion splits the voice information into two bands and inverts them around a carrier frequency. This will make the low tones of the voice sound like high ones and vice versa. Common carrier frequencies are: 2.868 kHz, 2.632 kHz, 2.718 kHz, 2.868 kHz, 3.023 kHz, 3.107 kHz, 3.196 kHz, 3.333 kHz, 3.339 kHz, 3.496 kHz, 3.729 kHz and 4.096 kHz. Slide 28: The scrambling method used is commonly referred to as frequency inversion. It takes an audio range, represented by the band 0.3 to 3kHz, and “folds” it about a carrier signal. The frequency inversion is achieved by multiplying (modulating) the audio input by a carrier signal, causing a shift in the frequency spectrum with upper and lower sidebands. On the lower sideband that represents the audible speech range, the low tones are high tones, and vice versa. The original unscrambled voice is recovered when the output of the DSK is used as the input to a second DSK running the same program. Block diagram of voice scrambler : Block diagram of voice scrambler At point A we have a band limited signal 0 to 3kHz.At point B we have a double-sideband signal with suppressed carrier.At point C the upper sideband is filtered out. Its attractiveness comes from its simplicity, since only simple algorithms are utilized for filtering, sine generation/modulation, and up-sampling : At point A we have a band limited signal 0 to 3kHz.At point B we have a double-sideband signal with suppressed carrier.At point C the upper sideband is filtered out. Its attractiveness comes from its simplicity, since only simple algorithms are utilized for filtering, sine generation/modulation, and up-sampling PHASE-LOCKED LOOP : PHASE-LOCKED LOOP The PLL project implements a software-based linear phase-locked loop It consists of a phase detector, a loop filter, and a voltage-controlled oscillator. The software PLL is more versatile. The PLL locks to a sine wave, generated either internally within the program or from an external source. Output signals are viewed on a scope or on a PC using DSP/BIOS’s real-time data transfer (RTDX). Slide 33: The phase detector, multiplies the input sine wave by the square wave output of the DCO. The sum and difference frequencies of the two inputs to the phase detector produces an output with a high- and a low-frequency component, respectively. The low-frequency component is used to control the loop, while the high-frequency component is filtered out. When the PLL is locked, the two inputs to the phase detector are at the same frequency but with a quadrature (90-degree) relationship. The loop filter is a low pass filter that passes the low-frequency output component of the phase detector while it attenuates the undesired high-frequency component. Slide 34: The RTDX feature was used to transfer data to the PC host using a sine wave from a lookup table as input. A single output channel was created to pass to CCS the input signal, the output of both the loop filter and the DCO, and time stamps. CCS buffers these data so that the data can be accessed by other applications on the PC host. CCS has an interface that allows PC applications to access buffered RTDX data. Visual Basic Excel was used (LABVIEW, or Visual C++ can also be used) to display the results on the PC monitor. What is AI? : What is AI? Various definitions: Building intelligent entities. Getting computers to do tasks which require human intelligence. But what is “intelligence”? Simple things turn out to be the hardest to automate: Recognising a face. Navigating a busy street. Understanding what someone says. All tasks require reasoning on knowledge. Overview of Artificial Intelligence (1) : Overview of Artificial Intelligence (1) Artificial intelligence (AI) Computers with the ability to mimic or duplicate the functions of the human brain Artificial intelligence systems The people, procedures, hardware, software, data, and knowledge needed to develop computer systems and machines that demonstrate the characteristics of intelligence Slide 37: Artificialintelligence Robotics Visionsystems Learningsystems Natural languageprocessing Neural networks Expert systems Major Branches of AI : Major Branches of AI Perceptive system A system that approximates the way a human sees, hears, and feels objects Vision system Capture, store, and manipulate visual images and pictures Robotics Mechanical and computer devices that perform tedious tasks with high precision Expert system Stores knowledge and makes inferences Slide 39: Learning system Computer changes how it functions or reacts to situations based on feedback Natural language processing Computers understand and react to statements and commands made in a “natural” language, such as English Neural network Computer system that can act like or simulate the functioning of the human brain Why do AI? : Why do AI? Two main goals of AI: To understand human intelligence better. We test theories of human intelligence by writing programs which emulate it. To create useful “smart” programs able to do tasks that would normally require a human expert. Typical AI Problems : Typical AI Problems Intelligent entities (or “agents”) need to be able to do both “mundane” and “expert” tasks: Mundane tasks - consider going shopping: Planning a route, and sequence of shops to visit! Recognising (through vision) buses, people. Communicating (through natural language). Navigating round obstacles on the street, and manipulating objects for purchase. Expert tasks are things like: medical diagnosis. equipment repair. Often “mundane” tasks are the hardest. ADVANTAGES : ADVANTAGES Smarter artificial intelligence promises to replace human jobs, freeing people for other pursuits by automating manufacturing and transportations. Self-modifying, self-writing, and learning software relieves programmers of the burdensome task of specifying the whole of a program’s functionality—now we can just create the framework and have the program itself fill in the rest (example: real-time strategy game artificial intelligence run by a neural network that acts based on experience instead of an explicit decision tree). Self-replicating applications can make deployment easier and less resource-intensive. AI can see relationships in enormous or diverse bodies of data that a human could not Slide 43: Disadvantages (Risks) Potential for malevolent programs, “cold war” between two countries, unforeseen impacts because it is complex technology, environmental consequences will most likely be minimal. Slide 44: Self-modifying, when combined with self-replicating, can lead to dangerous, unexpected results, such as a new and frequently mutating computer virus. As computers get faster and more numerous, the possibility of randomly creating an artificial intelligence becomes real. Military robots may make it possible for a country to indiscriminately attack less-advanced countries with few, if any, human casualties. Rapid advances in AI could mean massive structural unemployment AI utilizing non-transparent learning (i.e. neural networks) is never completely predictable Slide 45: VCO adjusts its frequency and phase in order to minimise the difference between its phase and the phase of the input signal. Provided that the input signal doesn’t change too fast the VCO stayed locked to the input. Thus the PLL acts like a narrow band tracking filter. VCO v1(t) •PLLs have a large number of applications including: FM/FSK demodulation; frequency synthesis; synchronisation •Depending on the application, either the VCO input control voltage or its output may be used as the PLL output signal. Application: : Application: FM Demodulation Frequency Synthesis THE END : THE END You do not have the permission to view this presentation. In order to view it, please contact the author of the presentation.