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Post Reply Close Saving..... Edit Comment Close Premium member Presentation Transcript Slide 1: UNIT - I CHAPTER – 1 RISC Reduced Instruction Set Computer RISC - Machines : RISC - Machines (1) UltraSPARC Architecture (2) PowerPC Architecture (3) Cray T3E Architecture Slide 3: Introduction - RISC was developed in early 1980’s. The purpose of RISC is “simplify the design processors’. - characterization of RISC standard, fixed instruction length, single cycle execution of instruction. - memory access is done by ‘Load & store” instruction. Some architecture that support RISC architecture is as follow: * UltraSPARC architecture * PowerPC architecture * Cray T3E architecture (1) UltraSPARC Architecture : (1) UltraSPARC Architecture UltraSPARC processor was introduced by Sun Microsystems in 1995 It’s the latest member of SPARC family. Other member of SPARC family is variety of SPACR processor, superSPARC processor The original SPARC architecture was developed in mid-1980’s SPARC – standard for Scalable Processor Architecture UltraSPACR – suitable for Micro – computers Super-computers because implementations are carried in wide range Slide 5: Memory - memory consist of 8-bit bytes - address use byte addresses - formation of word - UltraSPARC programs are written using Virtual Address Space of of 2 64 bytes -address space pages disk physical memory Divided into Some of the pages are stored in Slide 6: Virtual address physical address instruction UltraSPARC (MMU) (2) Register * SPARC – contains 100-general purpose register, but original SPACR architecture is 32-bit in long. * UltraSPARC architecture contains 64-bits in long. * Floating point registers UltraSPARC architecture contain 64-double preceision floating point registers. * Program Counter register (PC) it contains the address of next register next instruction going to be executed. * Condition code register Automatically translated By using specified Slide 7: (3) Data Foramt Slide 8: (4) Instruction format Format-1 * used for call instruction Instruction Format-2 Format * used for Branch instruction * one special instruction, that enters value into a register Format-3 * used for Load & Store registers * and three arithmetic operand operations 32-bit Three basic Instruction format 32-bit 32-bit Slide 9: (5) Addressing modes (6) Instruction set * The SPARC architecture has more than 100-machine instruction * Load & store registers (only one instruction) - used to access memory * other instructions are used to perform register-to-register operation. * instruction execution on SPARC system “pipelined”. which means while one instruction is being executed the next instruction is fetched by memory. Slide 10: * To make the pipeline to work more efficiently, branch instruction are treated as “delayed branches”. (e.g) SUB %Lo, 11, %L1 BA NEXT MOV %L1, %03 - the MOV-instruction is executed before the branch BA. - the MOV – instruction is called “delay state”. (7) Input & Output - each I/O put device communication is carried out by memory - each I/O device has unique address (or) set of address PowerPC Architecture : PowerPC Architecture Slide 12: Introduction * In 1990. the IBM first introduced the PowerPC architecture with Rs.600. * The acronym of POWER is Performance Optimization With Enhanced RISC * In October-1991 IBM, Apple, Motorola formed an alliance to develop & market powerful & low-cost microprocessor. * In In 1993 the first product of PwoerPC chips were delivered. The implementation of powerPC architecture are PowerPC-601, 603, 604 * Further information about PowerPC can be found in 1994. Slide 13: Memory * Memory consist of 8-bit byte, and address are byte address * Formation of word * PowerPC programs can be written using a virtual address space of 2 64 bytes. * virtual address space segment (256-MB) pages (4096-bytes) some of the pages used some of the pages used by physical memory are stored in disk Divided into Divided into Slide 14: (2) Registers (a) General purpose registers - 32-general purpose registers - designated from GPR0 t0 GPR31 - full powerPC architecture, contains 64-bit long registers. - powerPC architecture also implemented on 32-bit registers - usage: store & manipulate integer data & address (b) Floating Point registers (FPU) - computation of floating point is carried out by special FPU. - it contain 32-bit floating point register, & status register & control registers. (c) Condition register - 32 bit condition registers - it’s used as mechanism of testing & branching instruction - this register is divided into eight 4-bit subfields CR0 to CR7 (d) Link Register & Count Register - used for some branch instruction (e) Machine status Register (MSR) - this register is depend on implementaion Slide 15: (3) Data formats Slide 16: (4) Instruction format 1. there are 7 basic instruction formats. Some of the instruction formats have sub format. 2. All of these instruction are 32-bit long 3. instruction must be aligned at the beginning of word boundary 4. the first 6-bit of instruction word specify opcode. 5. some instruction may have extended opcode field. (5) Addressing Modes Slide 17: Load & store operation use any one of the following addressing mode Branch instruction use any one of the following addressing mode Slide 18: (6) Instruction Set * It contains approximately 200-machine instructions * some instructions are more complex (e.g) * Load & store instruction automatically update the index register to compute TA. * floating point addition & multiplication instruction take 3-i/p operand to perform multiplication & addition in one instruction. * instruction execution on PowerPC is “Pipeline”. branch prediction is used speed the execution of instruction * delayed brnach instruction is not used in powerPC architect. (7) Input & Output * This architect provide 2 different method to perform I/O operations Cray t3e architecture : Cray t3e architecture Slide 20: Introduction * in 1995, the T3E supercomputers was developed by “Cray research” * T3E supports: Massively Parallel Processing (MPP) (any machine having 100 (or) 1000 of processors is called MPP) * Reason for supporting used for technical applications in scientific computing * T3E-contains large number of processing elements, arranged in 3D-network overall T3E architecture Interconnect network Processing element node Slide 21: * The 3D.n/w provides a path for transferring data between processors. * In each dimension, the inter-connect n/w is circular. * T3E-system contains from 16 to 2048 processing elements * Each processing element contains DEC Alpha EV5 RISC – microprocessor, local memory, control logic Memory * each PE in 3E has from 64-MB to 2-GB capacity of local memory * Local memory in PE is - physically distributed because each PE contains local memory - Logically shared memory system because microprocessor PE-1 memory PE-2 access Without involving microprocessor of PE-2 Slide 22: * each processing element memory consist of 8-bit bytes * addresses used are byte address * word formation (2) Registers * Alpha architecture contains -32 general purpose registers (R0 to R31) -each general purpose register is 64-bit long -uses’ of general purpose register state & manipulate integer data & addresses. Slide 23: * Floating point registers - 32 floating point registers (F0 to F31) - each floating point register is 64-bit long * Program counter register (64-bit) * Status & control register (3) Data formats Slide 24: (4) Instruction formats * five basic instruction formats with 32-bit long * the first 6-bit of instruction format specify the “opcode”. some instruction format have additional function field (5) Addressing modes Slide 25: * operand in memory are addressed using one of following mode (6) Instruction set * The Alpha architecture contain 130 machine instructions (it reflect RISC orientation). * If the instruction set is designed well, then the implementation of this architecture is fast. Slide 26: (7) Input & Output * I/p & O/p performed using I/O channels. * Every 8-Processing Elements contains one I/O channel. You do not have the permission to view this presentation. In order to view it, please contact the author of the presentation.