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UNIT - I CHAPTER – 1 CISC Complex Instruction Set Computer

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PENTIUM PRO ARCHITECTURE Pentium pro-architecture was introduced in the end of 1995 Pentium pro-architecture is the latest in the x86-family. The recent microprocessor of x86-family is – “80486 microprocessor”. 4. Majority of personal computers use x86 family. 5. X86-processor differ on implementation details operating speed

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(1) MEMORY Memory is described in two different ways (i) physical level (ii) Collection of segments (i) physical level * this level consist of 8-bit bytes of memory * Address used are byte addresses * Word formation

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(ii) Collection of segments * programmers usually view x86 memory as a collection of segments. * Address consist of two parts (i) segment number - different sizes & purposes (e.g) some segment used for execute the instruction some segment used for storing the data some segment may be treated as stacks (ii) offset - points to a byte within the segment * segments pages physical memory disk Divided into Some of the pages of segment stored in

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* segment/offset address physical address byte x86 MMU (2) RESGISTER * there are 8-general purpose registers * the length of general purpose register is 32-bits * name’s of the general purpose registers EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP * generally used for data manipulation Automatically translated By using

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Special purpose registers Some of the special registers are used to store result of “comparison & arithmetic operation”.

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16-bit segment registers There are six 16-bit segment registers 80-bit data registers there are eight 80-bit registers (e.g) FPU

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(4) instruction formats instruction format begin with optional opcode (1(or) 2 bytes) prefixes containing flags Some prefixes some prefixes Count no. of specify the no. of byte specify Instructions addressing the operands & Repeated mode used by addressing mode the operand

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(5) Addressing modes (1) Immediate Mode an operand value is specified as a part of instruction itself is called “Immediate mode”. (2) Register Mode an operand value is specified in register is called “register mode” (3) Target Address Calculation TA = (Base register) + (index register) * (scale factor) + disp Base register any general purpose registers may be used as base registers Index register any general purpose register except ESP can be used as Index register. Scale factor value of scale factor is 1,2,4 (or) 8 disp encoded as part of operation specifiers

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(6) Instruction set * x86 architecture has large complex instruction set * this architecture contain more than 400 instructions set * An instruction may have 0,1 (or) 3 operands (a) Register-to-memory instruction (b) Register-to-memory instruction (c) Memory-to-memory instruction (7) Input & Output * I/P is performed by transferring 1-byte (or) word (or) dword. When I/o port in EAX. * O/P instruction teansger 1-byte word, dword from EAX to I/o port.

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