Compression of Data and Code on Embedded System - Copy

Compression of Data and Code on Embedded System: 

Compression of Data and Code on Embedded System By Prof. Kanade D.G. ID-100208 Symbiosis Institute of R esearch and Innovation

Personal Details: 

Personal Details Educational Qualifications: BE Electronics- Pune University Project: DSP ADD ON CARD ME Electronics- Dr.Babasaheb Ambedkar Marathwada University Project: GSM BASED REMOTE PROCESS CONTROL SYSTEM Experience : Five Years of Industry Eleven Years of Teaching

Literature Survey: 

Literature Survey Compressing executable code is not a new idea; there is a long history of code compression even before the rise of embedded systems. Researchers have studied various code compression techniques even during the 70’s. Executable code compression for embedded systems is a complex problem that is different from regular data compression. This is because embedded systems require partial decompression of the compressed data during runtime due to space Previous work on memory reduction for embedded systems has focused on compressing the instruction segment of executable code before execution and decompressing at runtime.

Proposed Work: 

Proposed Work My work will show that solely compressing the instruction segment is not enough as in many cases executable files contain large data areas that would benefit from compression as well.

Related Work: 

Related Work The MXT technology by Tremaine was one of the first systems that incorporate compression/decompression during runtime of an application. Shaw presented a system that combines compression and encryption in a unified architecture. Benini proposed a compressed memory system where the focus is on energy reduction. Kjelso presented a technology called X- match that improves performance when using memory compression.

My Contribution: 

My Contribution My approach is similar to theirs as I also use content addressable memories (CAM) to match input data with dictionary table entries. However, in my case I use a series of CAMs with different bit-widths to handle variable-length input as opposed to a single one, and my algorithm will select between the different CAMs While there is substantial amount of work on memory compression, my work is the first to address both instructions and data effectively and to target embedded systems where limited levels of memory hierarchy exist.

Problem Statement: 

Problem Statement Previous work on code compression focused on compressing the instruction segment only. This approach has some advantages. 1. Instructions do not change during execution (with the exception of self-modifying code), therefore it is possible to compress before execution once, and then decompress small portions at runtime. 2. Second, indexing compressed instructions, i.e. locating them in the compressed stream is substantially easier than in the case where runtime compression s required

Continued…..: 

Continued….. However I found that often executables contain large areas of data such as .bss ("Block Started by Symbol"), in compilers and linkers) areas that correspond to uninitialized data, which can be modified during runtime. When these areas are large and not compressed, they result in significant reduction of the benefits of instruction segment- only compression.

Slide 9: 

Thank You….

References: 

References [1] B. Tremaine, P. A. Franaszek , J. T Robinson,C . O. Schulz, T. B. Smith, M. E. azlowski , and P. M. Bland. IBM Memory Expansion Technology. IBM Journal of Research and Development, Vol 45 (2),March 2001. [2] L. Benini, D. Bruni , A. Macii , E. Macii . Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors. [3] M. Kjelso, M. Gooch, and S. Jones. Main memory hardware data compression. 22 nd Euro micro Conference, pages 423- 430. IEEE Computer Society Press, September1996. [4] IBM MXT Technology related patents: US Patent No.5,761,536 and 6,240,419. [5 ] Y. Yoshida, B.-Y. Song, H. Okuhata and T. Onoye An Object Code Compression Approach to Embedded Processors, Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED) pp. 265-268, ACM , August, 1997 . [6] A. Wolfe and A. Chanin , Executing Compressed Programs on an Embedded RISC Architecture, Proc. 25th Ann. International Symposium on Microarchitecture , pp . 81-91, Portland, OR, December, 1992 . [7] C. Lefurgy , P. Bird, I. Cheng and T. Mudge , Code Density Using Compression Techniques , Proc. of the 30th Annual International Symposium on MicroArchitecture , pp . 194-203, December, 1997 . [8 ] H. Lekatsas andW.Wolf , Random Access Decompression using Binary Arithmetic Coding , Proceedings of the 1999 IEEE Data Compression Conference, March 1999.