tps quizzes chapter 4

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EEL-3705 TPS QUIZZES: 

EEL-3705 TPS QUIZZES Chapter 4

Quiz 4-1: 

Quiz 4-1

Using the 2x4 Decoder shown below and two-input OR gates, design a logic circuit which implements: 

Using the 2x4 Decoder shown below and two-input OR gates, design a logic circuit which implements

Solution: 

Solution

Quiz 4-2: 

Quiz 4-2

Using the 3x8 Decoder shown below and two-input OR gates, design a logic circuit which implements: 

Using the 3x8 Decoder shown below and two-input OR gates, design a logic circuit which implements

Solution: 

Solution

Solution: 

Solution

Quiz 4-3: 

Quiz 4-3

Using the 3x8 Decoder shown below and two-input OR gates, design a logic circuit which implements: 

Using the 3x8 Decoder shown below and two-input OR gates, design a logic circuit which implements

Solution: 

Solution

Quiz 4-4a: 

Quiz 4-4a

Using 3x8 Decoders with Active LOW Enables and NOT gates, design a logic circuit which implements a 4x16 decoder: 

Using 3x8 Decoders with Active LOW Enables and NOT gates, design a logic circuit which implements a 4x16 decoder

Solution: 

Solution

Quiz 4-4b: 

Quiz 4-4b

Using standard two-input and three-input logic gates, design an encoder circuit that implements the following truth table: 

Using standard two-input and three-input logic gates, design an encoder circuit that implements the following truth table

Solution: 

Solution 1 1 1 1

Y1: 

Y1

Solution: 

Solution 1 1 1 1

Y0: 

Y0

Quiz 4-5: 

Quiz 4-5

Using standard two-input logic gates, design a 2X1 MUX which implements: 

Using standard two-input logic gates, design a 2X1 MUX which implements Your circuit should have three inputs, Data inputs D0 and D1, and control input S. Hint: Develop the truth table first

Solution: 

Solution

Solution: 

Solution

Demonstrations: 

Demonstrations

1 bit deep 2x1 MUX: 

1 bit deep 2x1 MUX 2 Logical Data Inputs 1 bit deep 1 Control Input 1 Logical Output 1 bit deep

1 bit deep 4x1 MUX: 

1 bit deep 4x1 MUX 4 Logical Data Inputs 1 bit deep 2 Control Inputs 1 Logical Output 1 bit deep

2 bits deep 2x1 MUX: 

2 bits deep 2x1 MUX 2 Logical Data Inputs 2 bits deep 1 Control Input 1 Logical Output 2 bits deep

2 bits deep 4x1 MUX: 

2 bits deep 4x1 MUX 4 Logical Data Inputs 2 bits deep 2 Control Inputs 1 Logical Output 2 bits deep

4 bits deep 2x1 MUX: 

4 bits deep 2x1 MUX 2 Logical Data Inputs 4 bits deep 1 Control Input 1 Logical Output 4 bits deep

Quiz 4-6: 

Quiz 4-6

Using the 2X1 MUX shown below and NOT gates, design a logic circuit which implements:: 

Using the 2X1 MUX shown below and NOT gates, design a logic circuit which implements:

Solution: 

Solution We need We have Let a=s, D0=b, D1=b

Quiz 4-7: 

Quiz 4-7

Using standard two-input logic gates, design a 2X1 MUX with Enable which implements: 

Using standard two-input logic gates, design a 2X1 MUX with Enable which implements Your circuit should have four inputs, Data inputs D0 and D1, and control inputs E and S.

Solution: 

Solution

Solution: 

Solution

Quiz 4-8: 

Quiz 4-8

Design a 4x1 MUX using the 2x1 MUX with enable shown below, NOT, and OR gates: 

Design a 4x1 MUX using the 2x1 MUX with enable shown below, NOT, and OR gates Your design should implement this equation

Solution: 

Solution

Quiz 4-9: 

Quiz 4-9

Using the 4x1 MUX shown below and NOT gates, design a logic circuit which implements: 

Using the 4x1 MUX shown below and NOT gates, design a logic circuit which implements

Solution: 

Solution

Quiz 4-10: 

Quiz 4-10

Using the 4x1 MUX shown below and NOT gates, design a logic circuit which implements: 

Using the 4x1 MUX shown below and NOT gates, design a logic circuit which implements

Solution: 

Solution c c c c a b F

Class Design Project: 

Class Design Project

Quiz 4-11: 

Quiz 4-11 Module A

Design a logic circuit (let’s call this module A) which converts a three bit signed magnitude input into its equivalent three bit two’s complement output. Let X2=0 indicate a positive number and X2=1 indicate a negative number. X1 and X0 represent the magnitude of the number. For example : 

Design a logic circuit (let’s call this module A) which converts a three bit signed magnitude input into its equivalent three bit two’s complement output. Let X2=0 indicate a positive number and X2=1 indicate a negative number. X1 and X0 represent the magnitude of the number. For example Hint: Really this is a hint !!!, Develop the truth table for all possible input combinations INPUT: X[2..0] OUTPUT: A[2..0] Module A

Solution: 

Solution

Solution: 

Solution

Solution: 

Solution 1 1 1 1

Quiz 4-12: 

Quiz 4-12 Module B

Design a logic circuit (let’s call this module B) which computes where A is a three bit two’s complement input with a domain of -3 to 3. : 

Design a logic circuit (let’s call this module B) which computes where A is a three bit two’s complement input with a domain of -3 to 3. Hint: This is really another hint!!!, Precompute B in decimal for each possible A and develop a truth table relating B to A in binary. Assume don’t care for B when |A| > 3. How many bits are you going to need for B? INPUT: A[2..0] OUTPUT: B[??..0] Module B

Solution: 

Solution

Solution: 

Solution

Solution: 

Solution 1 1 1 1

Quiz 4-13: 

Quiz 4-13 Module C

Using Half Adders and NOT gates, design a logic circuit which will compute the 2’s comp of a 4-bit signed binary number: 

Using Half Adders and NOT gates, design a logic circuit which will compute the 2’s comp of a 4-bit signed binary number INPUT: B[3..0] OUTPUT: C[3..0] Module C Hint: Calculate the 1’s complement and add 1.

Solution: 

Solution

Quiz 4-14: 

Quiz 4-14 Module D

Using Module C (i.e. 2’s comp module) and the 4-bit wide 2X1 MUX shown below, design a logic circuit which will calculate the sign magnitude of a 4-bit 2’s complement number. You may assume maximum magnitude is 7. Your design should also have an output labeled sign which is sign=1 for negative values. : 

Using Module C (i.e. 2’s comp module) and the 4-bit wide 2X1 MUX shown below, design a logic circuit which will calculate the sign magnitude of a 4-bit 2’s complement number. You may assume maximum magnitude is 7. Your design should also have an output labeled sign which is sign=1 for negative values. INPUT: B[3..0] OUTPUT: D[2..0] Sign Module D

Solution: 

Solution

Quiz 4-15: 

Quiz 4-15 Class Design Project

We have the design for four modules: A: 4-bit Sign Magnitude to 2’s complement B: y=2x-1 for |X|<4 C: 4-bit 2’s complement generator D: 4-bit 2’s complement to Sign Magnitude: 

We have the design for four modules: A: 4-bit Sign Magnitude to 2’s complement B: y=2x-1 for |X|<4 C: 4-bit 2’s complement generator D: 4-bit 2’s complement to Sign Magnitude Team with two other groups. One group (X) should implement module A One group (Y) should implement module B One group (Z) should implement module C,D Pick your groups and decide who is X,Y, and Z.

Slide66: 

I will give a series of inputs to Group X, who should compute A =A[2..0] and give it to group Y, who then needs to compute B=B[3..0] and give it to group Z who then needs to compute D=D[2..0] and Sign. Group D should convert the result to decimal using a minus sign to represent a negative number and record it on the board. Use the index card to pass data from one module to the next.

Block Diagram: 

Block Diagram A B C/D X[2..0] A[2..0] B[3..0] D[2..0] Record Results On Board From Dr. Perry Sign

X=000: 

X=000 1

X=100: 

X=100 2

X=001: 

X=001 3

X=101: 

X=101 4

X=011: 

X=011 5

X=111: 

X=111 6

Quiz 4-16: 

Quiz 4-16

Let tgate=15ns, calculate the worst case delay for a 32-bit adder for the three circuits below. : 

Let tgate=15ns, calculate the worst case delay for a 32-bit adder for the three circuits below.

Let tgate=15ns, calculate the worst case delay for a 32-bit adder.: 

Let tgate=15ns, calculate the worst case delay for a 32-bit adder.

Quiz 4-17: 

Quiz 4-17

Given the 4-bit add/sub module shown below, let A=$D, B=$F, ADD=0, what is S in ADDER module in hex and decimal?: 

Given the 4-bit add/sub module shown below, let A=$D, B=$F, ADD=0, what is S in ADDER module in hex and decimal?

Given the 4-bit add/sub module shown below, let A=$D, B=$F, , what is S?: 

Given the 4-bit add/sub module shown below, let A=$D, B=$F, , what is S? $D+$F=$C -3+(-1)=-4

Quiz 4-18: 

Quiz 4-18

Given the 4-bit add/sub module shown below, let A=$D, B=$F, ADD=1, what is S in hex and decimal?: 

Given the 4-bit add/sub module shown below, let A=$D, B=$F, ADD=1, what is S in hex and decimal?

Given the 4-bit add/sub module shown below, let A=$D, B=$F, ADD=1, what is S?: 

Given the 4-bit add/sub module shown below, let A=$D, B=$F, ADD=1, what is S? $D-$F=$E -3-(-1)=-2

Quiz 4-19: 

Quiz 4-19

Overflow/Underflow Detection: 

Overflow/Underflow Detection Recall That is, if for the MSB carry_in is not equal to carry_out, overflow or underflow has occurred.

Given a 4-bit adder, indicate whether each operation below gives an overflow(O), underflow(U), or correct (OK) answer.: 

Given a 4-bit adder, indicate whether each operation below gives an overflow(O), underflow(U), or correct (OK) answer. 1. $D+$4 2. $6 +$4 3. $7 + $A 4. $F + $F 5. $8 + $F

Given a 4-bit adder, indicate whether each operation below gives an overflow(O), underflow(U), or correct (OK) answer.: 

Given a 4-bit adder, indicate whether each operation below gives an overflow(O), underflow(U), or correct (OK) answer. 1. $D+$4 = $1 (OK) 2. $6 +$4 = $A (O) 3. $7 + $A = $1 (OK) 4. $F + $F = $E (OK) 5. $8 + $F = $7 (U)

Quiz 4-20: 

Quiz 4-20

Given a 4-bit adder, indicate whether each operation below gives an overflow(O), underflow(U), or correct (OK) answer.: 

Given a 4-bit adder, indicate whether each operation below gives an overflow(O), underflow(U), or correct (OK) answer. 1. $D-$7 2. $6 -$4 3. $7 - $A 4. $F - $F 5. $8 - $1

Given a 4-bit adder, indicate whether each operation below gives an overflow(O), underflow(U), or correct (OK) answer.: 

Given a 4-bit adder, indicate whether each operation below gives an overflow(O), underflow(U), or correct (OK) answer. 1. $D-$7=$6 (U) 2. $6 -$4 = $2 (OK) 3. $7 - $A = $D (O) 4. $F - $F = $0 (OK) 5. $8 - $1 =$7 (U)

Quiz 4-21: 

Quiz 4-21

Develop the truth table for a 2 bit signed comparator?: 

Develop the truth table for a 2 bit signed comparator? Your truth table should have four inputs b1 b0 a1 a0 and three outputs F1= (A<B) F2 = (A > B) F3 = (A = B) Assume 2-bit signed (i.e. 2’s comp) values Hint: convert to decimal and compare

Solution: 

Solution

Solution: 

Solution

Quiz 4-22: 

Quiz 4-22

Let A=$C and B=$7 and S[1..0]=00, what is F in hex?: 

Let A=$C and B=$7 and S[1..0]=00, what is F in hex? F[3..0]

Let A=$C and B=$7 and S[1..0]=00, what is F?: 

Let A=$C and B=$7 and S[1..0]=00, what is F? F[3..0] AND Operation F=$04

Quiz 4-23: 

Quiz 4-23

Let A=$C and B=$7 and S[1..0]=10, what is F in hex?: 

Let A=$C and B=$7 and S[1..0]=10, what is F in hex? F[3..0]

Let A=$C and B=$7 and S[1..0]=10, what is F?: 

Let A=$C and B=$7 and S[1..0]=10, what is F? F[3..0] NOT A Operation F=$03

Quiz 4-24: 

Quiz 4-24

Let A=$C and B=$7 and S[1..0]=11, what is F hex?: 

Let A=$C and B=$7 and S[1..0]=11, what is F hex? F[3..0]

Let A=$C and B=$7 and S[1..0]=10, what is F?: 

Let A=$C and B=$7 and S[1..0]=10, what is F? F[3..0] XOR Operation F=$0B

Quiz 4-25: 

Quiz 4-25

Let A=$3 and B=$4, S[1..0]=00, What is F in hex?: 

Let A=$3 and B=$4, S[1..0]=00, What is F in hex?

Let A=$3 and B=$4, S[1..0]=00, What is F in hex?: 

Let A=$3 and B=$4, S[1..0]=00, What is F in hex? F=A+B F=$07 0 0

Quiz 4-26: 

Quiz 4-26

Let A=$3 and B=$4, S[1..0]=10, What is F in hex?: 

Let A=$3 and B=$4, S[1..0]=10, What is F in hex?

Let A=$3 and B=$4, S[1..0]=10, What is F in hex?: 

Let A=$3 and B=$4, S[1..0]=10, What is F in hex? F=A+1 F=$04 0 0