# Metric tree labs

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https://metrictreelabs.com Assembly Language Programming

Instruction set

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Instruction Set of 8085  An instruction is a binary pattern designed inside a microprocessor to perform a specific function.  The entire group of instructions that a microprocessor supports is called Instruction Set.  8085 has 246 instructions.  Each instruction is represented by an 8-bit binary value.  These 8-bits of binary value is called Op-Code or Instruction Byte.

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Classification of Instruction Set  Data Transfer Instruction  Arithmetic Instructions  Logical Instructions  Branching Instructions  Control Instructions

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1.Data Transfer Instructions  These instructions move data between registers or between memory and registers.  These instructions copy data from source to destinationwithout changing the original data .

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2.Arithmetic Instructions  These instructions perform the operations like:  Addition  Subtract  Increment  Decrement

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3.Logical Instructions  These instructions perform logical operations on data stored in registers memory and status flags.  The logical operations are: ◦ AND ◦ OR ◦ XOR ◦ Rotate ◦ Compare ◦ Complement

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4.Branching Instructions  The branch group instructions allows the microprocessor to change the sequence of program either conditionally or under certain test conditions. The group includes  1 Jump instructions  2 Call and Return instructions  3 Restart instructions 20-Nov-19 https://metrictreelabs.com

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5. Control Instructions  The control instructions control the operation of microprocessor.

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Writing a Assembly Language Program • Steps to write a program – Analyze the problem – Develop program Logic – Write an Algorithm – Make a Flowchart – Write program Instructions using Assembly language of 8085

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Program 8085 in Assembly language to add two 8-bit numbers and store 8-bit result in register C. 1. Analyze the problem – Addition of two 8-bit numbers to be done 2. Program Logic – Add two numbers – Store result in register C – Example 10011001 99H A +00111001 39H D 11010010 D2H C

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3. Algorithm 1. Get two numbers 2. Add them 3. Store result 4. Stop https://metrictreelabs.c om • Load 1 st no. in register D • Load 2 nd no. in register E Translation to 8085 operations • Copy register D to A • Add register E to A • Copy A to register C • Stop processing

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4. Make a Flowchart Start Load Registers D E Copy D to A Add A and E Copy A to C Stop • Load 1 st no. in register D • Load 2 nd no. in register E • Copy register D to A • Add register E to A • Copy A to register C • Stop processing

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5. Assembly Language Program 1. Get two numbers 2. Add them 3. Store result 4. Stop a Load 1 st no. in register D b Load 2 nd no. in register E a Copy register D to A b Add register E to A a Copy A to register C a Stop processing https://metrictreelabs.com/ MVI D 2H MVI E 3H MOV A D ADD E MOV C A HLT

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https://metrictreelabs.com/

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1.Data Transfer Instructions  https://metrictreelabs.com/

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Opcode Operand MOV Rd Rs M Rs Rd M  This instruction copies the contents of the source register into the destination register. contents of the source register are not altered  If one of the operands is a memory location its location is specified by the contents of the HL registers.  Example: MOV B C or MOV B M

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A 20 B 20 A F B 30 C D E H 20 L 50 A 20 B BEFORE EXECUTION AFTER EXECUTION MOV BA A F B 30 C D E H 20 L 50 A F B C D E H 20 L 50 A F B C 40 D E H 20 L 50 MOV MB MOV CM 40 40 30

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Opcode Operand MVI Rd Data M Data  The 8-bit data is stored in the destination register or memory.  If the operand is a memory location its location is specified by the contents of the H-L registers.  Example: MVI B 60H or MVI M 40Hhttps://metrictreelabs.com/

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A F B C D E H L A F B 60 C D E H L AFTER EXECUTION BEFORE EXECUTION MVI B60H 40 HL2050 2051H 204FH 204F 2051H MVI M40Hhttps ://metrictre elabs.com / BEFORE EXECUTION AFTER EXECUTION HL2050

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Opcode Operand LDA 16-bit address  The contents of a memory location specified by a 16- bit address in the operand are copied to the accumulator.  The contents of the source are not altered.  Example: LDA 2000H

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A 30 A 30 30 AFTER EXECUTION BEFORE EXECUTION LDA 2000H 2000H 2000H

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Opcode Operand LDAX B/D Register Pair  The contents of the designated register pair point to a memory location.  This instruction copies the contents of that memory location into the accumulator.  The contents of either the register pair or the memory location are not altered.  Example: LDAX D

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A F B C D 20 E 30 A 80 F B C D 20 E 30 80 80 AFTER EXECUTION BEFORE EXECUTION LDAX D 2030H 2030H

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Opcode Operand LXI Reg. pair 16-bit data  This instruction loads 16-bit data in the register pair.  Example: LXI H 2030 H

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Opcode Operand LHLD 16-bit address  This instruction copies the contents of memory location pointed out by 16-bit address into register L.  It copies the contents of next memory location into register H.  Example: LHLD 2030 H

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A F B C H L A 80 F B C H 85 L 00 00 85 60 AFTER EXECUTION BEFORE EXECUTION LHLD 2030 2030H 8500H M6 0

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Opcode Operand STA 16-bit address  The contents of accumulator are copied into the memory location specified by the operand.  Example: STA 2000H

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A 50 A 50 50 AFTER EXECUTION BEFORE EXECUTION STA 2000H 2000H 2000H

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Opcode Operand STAX Reg. pair  The contents of accumulator are copied into the memory location specified by the contents of the register pair.  Example: STAX B

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B 85 C 00 A1AH BEFORE EXECUTION AFTER EXECUTION STAX B 1A 8500H

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Opcode Operand SHLD 16-bit address  The contents of register L are stored into memory location specified by the 16-bit address.  The contents of register H are stored into the next memory location.  Example: SHLD 2550H

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D E H 70 L 80 BEFORE EXECUTION AFTER EXECUTION SHLD 8500 80 70 8500H 8501H

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Opcode Operand XCHG None  The contents of register H are exchanged with the contents of register D.  The contents of register L are exchanged with the contents of register E.  Example: XCHG

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D 20 E 40 H 70 L 80 D 70 E 80 H 20 L 40 BEFORE EXECUTION AFTER EXECUTION XCHG

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Opcode Operand SPHL None  This instruction loads the contents of H-L pair into SP.  Example: SPHL

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H 25 L 00 SP BEFORE EXECUTION AFTER EXECUTION SPHL SP 2500 H 25 L 00

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Opcode Operand XTHL None  The contents of L register are exchanged with the location pointed out by the contents of the SP.  The contents of H register are exchanged with the next location SP + 1.  Example: XTHL

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H 30 L 40 SP 2700 BEFORE EXECUTION 50 60 H 60 L 50 SP 2700 40 30 AFTER EXECUTION XTHL 2700H 2701H 2702H 2700H 2701H 2702H LSP HSP+1

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Opcode Operand PUSH Reg. pair  The contents of register pair are copied onto stack.  SP is decremented and the contents of high-order registers B D H A are copied into stack.  SP is again decremented and the contents of low-order registers C E L Flags are copied into stack.  Example: PUSH H

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Opcode Operand Description PCHL None Load program counter with H-L contents  The contents of registers H and L are copied into the program counter PC.  The contents of H are placed as the high-order byte and the contents of L as the low-order byte.  Example: PCHL

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Opcode Operand POP Reg. pair  The contents of top of stack are copied into register pair.  The contents of location pointed out by SP are copied to the low-order register C E L Flags.  SP is incremented and the contents of location are copied to the high-order register B D H A.  Example: POP H

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Opcode Operand IN 8-bit port address  The contents of I/O port are copied into accumulator.  Example: IN 8C H

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10 A 10 A 10 BEFORE EXECUTION AFTER EXECUTION IN 80H PORT 80H PORT 80H

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Opcode Operand OUT 8-bit port address  The contents of accumulator are copied into the I/O port.  Example: OUT 78H

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10 A 40 40 A 40 BEFORE EXECUTION AFTER EXECUTION OUT 50H PORT 50H PORT 50H

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 These instructions perform the operations like:  Addition  Subtract  Increment  Decrement

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 Any 8-bit number or the contents of register or the contents of memory location can be added to the contents of Accumulator.  The result sum is stored in the Accumulator.  NB: No two other 8-bit registers can be added directly.  Example: The contents of register B cannot be added directly to the contents of register C.

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Opcode Operand Description ADD R M Add register or memory to accumulator  The contents of register or memory are added to the contents of accumulator.  The result is stored in accumulator.  If the operand is memory location its address is specified by H-L pair.  Example: ADD B or ADD M

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B C 05 D E H L B C 05 D E H L AFTER EXECUTION BEFORE EXECUTION B C D E H 20 L 50 B C D E H 20 L 50 AFTER EXECUTION BEFORE EXECUTION A 09 A 04 ADD C AA+C ADD M AA+M 10 10 2050 2050 A 04 A 14 04+0509 04+1014

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Opcode Operand Description ADC R M Add register or memory to accumulator with carry  The contents of register or memory and Carry Flag CY are added to the contents of accumulator.  The result is stored in accumulator.  If the operand is memory location its address is specified by H-L pair.  All flags are modified to reflect the result of the addition.  Example: ADC B or ADC M

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B C 05 D E H L A 50 B C 20 D E H L A 56 AFTER EXECUTION BEFORE EXECUTION ADC C AA+C+CY CY 01 CY 1 A 06 A 37 H 20 L 50 H 20 L 50 ADC M AA+M+CY AFTER EXECUTION BEFORE EXECUTION 30 30 2050H 2050H 06+1+3037 50+05+0156

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Opcode Operand Description ADI 8-bit data Add immediate to accumulator  The 8-bit data is added to the contents of accumulator.  The result is stored in accumulator.  All flags are modified to reflect the result of the addition.  Example: ADI 45 H

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A 03 AFTER EXECUTION BEFORE EXECUTION ADI 05H AA+DATA8 A 08 03+0508

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Opcode Operand Description ACI 8-bit data Add immediate to accumulator with carry  The 8-bit data and the Carry Flag CY are added to the contents of accumulator.  The result is stored in accumulator.  All flags are modified to reflect the result of the addition.  Example: ACI 45 H

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CY 1 A 05 AFTER EXECUTION BEFORE EXECUTION ACI 20H AA+DATA 8+CY A 26 05+20+126

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Opcode Operand Description DAD Reg. pair Add register pair to H-L pair  The 16-bit contents of the register pair are added to the contents of H-L pair.  The result is stored in H-L pair.  If the result is larger than 16 bits then CY is set.  No other flags are changed.  Example: DAD B or DAD D

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D 12 E 34 H 23 L 45 D 12 E 34 H 35 L 79 BEFORE EXECUTION AFTER EXECUTION DAD D DAD D HLHL+DE DAD B HLHL+BC 1234 2345 + ------- 3579

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 Any 8-bit number or the contents of register or the contents of memory location can be subtracted from the contents of accumulator.  The result is stored in the accumulator.  Subtraction is performed in 2’s complement form.  If the result is negative it is stored in 2’s complement form.  No two other 8-bit registers can be subtracted directly.

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Opcode Operand Description SUB R M Subtract register or memory from accumulator  The contents of the register or memory location are subtracted from the contents of the accumulator.  The result is stored in accumulator.  If the operand is memory location its address is specified by H-L pair.  All flags are modified to reflect the result of subtraction.  Example: SUB B or SUB M

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B C 04 D E H L B C 04 D E H L AFTER EXECUTION BEFORE EXECUTION B C D E H 20 L 50 B C D E H 20 L 50 AFTER EXECUTION BEFORE EXECUTION A 05 A 09 SUB C AA-C SUB M AA-M 10 10 2050 2050 A 14 A 04 09-0405 14-1004

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Opcode Operand Description SBB R M Subtract register or memory from accumulator with borrow  The contents of the register or memory location and Borrow Flag i.e. CY are subtracted from the contents of the accumulator.  The result is stored in accumulator.If the operand is memory location its address is specified by H-L pair.  All flags are modified to reflect the result of subtraction.  Example: SBB B or SBB M

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B C 05 D E H L A 08 B C 05 D E H L A 02 AFTER EXECUTION BEFORE EXECUTION SBB C AA-C-CY CY 01 CY 1 A 06 A 03 H 20 L 50 H 20 L 50 SBB M AA-M-CY AFTER EXECUTION BEFORE EXECUTION 02 02 2050H 2050H 08-05-0102 06-02-103

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Opcode Operand Description SUI 8-bit data Subtract immediate from accumulator  The 8-bit data is subtracted from the contents of the accumulator.  The result is stored in accumulator.  All flags are modified to reflect the result of subtraction.  Example: SUI 05H

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A 08 AFTER EXECUTION BEFORE EXECUTION SUI 05H AA-DATA8 A 03 08-0503

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Opcode Operand Description SBI 8-bit data Subtract immediate from accumulator with borrow  The 8-bit data and the Borrow Flag i.e. CY is subtracted from the contents of the accumulator.  The result is stored in accumulator.  All flags are modified to reflect the result of subtraction.  Example: SBI 45 H

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CY 1 A 25 AFTER EXECUTION BEFORE EXECUTION SBI 20H AA-DATA 8-CY A 04 25-20-0104

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 The 8-bit contents of a register or a memory location can be incremented or decremented by 1.  The 16-bit contents of a register pair can be incremented or decremented by 1.  Increment or decrement can be performed on any register or a memory location.

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Opcode Operand Description INR R M Increment register or memory by 1  The contents of register or memory location are incremented by 1.  The result is stored in the same place.  If the operand is a memory location its address is specified by the contents of H-L pair.  Example: INR B or INR M

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B 10 C D E H L A B 11 C D E H L A AFTER EXECUTION BEFORE EXECUTION H 20 L 50 H 20 L 50 10 1 1 2050H 2050H AFTER EXECUTION BEFORE EXECUTION INR M MM+1 B 10 C D E H L A BEFORE EXECUTION INR B RR+1 10+111 10+111

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Opcode Operand Description INX R Increment register pair by 1  The contents of register pair are incremented by 1.  The result is stored in the same place.  Example: INX H or INX B or INX D

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B C D E H 10 L 20 B C D E H 10 L 21 AFTER EXECUTION BEFORE EXECUTION SP SP INX H RPRP+1 1020+11021

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Opcode Operand Description DCR R M Decrement register or memory by 1  The contents of register or memory location are decremented by 1.  The result is stored in the same place.  If the operand is a memory location its address is specified by the contents of H-L pair.  Example: DCR B or DCR M

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B C D E 19 H L A AFTER EXECUTION B C D E 20 H L A BEFORE EXECUTION DCR E RR-1 H 20 L 50 H 20 L 50 21 20 2050H AFTER EXECUTION BEFORE EXECUTION DCR M MM-1 2050H 21-120 20-119

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Opcode Operand Description DCX R Decrement register pair by 1  The contents of register pair are decremented by 1.  The result is stored in the same place.  Example: DCX H or DCX B or DCX D

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B C D E H 10 L 21 B C D E H 10 L 20 AFTER EXECUTION BEFORE EXECUTION SP SP DCX H RPRP-1

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 These instructions perform logical operations on data stored in registers memory and status flags.  The logical operations are: ◦ AND ◦ OR ◦ XOR ◦ Rotate ◦ Compare ◦ Complement

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 Any 8-bit data or the contents of register or memory location can logically have ◦ AND operation ◦ OR operation ◦ XOR operation with the contents of accumulator.  The result is stored in accumulator.

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Opcode Operand Description ANA R M Logical AND register or memory with accumulator  The contents of the accumulator are logically ANDed with the contents of register or memory.  The result is placed in the accumulator.  If the operand is a memory location its address is specified by the contents of H-L pair.  S Z P are modified to reflect the result of the operation.  CY is reset and AC is set.  Example: ANA B or ANA M.

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B 10 C D E H L A B 0F C D E H L A 0A AFTER EXECUTION ANA B AA and R B 0F C D E H L A AA BEFORE EXECUTION CY A C CY 0 A C 1 AFTER EXECUTION BEFORE EXECUTION CY A C CY 0 A C 1 A 11 A 55 H 20 L 50 H 20 L 50 B3 B3 2050H ANA M AA and M 2050H 1010 1010AAH 0000 11110FH 0000 10100AH 0101 010155H 1011 0011B3H 0001 000111H

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Opcode Operand Description ANI 8-bit data Logical AND immediate with accumulator  The contents of the accumulator are logically ANDed with the 8-bit data.  The result is placed in the accumulator.  S Z P are modified to reflect the result.  CY is reset AC is set.  Example: ANI 86H.

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CY A C A B3 AFTER EXECUTION BEFORE EXECUTION CY 0 A C 1 A 33 ANI 3FH AA and DATA8 1011 0011B3H 0011 11113FH 0011 001133H

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Opcode Operand Description ORA R M Logical OR register or memory with accumulator  The contents of the accumulator are logically ORed with the contents of the register or memory.  The result is placed in the accumulator.  If the operand is a memory location its address is specified by the contents of H-L pair.  S Z P are modified to reflect the result.  CY and AC are reset.  Example: ORA B or ORA M.

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AFTER EXECUTION BEFORE EXECUTION CY A C ORA B AA or R 1010 1010AAH 0001 001012H 1011 1010BAH B 12 C D E H L A AA B 12 C D E H L A BA CY 0 A C 0

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AFTER EXECUTION BEFORE EXECUTION CY A C ORA M AA or M 0101 010155H 1011 0011B3H 1111 0111F7H H 20 L 50 A 55 A F7 CY 0 A C 0 H 20 L 50 B3 B3 2050H 2050H

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Opcode Operand Description ORI 8-bit data Logical OR immediate with accumulator  The contents of the accumulator are logically ORed with the 8-bit data.  The result is placed in the accumulator.  S Z P are modified to reflect the result.  CY and AC are reset.  Example: ORI 86H.

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CY A C A B3 AFTER EXECUTION BEFORE EXECUTION CY 0 A C 0 A BB ORI 08H AA or DATA8 1011 0011B3H 0000 100008H 1011 1011BBH

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Opcode Operand Description XRA R M Logical XOR register or memory with accumulator  The contents of the accumulator are XORed with the contents of the register or memory.  The result is placed in the accumulator.  If the operand is a memory location its address is specified by the contents of H-L pair.  S Z P are modified to reflect the result of the operation.  CY and AC are reset.  Example: XRA B or XRA M.

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B 10 C D E H L A B C 2D D E H L A 87 AFTER EXECUTION XRA C AA xor R B C 2D D E H L A AA BEFORE EXECUTION CY A C CY 0 A C 0 1010 1010AAH 0010 11012DH 1000 011187H

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H 20 L 50 A 55 AFTER EXECUTION XRA M AA xor M BEFORE EXECUTION CY A C CY 0 A C 0 0101 010155H 1011 0011B3H 1110 0110E6H H 20 L 50 A E6 B3 B3 2050H 2050H

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Opcode Operand Description XRI 8-bit data XOR immediate with accumulator  The contents of the accumulator are XORed with the 8-bit data.  The result is placed in the accumulator.  S Z P are modified to reflect the result.  CY and AC are reset.  Example: XRI 86H.

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CY A C A B3 AFTER EXECUTION BEFORE EXECUTION CY 0 A C 0 A 8A XRI 39H AA xor DATA8 1011 0011B3H 0011 100139H 1000 10108AH

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 Any 8-bit data or the contents of register or memory location can be compares for: ◦ Equality ◦ Greater Than ◦ Less Than with the contents of accumulator.  The result is reflected in status flags.

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Opcode Operand Description CMP R M Compare register or memory with accumulator  The contents of the operand register or memory are compared with the contents of the accumulator.  Both contents are preserved .

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B 10 C D E H L A B C D 20 E H L A 10 AFTER EXECUTION CMP D A-R B C D 20 E H L A 10 BEFORE EXECUTION CY Z CY 01 Z 0 AFTER EXECUTION BEFORE EXECUTION CY Z CY 0 ZF 1 A B8 A B8 H 20 L 50 H 20 L 50 B8 B8 2050H CMP M A-M 2050H AR: CY0 AR: ZF1 AR: CY1 AM: CY0 AM: ZF1 AM: CY1 1020:CY01 B8B8 :ZF01

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Opcode Operand Description CPI 8-bit data Compare immediate with accumulator  The 8-bit data is compared with the contents of accumulator.  The values being compared remain unchanged.

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CY Z A BA AFTER EXECUTION BEFORE EXECUTION CY 0 A C 0 A BA CPI 30H A-DATA ADATA: CY0 ADATA: ZF1 ADATA: CY1 BA30 : CY00

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 Each bit in the accumulator can be shifted either left or right to the next position.

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Opcode Operand Description RLC None Rotate accumulator left  Each binary bit of the accumulator is rotated left by one position.  Bit D7 is placed in the position of D0 as well as in the Carry flag.  CY is modified according to bit D7.  S Z P AC are not affected.  Example: RLC.

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B7 B6 B5 B4 B3 B2 B1 B0 CY B6 B5 B4 B3 B2 B1 B0 B7 B7 AFTER EXECUTION BEFORE EXECUTION

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Opcode Operand Description RRC None Rotate accumulator right  Each binary bit of the accumulator is rotated right by one position.  Bit D0 is placed in the position of D7 as well as in the Carry flag.  CY is modified according to bit D0.  S Z P AC are not affected.  Example: RRC.

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B7 B6 B5 B4 B3 B2 B1 B0 CY B0 B7 B6 B5 B4 B3 B2 B1 B0 AFTER EXECUTION BEFORE EXECUTION

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Opcode Operand Description RAL None Rotate accumulator left through carry  Each binary bit of the accumulator is rotated left by one position through the Carry flag.  Bit D7 is placed in the Carry flag and the Carry flag is placed in the least significant position D0.  CY is modified according to bit D7.  S Z P AC are not affected.  Example: RAL.

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B7 B6 B5 B4 B3 B2 B1 B0 CY B6 B5 B4 B3 B2 B1 B0 CY B7 AFTER EXECUTION BEFORE EXECUTION

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Opcode Operand Description RAR None Rotate accumulator right through carry  Each binary bit of the accumulator is rotated right by one position through the Carry flag.  Bit D0 is placed in the Carry flag and the Carry flag is placed in the most significant position D7.  CY is modified according to bit D0.  S Z P AC are not affected.  Example: RAR.

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B7 B6 B5 B4 B3 B2 B1 B0 CY CY B7 B6 B5 B4 B3 B2 B1 B0 AFTER EXECUTION BEFORE EXECUTION

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 The contents of accumulator can be complemented.  Each 0 is replaced by 1 and each 1 is replaced by 0.

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Opcode Operand Description CMA None Complement accumulator  The contents of the accumulator are complemented.  No flags are affected.  Example: CMA. AA’ A 00 A FF BEFORE EXECUTION AFTER EXECUTION

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Opcode Operand Description CMC None Complement carry  The Carry flag is complemented.  No other flags are affected.  Example: CMC cc’ BEFORE EXECUTION AFTER EXECUTION C 00 C FF

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Opcode Operand Description STC None Set carry  The Carry flag is set to 1.  No other flags are affected.  Example: STC CF1 S-set 1 C-clear 0

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 The branch group instructions allows the microprocessor to change the sequence of program either conditionally or under certain test conditions. The group includes  1 Jump instructions  2 Call and Return instructions  3 Restart instructions

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Opcode Operand Description JMP 16-bit address Jump unconditionally  The program sequence is transferred to the memory location specified by the 16-bit address given in the operand.  Example: JMP 2034 H.

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Opcode Operand Description Jx 16-bit address Jump conditionally  The program sequence is transferred to the memory location specified by the 16-bit address given in the operand based on the specified flag of the PSW.  Example: JZ 2034 H.

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Opcode Description Status Flags JC Jump if Carry CY 1 JNC Jump if No Carry CY 0 JZ Jump if Zero Z 1 JNZ Jump if No Zero Z 0 JPE Jump if Parity Even P 1 JPO Jump if Parity Odd P 0 A-Above B-Below C-Carry Z-Zero P-Parity

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Opcode Operand Description CALL 16-bit address Call unconditionally  The program sequence is transferred to the memory location specified by the 16-bit address given in the operand.  Before the transfer the address of the next instruction after CALL the contents of the program counter is pushed onto the stack.  Example: CALL 2034 H.

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Opcode Description Status Flags CC Call if Carry CY 1 CNC Call if No Carry CY 0 CP Call if Positive S 0 CM Call if Minus S 1 CZ Call if Zero Z 1 CNZ Call if No Zero Z 0 CPE Call if Parity Even P 1 CPO Call if Parity Odd P 0

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Opcode Operand Description RET None Return unconditionally  The program sequence is transferred from the subroutine to the calling program.  The two bytes from the top of the stack are copied into the program counter and program execution begins at the new address.  Example: RET.

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Opcode Description Status Flags RC Return if Carry CY 1 RNC Return if No Carry CY 0 RP Return if Positive S 0 RM Return if Minus S 1 RZ Return if Zero Z 1 RNZ Return if No Zero Z 0 RPE Return if Parity Even P 1 RPO Return if Parity Odd P 0

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Opcode Operand Description RST 0 – 7 Restart Software Interrupts  The RST instruction jumps the control to one of eight memory locations depending upon the number.  These are used as software instructions in a program to transfer program execution to one of the eight locations.  Example: RST 1 or RST 2 ….

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Instruction Code Vector Address RST 0 080000H RST 1 180008H RST 2 280010H RST 3 380018H RST 4 480020H RST 5 580028H RST 6 680030H RST 7 780038H

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 The control instructions control the operation of microprocessor.

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Opcode Operand Description NOP None No operation  No operation is performed.  The instruction is fetched and decoded but no operation is executed.  Example: NOP

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Opcode Operand Description HLT None Halt  The CPU finishes executing the current instruction and halts any further execution.  An interrupt or reset is necessary to exit from the halt state.  Example: HLT

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Opcode Operand Description DI None Disable interrupt  The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled.  No flags are affected.  Example: DI

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Opcode Operand Description EI None Enable interrupt  The interrupt enable flip-flop is set and all interrupts are enabled.  No flags are affected.  This instruction is necessary to re-enable the interrupts except TRAP.  Example: EI

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Opcode Operand Description RIM None Read Interrupt Mask  This is a multipurpose instruction used to read the status of interrupts 7.5 6.5 5.5 and read serial data input bit.  The instruction loads eight bits in the accumulator with the following interpretations.  Example: RIM

### slide 135:

Opcode Operand Description SIM None Set Interrupt Mask  This is a multipurpose instruction and used to implement the 8085 interrupts 7.5 6.5 5.5 and serial data output.  The instruction interprets the accumulator contents as follows.  Example: SIM