8051 Hardware Architecture

8051 Hardware Architecture: 

8051 Hardware Architecture 8051 Resources Internal Architecture Pins and Signals Delay Incorporation by software Port operation Memory Interfacing

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Block Diagram of 8051 is

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Internal interrupts include - timer interrupts - serial port interrupts Timer Interrupts – Timer 0 or Timer 1 overflow Serial Port Interrupts – Cmpletion of Transmission or reception or serial data.

Memory map of 8051 : 

Memory map of 8051

Program memory – Total capacity 64 KB: 

Program memory – Total capacity 64 K B ( i ) 4 KB internal ROM (0000H – 0FFFH) 60 KB external memory (1000H – FFFFH) EA = 5V i.e. External Address is not there for first 4KB. 64 KB external memory (0000H – FFFFH) EA = 0V i.e. First 4KB is external to processor chip

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Data Memory- External Data Memory =64KB Internal Data RAM =128 bytes Special Function Registers =21 Internal Data RAM- Register Bank 0 to Register Bank 4 – 32 bytes Direct Bit Addressing – 16 bytes General Purpose Data Ram – 80 bytes

Register Bank selected by bit 3 and bit 4 of PSW: 

Register Bank selected by bit 3 and bit 4 of PSW

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Memory location 20 to 2F (16 bytes) -Individual bits may be addressed or may be used as bytes Bits addressed are –

Special Function Registers: 

Special Function Registers Special Function Register in 8051 are - ACC - Accumulator* B - B Register* PSW - Program Status Word* SP - Stack Pointer DPTR (Low) - Data Pointer Low DPTR (High) - Data Pointer High P0 - Port 0* P1 - Port 1* P2 - Port 2* P3 - Port 3* IP - Interrupt Priority* IE - Interrupt Enable* TMOD - Timer/Counter Mode TCON - Timer/Counter Control* TH0 - (Timer/Counter) 0 High TL0 - (Timer/Counter) 0 Low TH1 - (Timer/Counter) 1 High TL1 - (Timer/Counter) 1 Low SCON - Serial Control* SBUF - Serial Data Buffer PCON - Power Control * These bytes are bit addressable as well.

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Some of the SFRS (Total 11) are byte as well bit addressable –

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Bit addresses of the SFR’S are –

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Note: observe the vacant space between SFR’s. These can be used an data RAM locations. Stack Operation Stack operation is explained in

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Stack in maintained in internal Data RAM PUSH - Stack pointer is incremented. - Data is stored. POP – Data is taken out from stack. - stack pointer is decremented. stack starts at lower location and grows to higher location as data is pushed. In 8086, it is opposite.

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Data Pointer(DPTR) – 16 bit register (DPH, DPL) – used for storing 16 bit address. Ports(0-3) 4 bidirectional I/O ports of 8 bits each P0 and P2 can be used for external memory address lines. If no external memory then P0, P2 can be used as normal I/O ports. Lower order Address lines – on (P0.0 to P0.7)(A0 – A7) Higher order Address lines – (P2.0 to P2.7) (A8 – A15) P0 - lines also act as data lines – (D0 to D7) P1 – Act as normal I/O port. Also used for programming of internal memory of 8751.

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Port 3 – (P3) can be used as I/O port P3 pins have important alternate functions Serial input and output lines External timer input line External Data Memory Read and Write Control Signal External Interrupt Lines Serial Data Buffer (SBUF) – Holds data to be transmitted on serial lines Also holds data received from serial lines SBUF Receive Shift Register Transmit Shift Register 8051 Internal Bus

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SBUF is connected to two 8 bit shift registers For data output SBUF loaded to transmit shift register For data input Receive Shift Register loaded to SBUF Thus transmit and receive can take place at the same time. FULL Duplex Communication

Control and Status Registers: 

Control and Status Registers All SFR’s used for controlling the internal resources. or SFR’s used for knowing the status of resources - belong to this category IP – Interrupt Priority Register IE – Interrupt Enable Register TMOD – Timer Mode Register TCON – Timer Control Register SCON – Serial Control Register PCON – Power Control Register - Will be described along with the resources.

Internal Architecture of 8051: 

Internal Architecture of 8051

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Chip contains as internal bus connected to - 4 KB ROM - 128 byte internal Data RAM - SFR’s – ACC, B Reg , SP, DPTR, PSW, Status and Control Registers ALU – Connected to two temporary registers TMP1 and TMP2. – ACC connected to TMP2 as one operand is in ACC – PSW connected to ALU for status – For reading and writing to internal data RAM-RAM Address Register Stores the address(MAR) – Data read / written in ACC or Register-acts as (MBR)

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- Program Address Register Stores address of instruction to be read from Internal Program Memory (4KB) or External Program Memory That’s why it is connected to 4KB ROM and port 0 and port 2 pins Program counter and PC incrementer are connected to program address register. PC after incrementing is loaded to program address register for reading next instruction. Instruction Register and Instruction Decoder are part of Timing and control Block. For external data memory read/write DPTR is connected to port 0 and port 2 Data to be Written/Data read is transferred through P0 latch.

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Bidirectional Buffer is provided to temporarily store branch address as well as operand address. Bidirectional Ports P0 to P3 have port driver and port latch Driver is connected to port pins Latch is connected to internal bus of microprocessor. DPTR is interfaced to program address register. Plays major role in external program memory addressing ( MOVC instruction) and external data memory addressing (MOVX) instruction. Port P0 lines (P0.0 to P0.7) act both as lower address lines (A0 to A7) as well as data lines (D0 to D7) in time multiplex manner.

Information flow in - : 

Information flow in - 1. Instruction Read and Decode. PC Incrementer Program Address Register Port 0 – Port 2 Lines Internal Program Memory Fetched Instruction Instruction Register a b External Program Memory Port 0 Instruction Decoder

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e.g. MOV R1, # data above is repeated. However data is moved to specified Register or memory location. MOV direct, # data 2. Operand Read after 1. a 3. Operand Read after 1. e.g. MOV R1, direct 4. ADD A, R3 ACC TMP 2 R3 TMP 1 , ALU Status PSW ALU Result ACC , Direct Address RAM Address Register Operand is moved to register or address e.g. MOV direct, direct

5. MOVX, A, @DPTR: 

5. MOVX, A, @DPTR Specified Register DPTR Program Address Register Port 0, Port 2 lines External Data Memory Port 0

8051 pins & signals : 

8051 pins & signals

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Port 0 (AD0 – AD7) – 8 bit bidirectional port pins. Bit addressable pins Act as lower 8 lines of address bus as well as data lines in time multiplex manner, for external memory access. Has open collector output. Thus external pull up register is required. Port 1 – 8 bit bidirectional port pins with internal pull up register. Also has role during programming of 8751. Port 2(A8 – A15)- 8 bit bidirectional port pins with internal pull ups. Also acts as higher order address lines (A8 – A15) for external memory access. Also plays part in the programming of 8751.

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Port 3 – 8 bit bidirectional port pins with internal pull ups. port3 pins have important alternate function – P3.0 - RXD (Serial input) P3.1 - TXD (Serial output) P3.2 - INT0 (External interrupt) P3.3 - INT1 (External interrupt) P3.4 - T0 (Timer 0 external input) P3.5 - T1 (Timer 1 external input) P3.6 - WR (External data memory write strobe) P3.7 - RD (External data memory read strobe)

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ALE(output) – is sent when external memory address is present in P0 – P2. It can be used to latch the lower address byte from P0. PSEN(output) – Read control signal for program memory. EA(input) – Conveys to microprocessor whether 4KB ROM is on chip or external. EA = 0 (GND) – External EA = 1 (5V) – Internal RST(input) – Reset signal to reset microprocessor.

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VPD, VPP, PROG - are used for programming of EPROM in 8751. XTAL1, XTAL2 – pins for connecting crystal. VSS - Ground VCC – (5v) Power Original 8051 designed and manufacturered by Intel had frequency range 3.5 – 12 MHZ . With advancements in microelectronics technology, no. of facilities have been incorporated in addition to basic design . The frequency range has also improved. 8051 is now being produced by no. of firms. Different versions have different frequency range.

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The firms which produce 8051 visions apart form Intel are Dallas Semiconductor (maxim) - Flash memory version Atmel Corporations Philips Corporations (Incorporated A to D and D to A on chip) Frequency range of 8051 from Atmel Corporation include – - 12 MHz (AT 89C51 – 12 PC) - 16 MHz (AT 89C51 – 16 PC) - 20 MHz (AT 89C51 – 20 PC) The register contents when 8051 in reset. Commercial version Plastic DIP Package

Delay incorporation by software: 

Delay incorporation by software Original 8051 of Intel had 12 clock period machine cycle. Using frequency of clock and no. of machine cycles the time taken by any instruction can be determined. Example - clock frequency = 12 MHz - clock period = 1/12 microsecond - Time for 1 machine cycle = 12 x 1/12 = 1 microsecond

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ORG 00H m/cycle Time(µ sec) MOV R1, # 30H 1 1 MOV A, # 50H 1 1 INC A 1 1 MOV @R1, A 1 1 SJMP $ 4 4 - Apart from MUL and DIV all instructions take 12 or 24 clock period i.e. 1 or 2 machine cycles. - MUL and DIV take 48 clock period i.e. 4 machine cycles.

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DJNZ Rn , Label - takes 24 clock period i.e. 2m/c cycle. If frequency is 12 MHz, m/c cycle = 1 µ sec Execution time for DJNZ Rn , label = 2 µ sec INS1 DELAY INS2 Delay Routine must be executed for 1 second - To incorporate 1 second delay between two instructions INS1 and INS2.

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Rn can take maximum value of 255 one complete loop of will account for delay of 255 x 2 + 1 = 511 µ sec ≈ 2 9 µ sec - We may envelop it in another loop. MOV Rn , #0FFH DJNZ Rn , $ MOV Rm , # 0FFH DLY 1 : MOV Rn , # 0FFH DJNZ Rn , $ DJNZ Rm , DLY1 a

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Now will be executed 255 times ≈ 2 8 µ sec Total execution time of block = x 255 + ex. time for DJNZ Rm , DLY1 x 255 + ex. time for MOV Rm , # 0FFH x 255 + 2 x 255 + 1 = 511 x 255 + 511 ≈ 512 x 256 ≈ 2 17 µ sec Now 1 sec = 10 6 µ sec = 10 3 x 10 3 µ sec 10 3 ≈ 2 10 (1024) 1 sec = 2 20 µ sec a a a

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The above block should be executed 2 20 / 2 17 = 2 3 = 8 times. Thus to incorporate 2 sec. Delay - MOV R3, # 08H DLY 2 : MOV R4, # 0FFH DLY 1 : MOV R5, # 0FFH DJNZ R5, $ DJNZ R4, DLY1 DJNZ R3, DLY2

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It will be more than 1 sec by few milliseconds that can be ignored. These calculations are for 12MHz clock with 12 clock cycles 8051. The above block may be written as subroutine DELAY. DELAY : MOV R3, # 08H - - - - - - - DJNZ R3, DLY2 RET

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To incorporate 5 sec. Delay - ACALL DELAY ACALL DELAY ACALL DELAY ACALL DELAY ACALL DELAY Any amount of delay may be incorporated using this approach. You may use direct addressing instead of registers.

DELAY : MOV Direct 1, # 08H | | | | DJNZ Direct1, DLY2 RET : 

DELAY : MOV Direct 1, # 08H | | | | DJNZ Direct1, DLY2 RET - For 1 minute delay can be enveloped in a loop that executes 160 times i.e. 3CH times. x x

8051 Port Operation: 

8051 Port Operation The ports P0 to P3 are quasi bidirectional i.e. On reset the ports are configured as output. To configure any port line as input i.e. to receive data from outside world, 1 must be written to the pin. Example – To configure line 3 of port 2 as input SETB P2.3 instruction can be used. To configure the port for input operation 1 should be written to each pin of port.

Thus to configure P0 as input: 

Thus to configure P0 as input Port as output - To toggle pins of a port Pk between 0 and 1. REPET : MOV A, # 00H (k=0,1,2,3) MOV Pk , A ACALL DELAY MOV A, # 0FFH MOV Pk , A SJMP REPET MOV A, # 0FFH MOV P0, A SFR addressed For P0 – 80H P1 – 90H P2 – A0H P3 – B0H may be used.

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We may also toggle by writing 0AAH (10 10 1010) and 055H ( 0101 0101). Note both are complement of other. Port as input- MOV A, # 0FFH MOV R3, # 0FH; counter for 15 bytes to be received MOV Pk , A ; configure as input MOV R0, # 30H BACK : MOV A, Pk ; Receive input MOV @ R0, A ACALL DELAY INC R0 DJNZ R3, BACK

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Ports P1, P2, P3 have internal pull up registers in the form of FETS. Port P0 has no internal pull up register called open drain output. To utilize P0 as input or output external pull up register of 10K Ω must be connected to each pin.

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Port P0 is open drain since it has address and data in time multiplex way. P3 pins are used for alternate functions. If alternate functions are not required then P3 pins may be used for I/O operation like other ports. P0 – P2 may be used for external data memory or external program memory operation. Otherwise these may be used as normal ports.

Memory Interfacing: 

Memory Interfacing External Memory- External Data Memory – up to 64 KB Read Control Signal – RD (P3.7) Write Control Signal – WR(P3.6) External Program Memory - up to 60 KB (8051, 8751) EA=5V - up to 64 KB (8031) EA=0V Read Control Signal = PSEN

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Address is sent to memory through P0(Lower Address Byte) and P2(Higher Address Byte) Data is sent to/from memory through P0. P0 acts both as Lower address lines as well as data lines in time multiplexed manner. When Address is present, content of P0 must be latched , so that it can be used for data. Microprocessor sends a pulse on ALE when address is present.

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High to Low transition of ALE may be used to latch the address on a latch. The latch can be connected to memory to give lower address byte. P2 is directly connected to higher address lines of memory.

Two latch chips (octal latch) are popular: 

Two latch chips (octal latch) are popular - 74LS373 - 8282 (by Intel) Both have 8 input lines & 8 output lines 74LS373 8282 Input 1D to 8D DI0 to DI7 Output 1Q to 8Q DO0 to DO7 Tracking when Enable=1 when STB=1 Latching when Enable=0 when STB=0 Presenting when Enable OC=0 when OE=0 on output

IF 74LS373 is used to latch the lower address byte: 

IF 74LS373 is used to latch the lower address byte P0 – connected to input (1D to 8D) output (1Q to 8Q) connected to memory chip - Enable in connected to ALE. - Thus when ALE is high, input is tracked. Input is latched on high to low transition of ALE. - OC is connected to ground. Thus latched data is available at output immediately.

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Similarly for 8282 STB is connected to ALE OE is grounded. V CC (+ 5V) 1 20 2 19 3 18 4 17 5 8282 16 6 or 15 7 8283 14 8 13 9 12 10 11 DI 0 DI 1 DI 2 DI 3 DI 4 DI 5 DI 6 DI 7 OE GND DO 0 DO 1 DO 2 DO 3 DO 4 DO 5 DO 6 DO 7 STB The 8282/8283 pin diagram

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Input – DI0 to DI7 Output – DO0 to DO7 When STB = 1, Input is tracked = 0, Input is latched When Output Enable (OE) = 0, latched input is present on output.

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Thus one may use 8282 or 74LS373 octal latch. Both are equally effective. We shall now interface some memory chips to 8051. Memory chip Address range 2732/6132(1) 0000H to 0FFFH(4K) 2716/6116(2) 1000H to 17FFH (2K) 2716/6116(3) 1800H to 1FFFH(2K) 2716/6116(4) 2000H to 27FFH(2K)

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For memory interfacing we need to move in defined steps. Step 1 – Work out the address range (if not given) where the memory chips need to be connected. Step 2 – Write down the bit patterns of address range. A15----------------------------A0

Address Range of the Memory Chips: 

Address Range of the Memory Chips C B A A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = 0000H 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 = 0FFFH 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 = 1000H 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 = 17FFH 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 = 1800H 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 = 1FFFH 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = 2000H 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 = 27FFH 1 2 3 4

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Step 3 – Examine the memory size of chips to be connected. - The minimum size chip will decide the connections. If min. size is 2 K bytes. A0 – A10 get connected to memory chip. A11 to A, A12 to B, A13 to C. Examine other bits if zero on complete range of an chips then A14 to G2A A15 to G2B

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c. If min. size = 4KBytes then – A0 to A11 to memory chip A12 to A, A13 to B, A14 to C – If A15 = 0 for complete range then – A15 to G2A, GND to G2B d. If min. size = 8K bytes then – A0 to A12 to memory chips – A13 to A, A14 to B, A15 to C GND to G2A, GND to G2B

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e. If min. size = 16 K bytes then – A0 to A13 to memory chips A14 to A, A15 to B, GND to C GND to G2A, GND to G2B f. If min. size = 32 K bytes then A0 to A14 to memory chips A15 to A, B=C=G2A=G2B=GND g. For 64 K byte – 74LS138 not needed. A0 to A15 may be connected directly to memory chip.

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In the example – - min. address range = 2K bytes connect A0 to A10 to memory A15 A14 = 00 in the complete range. Connect - A14 to G2B - A15 to G2B - A13 to C - A12 to B - A11 to A

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Note – Since minimum range is 2K byte and connection is w.r . to 2K byte each increment in CBA i.e. Y0, Y1 --- correspond to 2KB range. Thus for any chip with 4KB range 2 output lines of 74LS138 will be activated. Maximum memory that can be interfaced using one 74LS138 decoder = 2K x 8 = 16K bytes

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G2B G2A C B A | | | | | | | | | | A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 =0 -> Y0 is activated =7FFFH=(2KB) 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 = 0800H 2KB 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 = 0FFFH = 1 -> Y1 is activated

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Memory chip 1 has range of 4KB. Address range has CBA = 000 and 001 . Thus both Y0 and Y1 are activated. CS of memory chip Y0 and Y1 are Anded

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For memory chip 2, Y2 will be activated. Similarly for memory chips 3 and 4, Y3 and Y4 will be activated. Thus the 8051 interfacing circuit to these memory chips will look like.

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If these memory chips are for external data memory. WR – write control signal (P3.6) RD – read control signal (P3.7) Software instruction- MOVX If there address range are for external program memory then it with look like

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PSEN = Read Control Signal. (You can’t write to program memory) Software instruction – MOVC You may also combine external program and data memory in to one single external memory space (total 64K) which will serve both data as well as program.

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Your space gets limited to total (64 KB) You may write as well as read in to space using. MOVX and MOVC instructions Thus you can write in to program memory space to perform program modifications.

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The 8051 – memory interface will look like

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WR – write control signal PSEN AND RD – Read Control Signal Thus either PSEN (MOVC instruction) or RD (MOVX instruction) can be used to perform read operation. Write operation will be performed using WR (MOVX instruction).

-> Let us now consider different variations. : 

-> Let us now consider different variations. If memory space is for both program and data memory. Then- Let us say memory chip address 1 for program memory, whereas 2, 3 and 4 for data memory. Interface will look like Fig 25A PSEN used for chip 1 i.e. 2732 RD, WR used for others. Note- the same 74LS138 decoder has been used

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2. If there are gaps in memory space Let us say we wish to interface only Chips 1 and 3 at memory address space shown in following tow figures.

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In this case following will be changes in the interfacing circuits- - Memory chips 2 and 4 will not be present. - Y2 an Y4 output lines of 74LS138 will not be used. (These lines must be grounded) Rest of the circuit will be same.

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Example- Following memory chips to be interfaced for given address space 2764- A000H to BFFFH 2764- E000H to FFFFH Note: There is gap between two address space. Also the two address spaces are towards the end of 64KB space. a is from 40 to 48KB and b is from 56 KB to 64 KB.

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Step1- Work out address space range (if not given) where memory chips need to be connected. - Given. Step2- Write down bit pattern of address range. 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 a b

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As given above for 8KB range or higher memory chips – A0 to A12 to memory Address bits 74LS138 pins. A15 to C A14 to B A13 to A Since all bits are used for memory address and C B A.

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G2B and G2A are connected to Ground G1 is connected to 5V. Now – for chip a C B A = 101 ---> Y5 will be activated for chip b C B A = 111 ---> Y7 will be activated

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These will be connected to chip select pins of corresponding memory chips, Y0 to Y4 and Y6 must be grounded. A0 to A7 i.e. (P0 pins) will be latched and latched address will be connected to memory address pins A0 to A7 A8 to A12 (P2) will be connected directly to memory address pins A8 to A12.