Asynchronous Seq Circuits_dsd

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ASYNCHRONOUS SEQUENTIAL CIRCUITS:

ASYNCHRONOUS SEQUENTIAL CIRCUITS Prepared & Presented By: Anamika Gupta Assistant Professor RKGIT,Gzb

Why we go for Asynchronous sequential circuit???:

Why we go for Asynchronous sequential circuit???

Synchronous sequential circuits:

Synchronous sequential circuits State changes synchronized by the common clock pulse. Input changes occur between clock pulse. Outputs are read during the clock pulse. Thus the output and input must be in synchronization with the clock pulse.

Problem with synchronous circuit:

Problem with synchronous circuit As design system have grown in complexity and clock speeds are constantly increasing, several limitation of synchronous design have begun to be noticed. Some main problem with sequential circuit Clock skew Interfacing difficulties Power dissipation

Asynchronous sequential circuits:

Asynchronous sequential circuits It is therefore not a surprise that the area of asynchronous circuit and system which generally do not suffer from these problem are developing day by day. Within large synchronous systems, it is often desirable to allow certain subsystems to operate asynchronously to reduce delay and power consumption.

Asynchronous sequential circuits:

Asynchronous sequential circuits Difficult to design An unclocked FF or time delay element is used as memory element. Faster as the clock is not present. The status of memory element will change any time as soon as the input is changed.

Asynchronous Sequential Circuits. :

Asynchronous Sequential Circuits . Asynchronous Sequential Circuits consist of a combinational circuit and delay elements connected to from feedback loops. Delay elements x1,x2… are the n input variables. z1,z2 ..are the m output variables .

Total state :

x1,x2..xn are called input state variable. The combination of the output of the memory element are known as secondary state variable, also called present state(y1,y2..) Y1,Y2 are the excitation variable also called next state. The combination of both input state and secondary state is known as TOTAL state. TOTAL state= (x1,x2,y1,y2) Total state

Stable state:

Stable state : for a given input state, the circuit is said to be in a stable state if and only if y i = Y i for i = 1, 2, …, k. A stable total state is a combination of internal state and input state such that the next internal state predicted by the transaction table is the same as the current internal state and if different then called unstable state. Stable state

Fundamental mode:

Fundamental mode when a change in input values has occurred, no other change in any input value occurs until the circuit enters a stable state. Single-input change a single input value is allowed to change at a time.

Analysis:

Analysis

Transition table:

Transition table

Output table:

Output table

Flow table :

Flow table

Flow table:

Flow table Flow table in which states are named by letter symbols. flow table 2 This table is called a primitive flow table Because it has only one stable state in each row. Can also have a flow table with more than one stable state in the same row. flow table 1

Reduction of primitive flow table :

Reduction of primitive flow table

Slide 18:

Reduction of flow table to a minimum number of numbers of rows. Reduce the number of state variable. Reduce the amount of logic required. First a minimum row primitive flow table is found and then this table is further reducing by merging rows.

Example 1:

Example 1 C/1 B/0 D/0 E/1 A/0 F/1 0 0 0 0 0 0 x x x x y y y y

Flow Table:

Flow Table 1 - F - A F 1 - - E A E 0 - F E D D 1 - C - A C 0 - - B D B 0 - C B A A Z xy = 11 xy = 10 xy = 01 xy = 00 Output Next State Present State

Minimum row primitive flow table:

Minimum row primitive flow table Firstly eliminate redundant stable total states. Two stable tatal states are equivalent if Their inputs are same . Their outputs are the same. Their next states are equivalent for each possible next input.

State Reduction:

State Reduction Partitioning Procedure: State A and D are stable under input xy = 00 and producing output 0. They also have the unspecified entries in the same position. And for C F it is same under xy = 10. Initial partitioning is P1 = (A,D) (B) (C,F) (E) The successor of A and D are (A,D) for xy = 00 (B,E) for xy = 01 (C,F) for xy = 10 P2 = (A) (D) (B) (C,F)(E)

Reduced Table:

Reduced Table Because C = F, so F is replaced by C 1 - - E A E 0 - F C E D D 1 - C - A C 0 - - B D B 0 - C B A A Z xy = 11 xy = 10 xy = 01 xy = 00 Output Next State Present State

Example 2:

Example 2 0 - C E F F 0 H - G D G 1 H C G - H 0 H - E A E 1 - C G D D 0 H C - F C 0 H - B F B 0 - C B A A Z xy = 11 xy = 10 xy = 01 xy = 00 Output Next State Present State

Slide 25:

P1=(AF)(BEG)(C)(D)(H) P2=(AF)(BE)(G)(C)(D)(H) P3=P2

Flow Table:

Flow Table 1 H C G - H 0 H - G D G 1 - C G D D 0 H C - A C 0 H - B A B 0 - C B A A Z xy = 11 xy = 10 xy = 01 xy = 00 Output Next State Present State

Merger Diagram:

Merger Diagram

Slide 28:

Merger diagram is prepared for a primitive flow table to determine all the possible compatible states(maximal compatible state). From this a minimal collection of compatibles covering all the states. Merger Diagram

Merger Diagram:

Merger Diagram A B C H D G

Flow Table:

Flow Table 1 - xy = 11 - 0 xy = 10 0 0 xy = 01 1 0 xy = 00 Output D D xy = 11 - D D D A A A A xy = 10 xy = 01 xy = 00 Next State Present State

Slide 31:

Designing of Asynchronous circuits

Designing Asynchronous circuits:

Designing Asynchronous circuits Flow table is obtained from design specification. Reduce the primitive flow table by eliminating the redundant state. These redundant states are eliminating by merging the state, Merger Diagram is used for this. Binary numbers are assigned to the states in the reduced flow table. The binary state assignment must be made to ensure that the circuit will be free of critical races. Transition table is obtained. From the transition table logic diagram is designed by using the combinational design methods.

Asynchronous design problem:

Asynchronous design problem Design an asynchronous sequential circuit that has two input X1 and X2 and one output Z.The first change in X2 that occurs while X1 is a 1 will cause Z to be a 1 until X1 returns to 0.

Slide 34:

X2 X1 Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 a d f b a f b a c e

Slide 35:

f , 1 e , 1 - , - a , - f f , 1 e , 1 b , - - , - e f , - d , 0 b , 0 - , - d c , 0 e , - - , - a , 0 c - , - d , 0 b , 0 a , 0 b c , 0 - , - b , 0 a , 0 a 10 11 01 00 X 1 X 2 Present State Flow table

Merger diagram from the flow table:

Merger diagram from the flow table ROW-1(state a) a,b are compatible a,c are compatible a,d are compatible if c,f are compatible a,e are compatible if c,f are compatible a,f are compatible if c,f are compatible ROW-2(state b) b,c are compatible if d,e are compatible b,d are compatible b,e are not compatible b,f are not compatible

Slide 37:

ROW-3(state c) c,d are compatible if e,d and c,f are compatible c,e are compatible c,f are not compatible ROW-4(state d) d,e are not compatible d,f are not compatible ROW-5(state e) e,f are not compatible

Slide 38:

In the flow table there are total six stable state. Solid arcs are drawn between (a,b),(a,c),(b,d)and(f,e),because they are maximum compatible pairs. (c,f) and (d,e)are not compatible, therefore there are no implied pair available.

Slide 39:

f e a b c d Merger Diagram

Slide 40:

Now (a,b) is covered by (a,c) and (b,d) therefore, the minimal set is (a,c),(b,d),(e,f) From the merger diagram ,we have obtained three pairs of compatible states. These compatibles are merged together and are represented by a,c: S0 b,d: S1 e,f: S2

Slide 41:

S2 , 1 S1 , 0 S2 , - 11 S2 , 1 S1 , - S0 , - S2 S2 , - S1 , 0 S0 , 0 S1 S0 , 0 S1 , 0 S0 , 0 S0 10 01 00 X 1 X 2 Present State Reduced flow table

Slide 42:

11 , 1 11 , 1 01 , - 00 , - 11 01 , 0 11 , - 11 10 11 , - 01 , 0 00 , 0 01 00 , 0 01 , 0 00 , 0 00 10 01 00 X 1 X 2 Q 1 Q 2 Transition table

Slide 43:

Remove if critical races are there. assign the following binary states to S0,SI,S2 S0=00 S1=01 S2=11 From stable state 00 to unstable state 11 when X1 X2 changes from 10 to 00. From stable state 00 to unstable state 11 when X1 X2 changes from 10 to 00.

Slide 44:

11 , 1 11 , 1 01 , - 00 , - 11 01 , 0 11 , - 11 10 11 , - 01 , 0 00 , 0 01 00 , 0 01 , 0 00 , 0 00 10 01 00 X 1 X 2 Q 1 Q 2 Transition table

Slide 45:

Q 1 Q 2 X 1 X 2 00 01 11 10 00 00 , 0 01 , 0 10 , - 00 , 0 01 00 , 0 01 , 0 01 , 0 11 , - 11 10 , - 01 , - 11 , 1 11 , 1 10 00 , - - , - 11 , - - , - Modified Transition table

Slide 46:

K-map for Q 1 + 1 1 0 1 11 1 0 0 0 01 x 1 x 0 10 0 1 0 0 00 10 11 01 00 X 1 X 2 Q 1 Q 2

Slide 47:

K-map for Q 2 + 1 1 1 0 11 1 1 1 0 01 x 1 x 0 10 0 0 1 0 00 10 11 01 00 X 1 X 2 Q 1 Q 2

Slide 48:

K-map for Y 1 1 x x 11 x 0 0 0 01 x x x x 10 0 x 0 0 00 10 11 01 00 X 1 X 2 Q 1 Q 2

Slide 49:

From the k-maps, we obtain, Q 1 = X 1 X 2 Q 2 ’ + X 2 Q 1 Q 2 + X 1 X 2 ’Q 2 + X 1 Q 1 Q 2 = X 1 ’X 2 + X 1 Q 2 + X 1 Q 1 Y = Q 1

Slide 50:

So here we can see that an asynchronous circuit is preferred over synchronous circuit ,when high speed of operation is required. Since asynchronous sequential circuits respond immediately whenever there is a change in any input variable without having to wait for a close pulse. They are useful in applications in which input signals may change at any time. Also cost less than the sequential circuits, therefore, for economical reasons, they find useful applications.

Thank You:

Thank You

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