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See all Premium member Presentation Transcript CMOS VLSI Design : Digital Design Slide 1 CMOS VLSI Design Digital Design Overview : Digital Design Slide 2 Overview Physical principles Combinational logic Sequential logic Datapath Memories Trends Dopants : Digital Design Slide 3 Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) nMOS Operation : Digital Design Slide 4 nMOS Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF Transistors as Switches : Digital Design Slide 5 Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain CMOS Inverter : Digital Design Slide 6 CMOS Inverter Inverter Cross-section : Digital Design Slide 7 Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors Inverter Mask Set : Digital Design Slide 8 Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line Fabrication Steps : Digital Design Slide 9 Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2 Oxidation : Digital Design Slide 10 Oxidation Grow SiO2 on top of Si wafer 900 – 1200 C with H2O or O2 in oxidation furnace Photoresist : Digital Design Slide 11 Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light Lithography : Digital Design Slide 12 Lithography Expose photoresist through n-well mask Strip off exposed photoresist Etch : Digital Design Slide 13 Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed Strip Photoresist : Digital Design Slide 14 Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step n-well : Digital Design Slide 15 n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si Simplified Design Rules : Digital Design Slide 16 Simplified Design Rules Conservative rules to get you started Complementary CMOS : Digital Design Slide 17 Complementary CMOS Complementary CMOS logic gates nMOS pull-down network pMOS pull-up network a.k.a. static CMOS Example: NAND3 : Digital Design Slide 18 Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 l by 40 l I-V Characteristics : Digital Design Slide 19 I-V Characteristics In Linear region, Ids depends on How much charge is in the channel? How fast is the charge moving? Channel Charge : Digital Design Slide 20 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate – oxide – channel Qchannel = CV C = Cg = eoxWL/tox = CoxWL V = Vgc – Vt = (Vgs – Vds/2) – Vt Cox = eox / tox Carrier velocity : Digital Design Slide 21 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = mE m called mobility E = Vds/L Time for carrier to cross channel: t = L / v nMOS Linear I-V : Digital Design Slide 22 nMOS Linear I-V Now we know How much charge Qchannel is in the channel How much time t each carrier takes to cross Example : Digital Design Slide 23 Example Example: a 0.6 mm process from AMI semiconductor tox = 100 Å m = 350 cm2/V*s Vt = 0.7 V Plot Ids vs. Vds Vgs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2 l Capacitance : Digital Design Slide 24 Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion Gate Capacitance : Digital Design Slide 25 Gate Capacitance Approximate channel as connected to source Cgs = eoxWL/tox = CoxWL = CpermicronW Cpermicron is typically about 2 fF/mm Diffusion Capacitance : Digital Design Slide 26 Diffusion Capacitance Csb, Cdb Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to Cg for contacted diff ½ Cg for uncontacted Varies with process RC Delay Model : Digital Design Slide 27 RC Delay Model Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width Introduction : Digital Design Slide 28 Introduction Chips are mostly made of wires called interconnect In stick diagram, wires set size Transistors are little things under the wires Many layers of wires Wires are as important as transistors Speed Power Noise Alternating layers run orthogonally Wire Capacitance : Digital Design Slide 29 Wire Capacitance Wire has capacitance per unit length To neighbors To layers above and below Ctotal = Ctop + Cbot + 2Cadj Lumped Element Models : Digital Design Slide 30 Lumped Element Models Wires are a distributed system Approximate with lumped element models 3-segment p-model is accurate to 3% in simulation L-model needs 100 segments for same accuracy! Use single segment p-model for Elmore delay Crosstalk : Digital Design Slide 31 Crosstalk A capacitor does not like to change its voltage instantaneously. A wire has high capacitance to its neighbor. When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too. Called capacitive coupling or crosstalk. Crosstalk effects Noise on nonswitching wires Increased delay on switching wires Coupling Waveforms : Digital Design Slide 32 Coupling Waveforms Simulated coupling for Cadj = Cvictim Introduction : Digital Design Slide 33 Introduction What makes a circuit fast? I = C dV/dt -> tpd (C/I) DV low capacitance high current small swing Logical effort is proportional to C/I pMOS are the enemy! High capacitance for a given current Can we take the pMOS capacitance off the input? Various circuit families try to do this… Pseudo-nMOS : Digital Design Slide 34 Pseudo-nMOS In the old days, nMOS processes had no pMOS Instead, use pull-up transistor that is always ON In CMOS, use a pMOS that is always ON Ratio issue Make pMOS about ¼ effective strength of pulldown network Dynamic Logic : Digital Design Slide 35 Dynamic Logic Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate Pass Transistor Circuits : Digital Design Slide 36 Pass Transistor Circuits Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates CMOS + Transmission Gates: 2-input multiplexer Gates should be restoring Sequencing : Digital Design Slide 37 Sequencing Combinational logic output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline Sequencing Overhead : Digital Design Slide 38 Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence Sequencing Elements : Digital Design Slide 39 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, D latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, D flip-flop, D register Timing Diagrams Transparent Opaque Edge-trigger Latch Design : Digital Design Slide 40 Latch Design Buffered output + No backdriving Widely used in standard cells + Very robust (most important) Rather large Rather slow (1.5 – 2 FO4 delays) High clock loading Sequencing Methods : Digital Design Slide 41 Sequencing Methods Flip-flops 2-Phase Latches Pulsed Latches Summary : Digital Design Slide 42 Summary Flip-Flops: Very easy to use, supported by all tools 2-Phase Transparent Latches: Lots of skew tolerance and time borrowing Pulsed Latches: Fast, some skew tol & borrow, hold time risk Full Adder Design I : Digital Design Slide 43 Full Adder Design I Brute force implementation from eqns Carry-Skip Adder : Digital Design Slide 44 Carry-Skip Adder Carry-ripple is slow through all N stages Carry-skip allows carry to skip over groups of n bits Decision based on n-bit propagate signal Tree Adder : Digital Design Slide 45 Tree Adder If lookahead is good, lookahead across lookahead! Recursive lookahead gives O(log N) delay Many variations on tree adders Memory Arrays : Digital Design Slide 46 Memory Arrays Array Architecture : Digital Design Slide 47 Array Architecture 2n words of 2m bits each If n >> m, fold by 2k into fewer rows of more columns Good regularity – easy to design Very high density if good cells are used 6T SRAM Cell : Digital Design Slide 48 6T SRAM Cell Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters Read: Precharge bit, bit_b Raise wordline Write: Drive data onto bit, bit_b Raise wordline SRAM Sizing : Digital Design Slide 49 SRAM Sizing High bitlines must not overpower inverters during reads But low bitlines must write new value into cell Decoders : Digital Design Slide 50 Decoders n:2n decoder consists of 2n n-input AND gates One needed for each row of memory Build AND from NAND or NOR gates Static CMOS Pseudo-nMOS Decoder Layout : Digital Design Slide 51 Decoder Layout Decoders must be pitch-matched to SRAM cell Requires very skinny gates Sense Amplifiers : Digital Design Slide 52 Sense Amplifiers Bitlines have many cells attached Ex: 32-kbit SRAM has 256 rows x 128 cols 128 cells on each bitline tpd (C/I) DV Even with shared diffusion contacts, 64C of diffusion capacitance (big C) Discharged slowly through small transistors (small I) Sense amplifiers are triggered on small voltage swing (reduce DV) Queues : Digital Design Slide 53 Queues Queues allow data to be read and written at different rates. Read and write each use their own clock, data Queue indicates whether it is full or empty Build with SRAM and read/write counters (pointers) CAMs : Digital Design Slide 54 CAMs Extension of ordinary memory (e.g. SRAM) Read and write memory as usual Also match to see which words contain a key 10T CAM Cell : Digital Design Slide 55 10T CAM Cell Add four match transistors to 6T SRAM 56 x 43 l unit cell CAM Cell Operation : Digital Design Slide 56 CAM Cell Operation Read and write like ordinary SRAM For matching: Leave wordline low Precharge matchlines Place key on bitlines Matchlines evaluate Miss line Pseudo-nMOS NOR of match lines Goes high if no words match ROM Example : Digital Design Slide 57 ROM Example 4-word x 6-bit ROM Represented with dot diagram Dots indicate 1’s in ROM Word 0: 010101 Word 1: 011001 Word 2: 100101 Word 3: 101010 Looks like 6 4-input pseudo-nMOS NORs PLAs : Digital Design Slide 58 PLAs A Programmable Logic Array performs any function in sum-of-products form. Literals: inputs & complements Products / Minterms: AND of literals Outputs: OR of Minterms Example: Full Adder PLA Schematic & Layout : Digital Design Slide 59 PLA Schematic & Layout Ideal nMOS I-V Plot : Digital Design Slide 60 Ideal nMOS I-V Plot 180 nm TSMC process Ideal Models b = 155(W/L) mA/V2 Vt = 0.4 V VDD = 1.8 V Simulated nMOS I-V Plot : Digital Design Slide 61 Simulated nMOS I-V Plot 180 nm TSMC process BSIM 3v3 SPICE models What differs? Less ON current No square law Current increases in saturation Velocity Saturation : Digital Design Slide 62 Velocity Saturation We assumed carrier velocity is proportional to E-field v = mElat = mVds/L At high fields, this ceases to be true Carriers scatter off atoms Velocity reaches vsat Electrons: 6-10 x 106 cm/s Holes: 4-8 x 106 cm/s Better model Channel Length Modulation : Digital Design Slide 63 Channel Length Modulation Reverse-biased p-n junctions form a depletion region Region between n and p with no carriers Width of depletion Ld region grows with reverse bias Leff = L – Ld Shorter Leff gives more current Ids increases with Vds Even in saturation Body Effect : Digital Design Slide 64 Body Effect Vt: gate voltage necessary to invert channel Increases if source voltage increases because source is connected to the channel Increase in Vt with Vs is called the body effect OFF Transistor Behavior : Digital Design Slide 65 OFF Transistor Behavior What about current in cutoff? Simulated results What differs? Current doesn’t go to 0 in cutoff Leakage Sources : Digital Design Slide 66 Leakage Sources Subthreshold conduction Transistors can’t abruptly turn ON or OFF Junction leakage Reverse-biased PN junction diode current Gate leakage Tunneling through ultrathin gate dielectric Subthreshold leakage is the biggest source in modern transistors Low Power Design : Digital Design Slide 67 Low Power Design Reduce dynamic power a: clock gating, sleep mode C: small transistors (esp. on clock), short wires VDD: lowest suitable voltage f: lowest suitable frequency Reduce static power Selectively use ratioed circuits Selectively use low Vt devices Leakage reduction: stacked devices, body bias, low temperature Chip-to-Package Bonding : Digital Design Slide 68 Chip-to-Package Bonding Traditionally, chip is surrounded by pad frame Metal pads on 100 – 200 mm pitch Gold bond wires attach pads to package Lead frame distributes signals in package Metal heat spreader helps with cooling Bidirectional Pads : Digital Design Slide 69 Bidirectional Pads Combine input and output pad Need tristate driver on output Use enable signal to set direction Optimized tristate avoids huge series transistors Device Scaling : Digital Design Slide 70 Device Scaling Interconnect Delay : Digital Design Slide 71 Interconnect Delay Introduction toCMOS VLSIDesignLecture 14: CAMs, ROMs, and PLAs : Introduction toCMOS VLSIDesignLecture 14: CAMs, ROMs, and PLAs David Harris Harvey Mudd College Spring 2004 Outline : 14: CAMs, ROMs, and PLAs Slide 73 Outline Content-Addressable Memories Read-Only Memories Programmable Logic Arrays CAMs : 14: CAMs, ROMs, and PLAs Slide 74 CAMs Extension of ordinary memory (e.g. SRAM) Read and write memory as usual Also match to see which words contain a key 10T CAM Cell : 14: CAMs, ROMs, and PLAs Slide 75 10T CAM Cell Add four match transistors to 6T SRAM 56 x 43 l unit cell CAM Cell Operation : 14: CAMs, ROMs, and PLAs Slide 76 CAM Cell Operation Read and write like ordinary SRAM For matching: Leave wordline low Precharge matchlines Place key on bitlines Matchlines evaluate Miss line Pseudo-nMOS NOR of match lines Goes high if no words match Read-Only Memories : 14: CAMs, ROMs, and PLAs Slide 77 Read-Only Memories Read-Only Memories are nonvolatile Retain their contents when power is removed Mask-programmed ROMs use one transistor per bit Presence or absence determines 1 or 0 ROM Example : 14: CAMs, ROMs, and PLAs Slide 78 ROM Example 4-word x 6-bit ROM Represented with dot diagram Dots indicate 1’s in ROM Word 0: 010101 Word 1: 011001 Word 2: 100101 Word 3: 101010 Looks like 6 4-input pseudo-nMOS NORs ROM Array Layout : 14: CAMs, ROMs, and PLAs Slide 79 ROM Array Layout Unit cell is 12 x 8 l (about 1/10 size of SRAM) Row Decoders : 14: CAMs, ROMs, and PLAs Slide 80 Row Decoders ROM row decoders must pitch-match with ROM Only a single track per word! Complete ROM Layout : 14: CAMs, ROMs, and PLAs Slide 81 Complete ROM Layout PROMs and EPROMs : 14: CAMs, ROMs, and PLAs Slide 82 PROMs and EPROMs Programmable ROMs Build array with transistors at every site Burn out fuses to disable unwanted transistors Electrically Programmable ROMs Use floating gate to turn off unwanted transistors EPROM, EEPROM, Flash Building Logic with ROMs : 14: CAMs, ROMs, and PLAs Slide 83 Building Logic with ROMs Use ROM as lookup table containing truth table n inputs, k outputs requires __ words x __ bits Changing function is easy – reprogram ROM Finite State Machine n inputs, k outputs, s bits of state Build with ________ bit ROM and ____ bit reg Building Logic with ROMs : 14: CAMs, ROMs, and PLAs Slide 84 Building Logic with ROMs Use ROM as lookup table containing truth table n inputs, k outputs requires 2n words x k bits Changing function is easy – reprogram ROM Finite State Machine n inputs, k outputs, s bits of state Build with 2n+s x (k+s) bit ROM and (k+s) bit reg Example: RoboAnt : 14: CAMs, ROMs, and PLAs Slide 85 Example: RoboAnt Let’s build an Ant Sensors: Antennae (L,R) – 1 when in contact Actuators: Legs Forward step F Ten degree turns TL, TR Goal: make our ant smart enough to get out of a maze Strategy: keep right antenna on wall (RoboAnt adapted from MIT 6.004 2002 OpenCourseWare by Ward and Terman) L R Lost in space : 14: CAMs, ROMs, and PLAs Slide 86 Lost in space Action: go forward until we hit something Initial state Bonk!!! : 14: CAMs, ROMs, and PLAs Slide 87 Bonk!!! Action: turn left (rotate counterclockwise) Until we don’t touch anymore A little to the right : 14: CAMs, ROMs, and PLAs Slide 88 A little to the right Action: step forward and turn right a little Looking for wall Then a little to the right : 14: CAMs, ROMs, and PLAs Slide 89 Then a little to the right Action: step and turn left a little, until not touching Whoops – a corner! : 14: CAMs, ROMs, and PLAs Slide 90 Whoops – a corner! Action: step and turn right until hitting next wall Simplification : 14: CAMs, ROMs, and PLAs Slide 91 Simplification Merge equivalent states where possible State Transition Table : 14: CAMs, ROMs, and PLAs Slide 92 State Transition Table Lost RCCW Wall1 Wall2 ROM Implementation : 14: CAMs, ROMs, and PLAs Slide 93 ROM Implementation 16-word x 5 bit ROM ROM Implementation : 14: CAMs, ROMs, and PLAs Slide 94 ROM Implementation 16-word x 5 bit ROM PLAs : 14: CAMs, ROMs, and PLAs Slide 95 PLAs A Programmable Logic Array performs any function in sum-of-products form. Literals: inputs & complements Products / Minterms: AND of literals Outputs: OR of Minterms Example: Full Adder NOR-NOR PLAs : 14: CAMs, ROMs, and PLAs Slide 96 NOR-NOR PLAs ANDs and ORs are not very efficient in CMOS Dynamic or Pseudo-nMOS NORs are very efficient Use DeMorgan’s Law to convert to all NORs PLA Schematic & Layout : 14: CAMs, ROMs, and PLAs Slide 97 PLA Schematic & Layout PLAs vs. ROMs : 14: CAMs, ROMs, and PLAs Slide 98 PLAs vs. ROMs The OR plane of the PLA is like the ROM array The AND plane of the PLA is like the ROM decoder PLAs are more flexible than ROMs No need to have 2n rows for n inputs Only generate the minterms that are needed Take advantage of logic simplification Example: RoboAnt PLA : 14: CAMs, ROMs, and PLAs Slide 99 Example: RoboAnt PLA Convert state transition table to logic equations RoboAnt Dot Diagram : 14: CAMs, ROMs, and PLAs Slide 100 RoboAnt Dot Diagram RoboAnt Dot Diagram : 14: CAMs, ROMs, and PLAs Slide 101 RoboAnt Dot Diagram You do not have the permission to view this presentation. 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See all Premium member Presentation Transcript CMOS VLSI Design : Digital Design Slide 1 CMOS VLSI Design Digital Design Overview : Digital Design Slide 2 Overview Physical principles Combinational logic Sequential logic Datapath Memories Trends Dopants : Digital Design Slide 3 Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) nMOS Operation : Digital Design Slide 4 nMOS Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF Transistors as Switches : Digital Design Slide 5 Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain CMOS Inverter : Digital Design Slide 6 CMOS Inverter Inverter Cross-section : Digital Design Slide 7 Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors Inverter Mask Set : Digital Design Slide 8 Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line Fabrication Steps : Digital Design Slide 9 Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2 Oxidation : Digital Design Slide 10 Oxidation Grow SiO2 on top of Si wafer 900 – 1200 C with H2O or O2 in oxidation furnace Photoresist : Digital Design Slide 11 Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light Lithography : Digital Design Slide 12 Lithography Expose photoresist through n-well mask Strip off exposed photoresist Etch : Digital Design Slide 13 Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed Strip Photoresist : Digital Design Slide 14 Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step n-well : Digital Design Slide 15 n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si Simplified Design Rules : Digital Design Slide 16 Simplified Design Rules Conservative rules to get you started Complementary CMOS : Digital Design Slide 17 Complementary CMOS Complementary CMOS logic gates nMOS pull-down network pMOS pull-up network a.k.a. static CMOS Example: NAND3 : Digital Design Slide 18 Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 l by 40 l I-V Characteristics : Digital Design Slide 19 I-V Characteristics In Linear region, Ids depends on How much charge is in the channel? How fast is the charge moving? Channel Charge : Digital Design Slide 20 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate – oxide – channel Qchannel = CV C = Cg = eoxWL/tox = CoxWL V = Vgc – Vt = (Vgs – Vds/2) – Vt Cox = eox / tox Carrier velocity : Digital Design Slide 21 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = mE m called mobility E = Vds/L Time for carrier to cross channel: t = L / v nMOS Linear I-V : Digital Design Slide 22 nMOS Linear I-V Now we know How much charge Qchannel is in the channel How much time t each carrier takes to cross Example : Digital Design Slide 23 Example Example: a 0.6 mm process from AMI semiconductor tox = 100 Å m = 350 cm2/V*s Vt = 0.7 V Plot Ids vs. Vds Vgs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2 l Capacitance : Digital Design Slide 24 Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion Gate Capacitance : Digital Design Slide 25 Gate Capacitance Approximate channel as connected to source Cgs = eoxWL/tox = CoxWL = CpermicronW Cpermicron is typically about 2 fF/mm Diffusion Capacitance : Digital Design Slide 26 Diffusion Capacitance Csb, Cdb Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to Cg for contacted diff ½ Cg for uncontacted Varies with process RC Delay Model : Digital Design Slide 27 RC Delay Model Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width Introduction : Digital Design Slide 28 Introduction Chips are mostly made of wires called interconnect In stick diagram, wires set size Transistors are little things under the wires Many layers of wires Wires are as important as transistors Speed Power Noise Alternating layers run orthogonally Wire Capacitance : Digital Design Slide 29 Wire Capacitance Wire has capacitance per unit length To neighbors To layers above and below Ctotal = Ctop + Cbot + 2Cadj Lumped Element Models : Digital Design Slide 30 Lumped Element Models Wires are a distributed system Approximate with lumped element models 3-segment p-model is accurate to 3% in simulation L-model needs 100 segments for same accuracy! Use single segment p-model for Elmore delay Crosstalk : Digital Design Slide 31 Crosstalk A capacitor does not like to change its voltage instantaneously. A wire has high capacitance to its neighbor. When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too. Called capacitive coupling or crosstalk. Crosstalk effects Noise on nonswitching wires Increased delay on switching wires Coupling Waveforms : Digital Design Slide 32 Coupling Waveforms Simulated coupling for Cadj = Cvictim Introduction : Digital Design Slide 33 Introduction What makes a circuit fast? I = C dV/dt -> tpd (C/I) DV low capacitance high current small swing Logical effort is proportional to C/I pMOS are the enemy! High capacitance for a given current Can we take the pMOS capacitance off the input? Various circuit families try to do this… Pseudo-nMOS : Digital Design Slide 34 Pseudo-nMOS In the old days, nMOS processes had no pMOS Instead, use pull-up transistor that is always ON In CMOS, use a pMOS that is always ON Ratio issue Make pMOS about ¼ effective strength of pulldown network Dynamic Logic : Digital Design Slide 35 Dynamic Logic Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate Pass Transistor Circuits : Digital Design Slide 36 Pass Transistor Circuits Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates CMOS + Transmission Gates: 2-input multiplexer Gates should be restoring Sequencing : Digital Design Slide 37 Sequencing Combinational logic output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline Sequencing Overhead : Digital Design Slide 38 Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence Sequencing Elements : Digital Design Slide 39 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, D latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, D flip-flop, D register Timing Diagrams Transparent Opaque Edge-trigger Latch Design : Digital Design Slide 40 Latch Design Buffered output + No backdriving Widely used in standard cells + Very robust (most important) Rather large Rather slow (1.5 – 2 FO4 delays) High clock loading Sequencing Methods : Digital Design Slide 41 Sequencing Methods Flip-flops 2-Phase Latches Pulsed Latches Summary : Digital Design Slide 42 Summary Flip-Flops: Very easy to use, supported by all tools 2-Phase Transparent Latches: Lots of skew tolerance and time borrowing Pulsed Latches: Fast, some skew tol & borrow, hold time risk Full Adder Design I : Digital Design Slide 43 Full Adder Design I Brute force implementation from eqns Carry-Skip Adder : Digital Design Slide 44 Carry-Skip Adder Carry-ripple is slow through all N stages Carry-skip allows carry to skip over groups of n bits Decision based on n-bit propagate signal Tree Adder : Digital Design Slide 45 Tree Adder If lookahead is good, lookahead across lookahead! Recursive lookahead gives O(log N) delay Many variations on tree adders Memory Arrays : Digital Design Slide 46 Memory Arrays Array Architecture : Digital Design Slide 47 Array Architecture 2n words of 2m bits each If n >> m, fold by 2k into fewer rows of more columns Good regularity – easy to design Very high density if good cells are used 6T SRAM Cell : Digital Design Slide 48 6T SRAM Cell Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters Read: Precharge bit, bit_b Raise wordline Write: Drive data onto bit, bit_b Raise wordline SRAM Sizing : Digital Design Slide 49 SRAM Sizing High bitlines must not overpower inverters during reads But low bitlines must write new value into cell Decoders : Digital Design Slide 50 Decoders n:2n decoder consists of 2n n-input AND gates One needed for each row of memory Build AND from NAND or NOR gates Static CMOS Pseudo-nMOS Decoder Layout : Digital Design Slide 51 Decoder Layout Decoders must be pitch-matched to SRAM cell Requires very skinny gates Sense Amplifiers : Digital Design Slide 52 Sense Amplifiers Bitlines have many cells attached Ex: 32-kbit SRAM has 256 rows x 128 cols 128 cells on each bitline tpd (C/I) DV Even with shared diffusion contacts, 64C of diffusion capacitance (big C) Discharged slowly through small transistors (small I) Sense amplifiers are triggered on small voltage swing (reduce DV) Queues : Digital Design Slide 53 Queues Queues allow data to be read and written at different rates. Read and write each use their own clock, data Queue indicates whether it is full or empty Build with SRAM and read/write counters (pointers) CAMs : Digital Design Slide 54 CAMs Extension of ordinary memory (e.g. SRAM) Read and write memory as usual Also match to see which words contain a key 10T CAM Cell : Digital Design Slide 55 10T CAM Cell Add four match transistors to 6T SRAM 56 x 43 l unit cell CAM Cell Operation : Digital Design Slide 56 CAM Cell Operation Read and write like ordinary SRAM For matching: Leave wordline low Precharge matchlines Place key on bitlines Matchlines evaluate Miss line Pseudo-nMOS NOR of match lines Goes high if no words match ROM Example : Digital Design Slide 57 ROM Example 4-word x 6-bit ROM Represented with dot diagram Dots indicate 1’s in ROM Word 0: 010101 Word 1: 011001 Word 2: 100101 Word 3: 101010 Looks like 6 4-input pseudo-nMOS NORs PLAs : Digital Design Slide 58 PLAs A Programmable Logic Array performs any function in sum-of-products form. Literals: inputs & complements Products / Minterms: AND of literals Outputs: OR of Minterms Example: Full Adder PLA Schematic & Layout : Digital Design Slide 59 PLA Schematic & Layout Ideal nMOS I-V Plot : Digital Design Slide 60 Ideal nMOS I-V Plot 180 nm TSMC process Ideal Models b = 155(W/L) mA/V2 Vt = 0.4 V VDD = 1.8 V Simulated nMOS I-V Plot : Digital Design Slide 61 Simulated nMOS I-V Plot 180 nm TSMC process BSIM 3v3 SPICE models What differs? Less ON current No square law Current increases in saturation Velocity Saturation : Digital Design Slide 62 Velocity Saturation We assumed carrier velocity is proportional to E-field v = mElat = mVds/L At high fields, this ceases to be true Carriers scatter off atoms Velocity reaches vsat Electrons: 6-10 x 106 cm/s Holes: 4-8 x 106 cm/s Better model Channel Length Modulation : Digital Design Slide 63 Channel Length Modulation Reverse-biased p-n junctions form a depletion region Region between n and p with no carriers Width of depletion Ld region grows with reverse bias Leff = L – Ld Shorter Leff gives more current Ids increases with Vds Even in saturation Body Effect : Digital Design Slide 64 Body Effect Vt: gate voltage necessary to invert channel Increases if source voltage increases because source is connected to the channel Increase in Vt with Vs is called the body effect OFF Transistor Behavior : Digital Design Slide 65 OFF Transistor Behavior What about current in cutoff? Simulated results What differs? Current doesn’t go to 0 in cutoff Leakage Sources : Digital Design Slide 66 Leakage Sources Subthreshold conduction Transistors can’t abruptly turn ON or OFF Junction leakage Reverse-biased PN junction diode current Gate leakage Tunneling through ultrathin gate dielectric Subthreshold leakage is the biggest source in modern transistors Low Power Design : Digital Design Slide 67 Low Power Design Reduce dynamic power a: clock gating, sleep mode C: small transistors (esp. on clock), short wires VDD: lowest suitable voltage f: lowest suitable frequency Reduce static power Selectively use ratioed circuits Selectively use low Vt devices Leakage reduction: stacked devices, body bias, low temperature Chip-to-Package Bonding : Digital Design Slide 68 Chip-to-Package Bonding Traditionally, chip is surrounded by pad frame Metal pads on 100 – 200 mm pitch Gold bond wires attach pads to package Lead frame distributes signals in package Metal heat spreader helps with cooling Bidirectional Pads : Digital Design Slide 69 Bidirectional Pads Combine input and output pad Need tristate driver on output Use enable signal to set direction Optimized tristate avoids huge series transistors Device Scaling : Digital Design Slide 70 Device Scaling Interconnect Delay : Digital Design Slide 71 Interconnect Delay Introduction toCMOS VLSIDesignLecture 14: CAMs, ROMs, and PLAs : Introduction toCMOS VLSIDesignLecture 14: CAMs, ROMs, and PLAs David Harris Harvey Mudd College Spring 2004 Outline : 14: CAMs, ROMs, and PLAs Slide 73 Outline Content-Addressable Memories Read-Only Memories Programmable Logic Arrays CAMs : 14: CAMs, ROMs, and PLAs Slide 74 CAMs Extension of ordinary memory (e.g. SRAM) Read and write memory as usual Also match to see which words contain a key 10T CAM Cell : 14: CAMs, ROMs, and PLAs Slide 75 10T CAM Cell Add four match transistors to 6T SRAM 56 x 43 l unit cell CAM Cell Operation : 14: CAMs, ROMs, and PLAs Slide 76 CAM Cell Operation Read and write like ordinary SRAM For matching: Leave wordline low Precharge matchlines Place key on bitlines Matchlines evaluate Miss line Pseudo-nMOS NOR of match lines Goes high if no words match Read-Only Memories : 14: CAMs, ROMs, and PLAs Slide 77 Read-Only Memories Read-Only Memories are nonvolatile Retain their contents when power is removed Mask-programmed ROMs use one transistor per bit Presence or absence determines 1 or 0 ROM Example : 14: CAMs, ROMs, and PLAs Slide 78 ROM Example 4-word x 6-bit ROM Represented with dot diagram Dots indicate 1’s in ROM Word 0: 010101 Word 1: 011001 Word 2: 100101 Word 3: 101010 Looks like 6 4-input pseudo-nMOS NORs ROM Array Layout : 14: CAMs, ROMs, and PLAs Slide 79 ROM Array Layout Unit cell is 12 x 8 l (about 1/10 size of SRAM) Row Decoders : 14: CAMs, ROMs, and PLAs Slide 80 Row Decoders ROM row decoders must pitch-match with ROM Only a single track per word! Complete ROM Layout : 14: CAMs, ROMs, and PLAs Slide 81 Complete ROM Layout PROMs and EPROMs : 14: CAMs, ROMs, and PLAs Slide 82 PROMs and EPROMs Programmable ROMs Build array with transistors at every site Burn out fuses to disable unwanted transistors Electrically Programmable ROMs Use floating gate to turn off unwanted transistors EPROM, EEPROM, Flash Building Logic with ROMs : 14: CAMs, ROMs, and PLAs Slide 83 Building Logic with ROMs Use ROM as lookup table containing truth table n inputs, k outputs requires __ words x __ bits Changing function is easy – reprogram ROM Finite State Machine n inputs, k outputs, s bits of state Build with ________ bit ROM and ____ bit reg Building Logic with ROMs : 14: CAMs, ROMs, and PLAs Slide 84 Building Logic with ROMs Use ROM as lookup table containing truth table n inputs, k outputs requires 2n words x k bits Changing function is easy – reprogram ROM Finite State Machine n inputs, k outputs, s bits of state Build with 2n+s x (k+s) bit ROM and (k+s) bit reg Example: RoboAnt : 14: CAMs, ROMs, and PLAs Slide 85 Example: RoboAnt Let’s build an Ant Sensors: Antennae (L,R) – 1 when in contact Actuators: Legs Forward step F Ten degree turns TL, TR Goal: make our ant smart enough to get out of a maze Strategy: keep right antenna on wall (RoboAnt adapted from MIT 6.004 2002 OpenCourseWare by Ward and Terman) L R Lost in space : 14: CAMs, ROMs, and PLAs Slide 86 Lost in space Action: go forward until we hit something Initial state Bonk!!! : 14: CAMs, ROMs, and PLAs Slide 87 Bonk!!! Action: turn left (rotate counterclockwise) Until we don’t touch anymore A little to the right : 14: CAMs, ROMs, and PLAs Slide 88 A little to the right Action: step forward and turn right a little Looking for wall Then a little to the right : 14: CAMs, ROMs, and PLAs Slide 89 Then a little to the right Action: step and turn left a little, until not touching Whoops – a corner! : 14: CAMs, ROMs, and PLAs Slide 90 Whoops – a corner! Action: step and turn right until hitting next wall Simplification : 14: CAMs, ROMs, and PLAs Slide 91 Simplification Merge equivalent states where possible State Transition Table : 14: CAMs, ROMs, and PLAs Slide 92 State Transition Table Lost RCCW Wall1 Wall2 ROM Implementation : 14: CAMs, ROMs, and PLAs Slide 93 ROM Implementation 16-word x 5 bit ROM ROM Implementation : 14: CAMs, ROMs, and PLAs Slide 94 ROM Implementation 16-word x 5 bit ROM PLAs : 14: CAMs, ROMs, and PLAs Slide 95 PLAs A Programmable Logic Array performs any function in sum-of-products form. Literals: inputs & complements Products / Minterms: AND of literals Outputs: OR of Minterms Example: Full Adder NOR-NOR PLAs : 14: CAMs, ROMs, and PLAs Slide 96 NOR-NOR PLAs ANDs and ORs are not very efficient in CMOS Dynamic or Pseudo-nMOS NORs are very efficient Use DeMorgan’s Law to convert to all NORs PLA Schematic & Layout : 14: CAMs, ROMs, and PLAs Slide 97 PLA Schematic & Layout PLAs vs. ROMs : 14: CAMs, ROMs, and PLAs Slide 98 PLAs vs. ROMs The OR plane of the PLA is like the ROM array The AND plane of the PLA is like the ROM decoder PLAs are more flexible than ROMs No need to have 2n rows for n inputs Only generate the minterms that are needed Take advantage of logic simplification Example: RoboAnt PLA : 14: CAMs, ROMs, and PLAs Slide 99 Example: RoboAnt PLA Convert state transition table to logic equations RoboAnt Dot Diagram : 14: CAMs, ROMs, and PLAs Slide 100 RoboAnt Dot Diagram RoboAnt Dot Diagram : 14: CAMs, ROMs, and PLAs Slide 101 RoboAnt Dot Diagram