VLSI_Design Rules,Layout and Stick Diagram Lecture04

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Lecture 4 Design Rules,Layout and Stick Diagram:

Lecture 4 Design Rules,Layout and Stick Diagram ENG.AMGAD YOUNIS amgadyounis@hotmail.com Department of Electronics Faculty of Engineering Helwan University

Acknowledgement:

April 29, 2013 204424 Digital Design Automation 2 Acknowledgement This lecture note has been summarized from lecture note on Introduction to VLSI Design, VLSI Circuit Design all over the world. I can’t remember where those slide come from. However, I’d like to thank all professors who create such a good work on those lecture notes. Without those lectures, this slide can’t be finished.

Roadmap for the term: major topics:

April 29, 2013 204424 Digital Design Automation 3 Roadmap for the term: major topics VLSI Overview CMOS Processing & Fabrication Components: Transistors, Wires, & Parasitics Design Rules & Layout Combinational Circuit Design & Layout Sequential Circuit Design & Layout Standard-Cell Design with CAD Tools Systems Design using Verilog HDL Design Project: Complete Chip

Review - CMOS Mask Layers:

April 29, 2013 204424 Digital Design Automation 4 P substrate Review - CMOS Mask Layers Determine placement of layout objects Color coding specifies layers Layout objects: Rectangles Polygons Arbitrary shapes Grid types Absolute (“micron”) Scaleable (“lambda”) wafer n well

Mask Generation:

April 29, 2013 204424 Digital Design Automation 5 Mask Generation Mask Design using Layout Editor user specifies layout objects on different layers output: layout file Pattern Generator Reads layout file Generates enlarged master image of each mask layer Image printed on glass Step & repeat camera Reduces & copies image onto mask One copy for each die on wafer Note importance of mask alignment

Symbolic Mask Layers:

April 29, 2013 204424 Digital Design Automation 6 Symbolic Mask Layers Key idea: Reduce layers to those that describe design Generate physical layers as needed Magic Layout Editor: "Abstract Layers” metal1 (blue) - 1st layer metal (equiv. to physical layer) Poly (red) - polysilicon (equivalent to physical layer) ndiff (green) - n diffusion (combination of active, nselect) ntranistor (green/red crosshatch) - combined poly, ndiff pdiff (brown) - p diffusion (combination of active, pselect) ptransistor (brown/red crosshatch) - combined poly, pdiff contacts: combine layers, cut mask

About Magic:

April 29, 2013 204424 Digital Design Automation 7 About Magic Scalable Grid for Scalable Design Rules Grid distance: l ( lambda) Value is process-dependent: l = 0.5 X minimum transistor length Painting metaphor Paint squares on grid for each mask layer Layers to interact to form components (e.g. transistors)

Mask Layers in Magic:

April 29, 2013 204424 Digital Design Automation 8 Mask Layers in Magic Poly (red) N Diffusion (green) P Diffusion (brown) Metal (blue) Metal 2 (purple) Well (cross-hatching) Contacts (X)

Magic User-Interface:

April 29, 2013 204424 Digital Design Automation 9 Magic User-Interface Graphic Display Window Cursor Box - specifies area to paint Command window (not shown) accepts text commands :paint poly :paint red :paint ndiff :paint green :write prints error & status messages Cursor Box Paint (poly) Paint (pdiff) Paint (ntransistor)

Layer Interaction in Magic:

April 29, 2013 204424 Digital Design Automation 10 Layer Interaction in Magic Transistors - where poly, diffusion cross poly crosses ndiffusion - ntransistor poly crosses pdiffusion - ptransistor Vias - where layers connect Metal 1 connecting to Poly - polycontact Metal 1 connecting to P-Diffusion (normal) - pdc Metal 1 connecting to P-Diffusion (substrate contact) - psc Metal 1 connecting to N-Diffusion (normal) - ndc Metal 1 connecting to N-Diffusion (substrate contact) - nsc Metal 1 connecting to Metal 2 - via

Magic Layers - Example:

April 29, 2013 204424 Digital Design Automation 11 Magic Layers - Example nwell nsc psc p-transistor ntransistor metal1 metal1 metal1 poly poly ndc ndc polycontact polycontact pdc

Why we need design rules:

April 29, 2013 204424 Digital Design Automation 12 Why we need design rules Masks are tooling for manufacturing. Manufacturing processes have inherent limitations in accuracy. Design rules specify geometry of masks which will provide reasonable yields. Design rules are determined by experience.

Manufacturing problems:

April 29, 2013 204424 Digital Design Automation 13 Manufacturing problems Photoresist shrinkage, tearing. Variations in material deposition. Variations in temperature. Variations in oxide thickness. Impurities. Variations between lots. Variations across a wafer.

Transistor problems:

April 29, 2013 204424 Digital Design Automation 14 Transistor problems Varaiations in threshold voltage: oxide thickness; ion implanatation; poly variations. Changes in source/drain diffusion overlap. Variations in substrate.

Wiring problems:

April 29, 2013 204424 Digital Design Automation 15 Wiring problems Diffusion: changes in doping -> variations in resistance, capacitance. Poly, metal: variations in height, width -> variations in resistance, capacitance. Shorts and opens:

Oxide problems:

April 29, 2013 204424 Digital Design Automation 16 Oxide problems Variations in height. Lack of planarity -> step coverage. metal 1 metal 2 metal 2

Via problems:

April 29, 2013 204424 Digital Design Automation 17 Via problems Via may not be cut all the way through. Undesize via has too much resistance. Via may be too large and create short.

MOSIS SCMOS design rules:

April 29, 2013 204424 Digital Design Automation 18 MOSIS SCMOS design rules Designed to scale across a wide range of technologies. Designed to support multiple vendors. Designed for educational use. Ergo, fairly conservative.

 and design rules:

April 29, 2013 204424 Digital Design Automation 19  and design rules  is the size of a minimum feature. Specifying  particularizes the scalable rules. Parasitics are generally not specified in  units 

Design Rules:

April 29, 2013 204424 Digital Design Automation 20 Design Rules Typical rules: Minumum size Minimum spacing Alignment / overlap Composition Negative features

Types of Design Rules:

April 29, 2013 204424 Digital Design Automation 21 Types of Design Rules Scalable Design Rules (e.g. SCMOS) Based on scalable “coarse grid” - l (lambda) Idea: reduce l value for each new process, but keep rules the same Key advantage: portable layout Key disadvantage: not everything scales the same Not used in “real life” Absolute Design Rules Based on absolute distances (e.g. 0.75µm) Tuned to a specific process (details usually proprietary) Complex, especially for deep submicron Layouts not portable

SCMOS Design Rules:

April 29, 2013 204424 Digital Design Automation 22 SCMOS Design Rules Intended to be Scalable Original rules: SCMOS Submicron: SCMOS-SUBM Deep Submicron: SCMOS-DEEP Pictorial Summary: Book Fig. 2-24, p. 27 Authoritative Reference: www.mosis.org

SCMOS Design Rule Summary:

April 29, 2013 204424 Digital Design Automation 23 SCMOS Design Rule Summary Line size and spacing: metal1: Minimum width=3 l , Minimum Spacing=3 l metal2: Minimum width=3 l , Minimum Spacing=4 l poly: Minimum width= 2 l , Minimum Spacing=2 l ndiff/pdiff: Minimum width= 3 l , Minimum Spacing=3 l, minimum ndiff/pdiff seperation=10 l wells: minimum width=10 l , min distance form well edge to source/drain=5 l Transistors: Min width=3 l Min length=2 l Min poly overhang=2 l

SCMOS Design Rule Summary:

April 29, 2013 204424 Digital Design Automation 24 SCMOS Design Rule Summary Contacts (Vias) Cut size: exactly 2 l X 2 l Cut separation: minimum 2 l Overlap: min 1 l in all directions Magic approach: Symbolic contact layer min. size 4 l X 4 l Contacts cannot stack (i.e., metal2/metal1/poly) Other rules cut to poly must be 3 l from other poly cut to diff must be 3 l from other diff metal2/metal1 contact cannot be directly over poly negative features must be at least 2 l in size CMP Density rules (AMI/HP subm): 15% Poly, 30% Metal

Design Rule Checking in Magic:

April 29, 2013 204424 Digital Design Automation 25 Design Rule Checking in Magic Design violations displayed as error paint Find which rule is violated with " :drc why ” Poly must overhang transistor by at least 2 (MOSIS rule #3.3)

Scaling Design Rules:

April 29, 2013 204424 Digital Design Automation 26 Scaling Design Rules Effects of scaling down are positive See book, p. 78-79 - if “everything” scales, scaling circuit by 1/x increases performance by x Problem: not everything scales proportionally

Aside - About MOSIS:

April 29, 2013 204424 Digital Design Automation 27 Aside - About MOSIS MOSIS - MOS Implementation Service Rapid-prototyping for small chips Multi-project chip idea - several designs on the same wafer Reduced mask costs per design Accepts layout designs via email Brokers fabrication by foundries (e.g. AMI, Agilent, IBM, TSMC) Packages chips & ships back to designers Our designs will use AMI 1.5µm process (more about this later)

Aside - About MOSIS:

April 29, 2013 204424 Digital Design Automation 28 Aside - About MOSIS Some Typical MOSIS Prices (from www.mosis.org) AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm) $1,080 AMI 1.5µm 9.4mm X 9.7mm $17,980 AMI 0.5µm 0-5mm 2 $5,900 TSMC 0.25µm 0-10mm 2 $15,550 TSMC 0.18µm 0-7mm 2 $24,500 TSMC 100-159mm 2 $63,250 + $900 X size MOSIS Educational Program (what we use) AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm) FREE* AMI 0.5mm “Tiny Chip” (1.5mm X 1.5mm) FREE* *sponsored by Semiconductor Industry Assn., Semiconductor Research Corp., | AMI, Inc., DuPont Photomasks, and MOSIS

Layout Considerations:

April 29, 2013 204424 Digital Design Automation 29 Layout Considerations Break layout into interconnected cells Use hierarchy to control complexity Connect cells by Abutment Added wires Key goals: Minimize size of overall layout Meet performance constraints Meet design time deadlines

Hierarchy in Layout:

April 29, 2013 204424 Digital Design Automation 30 Hierarchy in Layout Chips are constructed as a hierarchy of cells Leaf cells - bottom of hierarchy Root cells - contains overall cell Example - hypothetical “UART” Pad frame - “ring” that contains I/O pads Core - contains logic organized as subcells Shift register FSM Other cells

Hierarchy Example:

April 29, 2013 204424 Digital Design Automation 31 Hierarchy Example Root Cell: UART

Wires:

April 29, 2013 204424 Digital Design Automation 32 Wires metal 3 6 metal 2 3 metal 1 3 pdiff/ndiff 3 poly 2

Transistors:

April 29, 2013 204424 Digital Design Automation 33 Transistors 2 3 1 3 2 5

Vias:

April 29, 2013 204424 Digital Design Automation 34 Vias Types of via: metal1/diff, metal1/poly, metal1/metal2. 4 1 4 2

Metal 3 via:

April 29, 2013 204424 Digital Design Automation 35 Metal 3 via Type: metal3/metal2. Rules: cut: 3 x 3 overlap by metal2: 1 minimum spacing: 3 minimum spacing to via1: 2

Tub tie:

April 29, 2013 204424 Digital Design Automation 36 Tub tie 4 1

Spacings:

April 29, 2013 204424 Digital Design Automation 37 Spacings Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: 1 Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4 Metal3/metal3: 4

Overglass:

April 29, 2013 204424 Digital Design Automation 38 Overglass Cut in passivation layer. Minimum bonding pad: 100  m. Pad overlap of glass opening: 6 Minimum pad spacing to unrelated metal2/3: 30 Minimum pad spacing to unrelated metal1, poly, active: 15

Stick diagrams (1/3):

April 29, 2013 204424 Digital Design Automation 39 Stick diagrams (1/3) A stick diagram is a cartoon of a layout. Does show all components/vias (except possibly tub ties), relative placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

Stick Diagrams (2/3):

April 29, 2013 204424 Digital Design Automation 40 Stick Diagrams (2/3) Key idea: "Stick figure cartoon" of a layout Useful for planning layout relative placement of transistors assignment of signals to layers connections between cells cell hierarchy

Stick Diagrams (3/3):

April 29, 2013 204424 Digital Design Automation 41 Stick Diagrams (3/3)

Example - Stick Diagrams (1/2):

April 29, 2013 204424 Digital Design Automation 42 Example - Stick Diagrams (1/2) Circuit Diagram. Pull-Down Network (The easy part!) Alternatives - Pull-up Network Complete Stick Diagram

Example - Stick Diagrams (2/2):

April 29, 2013 204424 Digital Design Automation 43 Example - Stick Diagrams (2/2)

Dynamic latch stick diagram:

April 29, 2013 204424 Digital Design Automation 44 Dynamic latch stick diagram VDD in VSS phi phi’ out

Stick Diagram XOR Gate Examples:

April 29, 2013 204424 Digital Design Automation 45 Stick Diagram XOR Gate Examples

Hierarchical Stick Diagrams:

April 29, 2013 204424 Digital Design Automation 46 Hierarchical Stick Diagrams Define cells by outlines & use in a hierarchy to build more complex cells

Cell Connection Schemes:

April 29, 2013 204424 Digital Design Automation 47 Cell Connection Schemes External connection - wire cells together Abutment - design cells to connect when adjacent Reflection, mirroring - use to make abutment possible

Example: 2-input multiplexer:

April 29, 2013 204424 Digital Design Automation 48 Example: 2-input multiplexer First cut:

Sticks design of multiplexer:

April 29, 2013 204424 Digital Design Automation 49 Sticks design of multiplexer Start with NAND gate:

NAND sticks:

April 29, 2013 204424 Digital Design Automation 50 NAND sticks VDD a VSS out b

Refined one-bit Mux Design:

April 29, 2013 204424 Digital Design Automation 51 Refined one-bit Mux Design Use NAND cell as black box Arrange easy power connections Vertical connections for allow multiple bits

3-bit mux sticks:

April 29, 2013 204424 Digital Design Automation 52 3-bit mux sticks m2(one-bit-mux) select’ select VDD VSS o i a i b i m2(one-bit-mux) select’ select VDD VSS o i a i b i m2(one-bit-mux) select’ select VDD VSS o i a i b i select’ select a 2 b 2 a 1 b 1 a 0 b 0 o 2 o 1 o 0

Multiple-Bit Mux:

April 29, 2013 204424 Digital Design Automation 53 Multiple-Bit Mux

Cell Mirroring, Overlap:

April 29, 2013 204424 Digital Design Automation 54 Cell Mirroring, Overlap Use mirroring, overlap to save area

Example: Layout / Stick Diagram:

April 29, 2013 204424 Digital Design Automation 55 Example: Layout / Stick Diagram Create a layout for a NAND gate given constraints: Use minimum-size transistors Assume power supply lines “pass through” cell from left to right at top and bottom of cell Assume inputs are on left side of cell Assume output is on right side of cell Optimize cell to minimize width Optimize cell to minimize overall area

Layout Example:

April 29, 2013 204424 Digital Design Automation 56 Layout Example Circuit Diagram. Exterior of Cell

Example - Magic Layout:

April 29, 2013 204424 Digital Design Automation 57 Example - Magic Layout Overall Layout: 52 X 16

Review - VLSI Levels of Abstraction:

April 29, 2013 204424 Digital Design Automation 58 Review - VLSI Levels of Abstraction Specification (what the chip does, inputs/outputs) Architecture major resources, connections Register-Transfer logic blocks, FSMs, connections Circuit transistors, parasitics, connections Layout mask layers, polygons Logic gates, flip-flops, latches, connections You are Here

Levels of Abstraction - Perspective:

April 29, 2013 204424 Digital Design Automation 59 Levels of Abstraction - Perspective Right now, we’re focusing on the “low level”: Circuit level - transistors, wires, parasitics Layout level - mask objects We’ll work upward to higher levels: Logic level - individual gates, latches, flip-flops Register- transfer level - Verilog HDL Behavior level - Specifications

The Challenge of Design:

April 29, 2013 204424 Digital Design Automation 60 The Challenge of Design Start: higher level (spec) Finish: lower level (implementation) Must meet design criteria and constraints Design time - how long did it take to ship a product? Performance - how fast is the clock? Cost - NRE + unit cost CAD tools - essential in modern design

CAD Tool Survey: Layout Design:

April 29, 2013 204424 Digital Design Automation 61 CAD Tool Survey: Layout Design Layout Editors Design Rule Checkers (DRC) Circuit Extractors Layout vs. Schematic (LVS) Comparators Automatic Layout Tools Layout Generators ASIC: Place/Route for Standard Cells, Gate Arrays

Layout Editors:

April 29, 2013 204424 Digital Design Automation 62 Layout Editors Goal: produce mask patterns for fabrication Grid type: Absolute grid (MAX, LASI, LEdit, Mentor ICStation, other commercial tools) Magic: lambda-based grid - easier to learn, but less powerful Mask description: Absolute mask (one layer for each mask) Magic: symbolic masks (layers combine to generate actual mask patterns)

Design Rule Checkers:

April 29, 2013 204424 Digital Design Automation 63 Design Rule Checkers Goal: identify design rule violations Often a separate tool (built in to Magic) General approach: “scanline” algorithm Computationally intensive, especially for large chips

Circuit Extractors:

April 29, 2013 204424 Digital Design Automation 64 Circuit Extractors Goal: extract netlist of equivalent circuit Identify active components Identify parasitic components Capacitors Resistors

Layout Versus Schematic (LVS):

April 29, 2013 204424 Digital Design Automation 65 Layout Versus Schematic (LVS) Goal: Compare layout, schematic netlists Compare transistors, connections (ignore parasitics) Issue error if two netlists are not equivalent Important for large designs

Automatic Layout Tools:

April 29, 2013 204424 Digital Design Automation 66 Automatic Layout Tools Layout Generators - produce cell from spec. Simple: Procedural specification of layout (see book Fig. 2-33, p. 95) Complex: Netlist - places & wires individual transistors ASIC - Place, route modules with fixed shape Standard Cells - use predefined cells as "cookie cutters" Gate Arrays - configurable pre-manufactured gates (only change metal masks) FPGAs - electrically configurable array of gates

Layout design and analysis tools:

April 29, 2013 204424 Digital Design Automation 67 Layout design and analysis tools Layout editors are interactive tools. Design rule checkers are generally batch---identify DRC errors on the layout. Circuit extractors extract the netlist from the layout. Connectivity verification systems (CVS) compare extracted and original netlists.

Automatic layout:

April 29, 2013 204424 Digital Design Automation 68 Automatic layout Cell generators (macrocell generators) create optimized layouts for ALUs, etc. Standard cell/sea-of-gates layout creates layout from predesigned cells + custom routing. Sea-of-gates allows routing over the cell.

Standard cell layout:

April 29, 2013 204424 Digital Design Automation 69 Standard cell layout routing area routing area routing area routing area

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