logging in or signing up cpu alp1 Download Post to : URL : Related Presentations : Let's Connect Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Copy embed code: Embed: Flash iPad Dynamic Copy Does not support media & animations Automatically changes to Flash or non-Flash embed WordPress Embed Customize Embed URL: Copy Thumbnail: Copy The presentation is successfully added In Your Favorites. Views: 4008 Category: Education License: All Rights Reserved Like it (7) Dislike it (0) Added: May 14, 2009 This Presentation is Public Favorites: 4 Presentation Description No description available. Comments Posting comment... Premium member Presentation Transcript CPU (Central Processing Unit) : “The brain of the computer” that takes care of all the computations and processes. CPU (Central Processing Unit) Architecture : The component of CPU include, CU: Control Unit Directs and manages the activities of the processor. ALU: Arithmetic and Logic Unit. Performs Arithmetic and Logical operations.(+, -, x, /, >,<, =) FPU: Floating Point Unit. Performs division and large decimal operations. Cache Memory: Predicts and anticipates the data that the processor needs. I/O Unit: Input Output unit. The gateway for the processor. Register : Which hold temporary data for a specific purpose of function. Architecture Basic Architecture : Basic Architecture Processing : Processing In this chapter, we will focus on the central processing unit (CPU) in more detail. Input Processing Output Secondary Storage The CPU : The CPU The CPU interacts(affects) closely with memory (primary storage). CPU Memory Memory, however, is not part of the CPU. Parts of the CPU : Parts of the CPU The CPU consists of a variety of parts including: Control unit Arithmetic/logic unit (ALU) Registers The Control Unit… : The Control Unit… directs the other parts of the computer system to execute(perform) stored program instructions. The control unit communicates with the ALU and memory. The Arithmetic/Logic Unit (ALU)… : The Arithmetic/Logic Unit (ALU)… performs mathematical operations as well as logical operations. Mathematical Operations : Mathematical Operations The ALU can perform four kinds of mathematical calculations: addition subtraction multiplication division Logical Operations : Logical Operations The ALU can perform logical operations. Logical operations can test for these conditions(position): Equal-to (=) Less-than (<) Greater-than (>) Equal-to Condition : Equal-to Condition In a test for this condition, the ALU compares two values to determine if they are equal. Less-than Condition : Less-than Condition In a test for this condition, the ALU compares values to determine if one value is less than another. Greater-than Condition : Greater-than Condition In a test for this condition, the ALU compares values to determine if one value is greater than another. Registers… : Registers… are temporary storage areas for data or instructions. Data held temporarily in registers can be accessed at greater speeds than data stored in memory. Memory (Primary Storage) : Memory (Primary Storage) Memory is the part of the computer that stores data and program instructions for processing. CPU Memory Memory… : Memory… is also referred to as RAM (random-access memory). CPU Memory RAM is temporary, finite, and more expensive than secondary storage. Executing Program Instructions : Executing Program Instructions Before the CPU can execute a program, program instructions and data must be placed into memory from an input device or storage device. Input Processing Secondary Storage Executing Program Instructions : Executing Program Instructions Once the necessary data and instructions are in memory, the CPU performs the following steps for each instruction: Fetching Decoding Executing Storing Fetching Instructions : Fetching Instructions The control unit fetches (gets) the instruction from memory. Memory Decoding(solve) Instructions : Decoding(solve) Instructions The control unit decodes the instruction and directs that the necessary data be moved from memory to the ALU. Memory Executing Arithmetic/Logic Operations : Executing Arithmetic/Logic Operations The ALU performs the arithmetic or logical operation on the data. Memory Storing Results : Storing Results The ALU stores the result of its operation on the data in memory or in a register. Memory Executing Program Instructions : Executing Program Instructions Eventually, the control unit sends the results in memory to an output device or secondary storage. Output Secondary Storage Instruction Time : Instruction Time The time it takes to fetch an instruction and decode it is called instruction time. + Execution Time : Execution Time The time it takes to execute an ALU operation and then store the result is called execution(perform) time. + Memory Locations and Addresses : Control Unit Memory Locations and Addresses The control unit can find data and instructions because each location in memory has an address. Memory Storage Locations : Storage Locations Each location in memory is identified by an address. Memory Each location has a unique address. Symbolic Addresses : Symbolic Addresses The choice of the location in memory is arbitrary (determination). Memory 17 364 Pat $ % Addresses can only hold one number or word. Data Representation : Data Representation The system in which all computer data is represented(colled) and manipulated(used) is called the binary system. Binary System : Binary System The binary system has only two digits to represent all values. This corresponds to the two states of a computer’s electrical system —on and off. Off/On Switches : Off/On Switches The computer can represent data by constructing combinations of off or on switches. off on or Zero or One? : Zero or One? The binary system can also be represented by the digits zero and one. 0 1 or Zero (off) and one (on) make up the two digits in the binary system. The Bit : The Bit Each 0 or 1 in the binary system is called a bit. one bit two bits three bits The Byte : The Byte A group of 8 bits is called a byte. One Character of Data : One Character of Data Each byte represents one character of data (a letter, digit, or special character). J = Storing Bytes : Storing Bytes Storage and memory capacity is expressed in the number of bytes they can hold: 1 kilobyte = 210 or 1024 bytes 1 megabyte = 220 or 1,048,576 bytes 1 gigabyte = 230 or 1,073,741,824 bytes Computer Word : Computer Word A computer word is defined as the number of bits that constitute a common unit of data. Computer Word Length : Computer Word Length Word length varies by computer. For example: 8 bits = 1 byte = one word length 64 bits = 8 bytes = one word length Coding the Computer : Coding the Computer A code for determining which group of bits represent which characters on a keyboard is called ASCII. (American Standard Code for Information Interchange) ASCII : ASCII ASCII has been adopted, as the standard, by the U.S. government and is found in a variety of computers. J = ASCII-8 code Keyboard character Computer Speed and Power : Computer Speed and Power Speed and power are determined by: Microprocessor speed Bus lines Cache Microprocessor Speeds : Microprocessor Speeds Microprocessor speeds can be measured in a variety of ways: Megahertz MIPS Megaflops Fsb Megahertz : Megahertz One measure of microprocessor speed is megahertz (MHz) which is one million machine cycles per second. gigahertz(billions of cycles per second). MIPS : MIPS Another measure of microprocessor speed is MIPS which is one million instructions per second. Megaflops : Megaflops Megaflops, or one million floating-point operations per second, is still another measure of microprocessor speed. Slide 46: Front Side Bus (FSB(: Measured in megahertz (MHz), the FSB is the channel that connects the processor with main memory. The faster this is, the better the performance will be. The Front Side Bus operates at a speed which is a percentage of the CPU clock speed. The faster the speed at which the Front Side Bus allows data transfer, the better the performance of the CPU. FSB Bus Lines : Bus Lines A bus line is a set of parallel electrical paths. A bus is like a mode of transportation for data. Bus width (Wide)= the number of wires in the bus over which data can travel+-- Bus Width(wide) : Bus Width(wide) The amount of data that can be carried at one time is bus width (wider = more data). Cache : Cache Cache is a relatively small block of very fast memory. The data and instructions stored in cache are those that are most recently or most frequently used. Cache speeds up the internal transfer of data and software instructions. Level 1 is fatest, followed by Level 2 Slide 50: Private vs shared caches • Advantages of private: – They are closer to core, so faster access – Reduces contention • Advantages of shared: – Threads on different cores can share the same cache data – More cache space available if a single (or a few) high-performance thread runs on the system RAM: Random Access Memory : RAM: Random Access Memory DRAM (Dynamic RAM) Most common, cheap Volatile: must be refreshed (recharged with power) 1000’s of times each second SRAM (static RAM) Faster than DRAM and more expensive than DRAM Volatile Frequently small amount used in cache memory for high-speed access used Processor Types : Two types: Socket type Slot type. Pin arrangement in the Socket type processor is known as Pin Grid Array (PGA). Slot type processor is also known as Single Edged Contact Cartridge (SECC). Processor Types Types of Processors : Types of Processors SECC PGA Intel Scalar Processors : 8085-8bit 8086-16bit 80186-32bit 80286-32bit 80386(SX/DX)-32 bit 80486(SX/DX)-32bit Intel Scalar Processors Super Scalar Processors : Pentium –first super scalar processor Pentium family uses super scalar technology P4 also uses Hyper Threading(HT) Super Scalar Processors Processor Manufacturers : Processor Manufacturers Intel (Integrated Electronics) AMD (Advanced Micro Devices) VIA Cyrix Brands of Intel : Brands of Intel Pentium I Pentium Pro Pentium MMX Pentium II Pentium III Pentium IV Pentium D Celeron Centrino M Core 2 Duo Core 2 Extreme Core 2 Quad Brands of AMD : Brands of AMD Athlon Duron Sempron Turion Pentium (1993) : 273/296 pins PGA arrangement Socket 4,5 or 7 Speed:60 to 200 MHz L1 cache-16 KB L2-256 to 512 KB Power supply- 3.3 to 5 v Transistors:3.1 to 3.3 million Features:1st super scalar processor,64 bit registers Pentium (1993) Pentium MMX (1997) : 296 pins SPGA Socket 7 166 to 233 MHZ 32 KB L1 256-512 KB L2 P.S: 3.3v-Ext,2.8v-Internal 4.5 million transistors Enhanced multimedia Pentium MMX (1997) Pentium II (1997) : 242 contacts SEC/SECC Slot 1 233-333 MHz 32 KB L1 512KB L2 3.3v power supply 7.5 million transistors First SEC processor Pentium II (1997) Pentium III (1999) : 242 contacts/370 pins SEPP/SECC/PGA PGA370/slot 1 450 MHz to 1.13 GHz 32 KB L1 256 KB to 512 KB L2 2v power supply 9.1 to 9.3 million transistors Streaming SIMDA (single instr. multiple data access) Pentium III (1999) Pentium 4 (2000) : 423/478 pins SPGA PGA 423/PGA 478(PGA2) 1.3 to 3.2 GHz 8 KB L1 256 KB to 512 KB L2 1.44 to 1.75v power supply Billion transistors Net burst architecture Technology HT (Hyper Threading) (above 2.4 GHz) Pentium 4 (2000) Hyper threading : A technology developed by Intel that enables multithreaded(current of data) software applications to execute threads in parallel on a single processor instead of processing threads in a linear fashion. Older systems took advantage of dual-processing threading in software by splitting(dividing) instructions into multiple streams so that more than one processor could act upon (on)them at once. Hyper threading Celeron : Celeron A brand name for a line of Intel microprocessors introduced in June, 1998. Celeron chips are based on the same P6 architecture as the Pentium II microprocessor, but are designed for low-cost PCs. They run at somewhat lower clock speeds (266 and 300 MHz) and are not as expandable as Pentium II microprocessors. AMD K5 (1995) : 296 pins PGA Socket 7 75 to 116 MHz 8 KB L1 3.52 v power supply 4.3 million transistors 32 bit address bus(4 GB RAM), 64 bit data bus. AMD K5 (1995) AMD K6 : 296 pins PGA Socket 7 166-266 MHz 256 KB to 1MB L1 3.3 v power supply 8.8 million transistors 32 bit address bus(4 GB RAM), 64 bit data bus. AMD K6 Slide 68: Three versions of the Athlon processor have been introduced so far. The first version was the K7 version that ran between 500MHz and 700MHz, provided a 128KB L1 cache and a 512KB L2 cache, employed a 100MHz system bus, and used Slot-A. AMD : AMD The Athlon is a Pentium III clone processor. It is available in a Slot 1 cartridge clone, called the Slot-A specification. The Duron processor is a Celeron clone processor that conforms to the AMD Socket-A specification. The Duron features processor speeds between 600MHz and 1.3 GHz. It includes a 128KB L1 cache and a 64KB L2 cache, and employs a 100MHz system bus. Why multicore? : Why multicore? New modern processors are launched How to make a use of new technologies? Dual-core CPU Quad-core CPU 70 Slide 71: 71 Dual-core, Max. speedup ~2x Quad-core, Max. speedup ~4x Slide 72: • Difficult to make single-core clock frequencies even higher • Deeply pipelined circuits(term): – heat problems • Many new applications are multithreaded • General(common) trend in computer architecture Slide 73: • Editing a photo while recording a TV show through a digital video recorder • Downloading software while running an anti-virus program • “Anything that can be threaded today will map efficiently to multi-core” Slide 75: Summary • Multi-core chips an important new trend in computer architecture • Several new multi-core chips in design phases likely to gain importance Intel Core 2 models : Intel Core 2 models Allendale, Conroe - process technology Desktop CPU Introduced on July 27, 2006 Number of Transistors 291 Million on 4 MB Models Number of Transistors 167 Million on 2 MB Models Variants Core 2 Duo E6700 - 2.67 GHz (4 MB L2, 1066 MHz FSB) Core 2 Duo E6600 - 2.40 GHz (4 MB L2, 1066 MHz FSB) Core 2 Duo E6400 - 2.13 GHz (2 MB L2, 1066 MHz FSB) Core 2 Duo E6300 - 1.86 GHz (2 MB L2, 1066 MHz FSB) Core 2 Duo E4200 - 1.60 GHz (2 MB L2, 800 MHz FSB) 6 / 37 Intel Core 2 models : Intel Core 2 models Woodcrest - process technology Server optimized CPU Introduced on July 26, 2006 Same features as Conroe Variants Xeon 5160 - 3.00 GHz (4 MB L2, 1333 MHz FSB, 80 W) Xeon 5150 - 2.66 GHz (4 MB L2, 1333 MHz FSB, 65 W) Xeon 5140 - 2.33 GHz (4 MB L2, 1333 MHz FSB, 65 W) Xeon 5130 - 2.00 GHz (4 MB L2, 1333 MHz FSB, 65 W) Xeon 5120 - 1.86 GHz (4 MB L2, 1066 MHz FSB, 65 W) Xeon 5110 - 1.60 GHz (4 MB L2, 1066 MHz FSB, 65 W) Xeon 5148LV - 2.33 GHz (4 MB L2,1333 MHz FSB,40 W) 7 / 37 Intel Core 2 models : Intel Core 2 models Merom - process technology Mobile CPU Introduced on July 27, 2006 Same features as Conroe Variants Core 2 Duo T7600 - 2.33 GHz (4 MB L2, 667 MHz FSB) Core 2 Duo T7400 - 2.16 GHz (4 MB L2, 667 MHz FSB) Core 2 Duo T7200 - 2.00 GHz (4 MB L2, 667 MHz FSB) Core 2 Duo T5600 - 1.83 GHz (2 MB L2, 667 MHz FSB) Core 2 Duo T5500 - 1.66 GHz (2 MB L2, 667 MHz FSB) Core 2 Duo T5200 - 1.60 GHz (2 MB L2, 533 MHz FSB) 8 / 37 What is L1 and L2? : What is L1 and L2? Level-1 and Level-2 caches The cache memories in a computer Much faster than RAM L1 is built on the microprocessor chip itself. L2 is a seperate chip L2 cache is much larger than L1 cache 19 / 37 AMD Phenom™ PerformanceOverall Performance of Office Productivity + Digital Media + Games : November 2007 AMD Phenom™ PerformanceOverall Performance of Office Productivity + Digital Media + Games AMD Phenom™ Processor Performance Desktop Platform Performance – Overall Performance (Windows Vista®) UMA 80 The value of each category of benchmarks is the geometric mean of every test within that benchmark category. The geometric mean of these categories provides the Overall Performance value for each processor model. The geometric mean of scores is normalized to the AMD Phenom X4 9600 Quad-Core Processor . See pg 12-14 for system configurations and tests. Slide 81: CPU Positioning Against Intel Slide 82: Tri core Phenom X3 Architecture Chipset Chipset Memory Memory Intel Core2Duo AMD Phenom VS Slide 83: Quad Core Phenom X4 Architecture DDR2 HyperTransport™ technology Chipset Chipset Memory Memory Intel Core2Quad AMD Phenom Shared 2MB L3 Cache VS Slide 84: Desktop Product Marketing February 2007 System Request Interface & Crossbar Switch FSB bottleneck other I/O links Intel Quad-Core Processor other I/O links Integrated memory controller operating at full CPU clock speed 2000MHz HyperTransport™ technology link AMD Phenom™ X4 I/O and memory calls are implemented on separate, dedicated high-speed busses Die 1 Die 2 AMD Quad-Core Processor Integrated DDR2 Memory Controller HyperTransport™ Bus Shared L3 Cache Quad-Core ArchitectureComparison Quad-Core ArchitectureComparison : Presentation Title Month ##, 200# System Request Interface & Crossbar Switch Quad-Core ArchitectureComparison FSB bottleneck other I/O links Intel Quad-Core Processor other I/O links Integrated memory controller operating at full CPU clock speed AMD Phenom™ X4 I/O and memory calls are implemented on separate, dedicated high-speed busses Die 1 Die 2 AMD Quad-Core Processor Integrated DDR2 Memory Controller HyperTransport™ Bus Shared L3 Cache 2000MHz HyperTransport™ technology link Slide 86: Presentation Title Month ##, 200# L2 core Çekirdek 1 Çekirdek 2 Çekirdek 2 Çekirdek 1 2MB Paylasimli 1MB ÖnBellek 1MB ÖnBellek Intel® Smart Cache Intel® Akilli Güç Yönetimi : Intel® Akilli Güç Yönetimi core 1 core 2 4 MB (Cache) 1MB L2 1MB L2 data Intel® Core core 1 Core 2 Intel® Advanced Smart Cache : Intel® Advanced Smart Cache Decreased traffic Increased traffic Higher cache hit rateReduced bus trafficLower latency to data Advantage L2 cache is shared equallyData stored in one placeOptimizes cache resourceUp to 100% utilization of L2 cache Intel’s Core i7 : Intel’s Core i7 Socket : Socket Known as the LGA 1366 or Socket B Contact points Core: Intel Quickpath Interconnect : Core: Intel Quickpath Interconnect Intel X58 Arch Replaced front side bus Max bandwidth: 16GB/s Unidirectional I7 920, 9404.8 GT/s = 19.2 GB/s I7 965XE 6.4 GT/s = 25.6GB/s Slide 95: Tank for your time and patience You do not have the permission to view this presentation. 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