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Digital Electronics – E&I2480 : 

Digital Electronics – E&I2480 Chapter 8 – Logic Gate Characteristics

Properties of Digital ICs : 

Prepared by K.T. NG 2 Properties of Digital ICs When you work with digital IC's, you should be familiar, not only with their logical operation, but also with such operational properties as Voltage levels Noise immunity Power dissipation Fan-in, and fan-out Propagation delays

Supply Voltage Designations : 

Prepared by K.T. NG 3 Supply Voltage Designations The supply voltages for various families have names which are based on the type of transistors used in their construction: TTL gates are made with bipolar transistors, which have a collector and an emitter, so the supply voltages are VCC and GROUND is occasionally given as VEE CMOS gates are built with field-effect transistors which have a drain and a source, so the supply voltages are VDD and VSS

Voltage Limits : 

Prepared by K.T. NG 4 Voltage Limits While the ideal voltage in TTL circuits are 0 (logic 0) and +5 volts (logic 1), the typical, or observed, voltages are different in practice It is important to know what tolerances must be observed in order to guarantee the correct operation of a digital circuit Four particular quantities are of interest in specifying the tolerance: 1. 2. 3. 4.

Voltage Limits (Cont.) : 

Prepared by K.T. NG 5 Voltage Limits (Cont.) VIHmin: The minimum input voltage which will be accepted as a logic 1 VILmax: The maximum input voltage which will be accepted as a logic 0 VOHmin: The minimum output voltage representing a logic 1 state VOLmax: The maximum output voltage representing a logic 0 state

Voltage Limits (Cont.) : 

Prepared by K.T. NG 6 Voltage Limits (Cont.) For the 3 logic families listed as an example, the specified values of these parameters are given in the following table In other words, real gates should perform at least as well as the values listed Note: For CMOS logic VDD can be as low as 3.5 V and as high as 15 V What the above information means is that, (for instance), if input to a 74LS04 NOT gate is at greater than or equal to 2.0 volts, it will be considered "high", and so the output should be "low", i.e. at a voltage less than or equal to 0.5 volts

Voltage Limits (Cont.) : 

Prepared by K.T. NG 7 Voltage Limits (Cont.) For each logic family, you should notice that the output voltage limits are more strict than the input voltage limits This is to provide noise immunity to the devices Values outside the given range are not allowed – indeterminate region VOL(max) is lower than VIL(max) to allow for noise and signal deterioration. Similarly VOH(min) is higher than VIH(min)

Noise Immunity : 

Prepared by K.T. NG 8 Noise Immunity Noise is the unwanted voltage that might add to the output of one gate. This may cause the voltage at the input to a logic circuit to drop below VIH or rise above VIL into the indeterminate or “illegal” region to produce undesired operation In order not to be adversely affected by noise, a logic circuit must have the ability to tolerate noise signals which is referred to as the noise immunity

Noise Margin : 

Prepared by K.T. NG 9 Noise Margin A measure of a circuit’s noise immunity is called the noise margin, which is expressed in volts There are 2 values of noise margin specified for a given logic circuit: the HIGH level noise margin (VNH) and the LOW level noise margin (VNL) These parameters are defined by the following equations: VNH = HIGH level noise margin = VOH(min) – VIH(min) VNL = LOW level noise margin = VIL(max) – VOL(max)

Comparing TTL and CMOS Noise Margins : 

Prepared by K.T. NG 10 Comparing TTL and CMOS Noise Margins The noise margin is much better for the CMOS than for the TTL family You may introduce almost 1.5 V of unwanted noise into the CMOS input before getting unpredictable results

Worked Example : 

Prepared by K.T. NG 11 Worked Example Given the following parameters, calculate the noise margin of 74LS series Solution: High Level Noise Margin, VNH = VOH(min) - VIH(min) = 2.7 V - 2.0 V = 0.7 V Low Level Noise Margin, VNL = VIL(max) - VOL(max) = 0.8 V - 0.4 V = 0.4 V

Current Limits : 

Prepared by K.T. NG 12 Current Limits Similar to that of voltage limits, there are limits to the input and output currents of each individual gate. Four particular quantities are of interest in specifying the tolerance: 1. 2. 3. 4.

Current Limits (Cont.) : 

Prepared by K.T. NG 13 Current Limits (Cont.) IIHmax: The maximum input current which must be supplied to a gate's input to guarantee the input will be high IILmax: The maximum input current which must be drawn from a gate's input to ground to guarantee the input will be low IOHmax: The maximum current which the gate can source through its output and still keep the output high IOLmax: The maximum current which the gate can sink through its output and still keep the output low

Current Direction : 

Prepared by K.T. NG 14 Current Direction According to IEEE standards, currents are directed into devices. Therefore, If a current in a specification is positive, it is entering the device If a current in a specification is negative, it is leaving the device The –ve sign means current direction is leaving the device rather than actual value

Current-Sourcing and Current-Sinking Action : 

Prepared by K.T. NG 15 Current-Sourcing and Current-Sinking Action Current sinking and sourcing rates are important while designing circuits. These ratings determine the current capacity to drive external devices Current Sinking It is the amount of current that the driving gate produces a outgoing current that flow into the load gate Current Sourcing It is the amount of incoming current that the driving gate receives from the loaded gate Most of the TTL can sink up to 16 mA and source 250 A

Fan-in : 

Prepared by K.T. NG 16 Fan-in Number of input signals to a gate Not an electrical property Function of the manufacturing process NAND gate with a Fan-in of 8

Loading and Fan-Out : 

Prepared by K.T. NG 17 Loading and Fan-Out When the output of a logic gate is connected to one or more inputs of the other gates, a load on the driving gate is created As more load gates are connected to the driving gate, the loading on the driving gate increases There is a limit to the number of load gate inputs that a given gate can drive. The limit is called fan-out of the gate

Fan-Out : 

Prepared by K.T. NG 18 Fan-Out A measure of the ability of the output of one gate to drive the input(s) of subsequent gates Usually specified as standard loads within a single family e.g., An input to an inverter in the same family For TTL devices, the number of standard loads is limited by the amount of input current each load requires as compared to the current that the driving gate can deliver. It is generally considered to be the smaller of the following two items: May have to compute based on current drive requirements when mixing families Although mixing families is not usually recommended

Fan-Out (Cont.) : 

Prepared by K.T. NG 19 Fan-Out (Cont.) An illustration of fan-out and the associated source and sink currents

Worked Example : 

Prepared by K.T. NG 20 Worked Example How many 74ALS00 NAND gate inputs can be driven by a 74ALS00 NAND gate outputs ? Solution: Refer to data sheet of 74ALS00, the maximum values of IOH = 0.4 mA, IOL = 8 mA, IIH = 20 A, and IIL = 0.1 mA Hence, Fan-out (high) = IOH(max) / IIH (max) = 0.4 mA/20  A = 400  A/20  A = 20 Fan-out (low) = IOL(max) / IIL(max) = 8 mA/0.1 mA = 80, The overall fan-out = fan-out (high) or fan-out (low) whichever is lower Hence, overall fan-out = 20 Note: If the fan-out has a fractional part, it should be dropped. In other words, you should always round down when calculating fan-out

Another Example : 

Prepared by K.T. NG 21 Another Example A unit load for some particular logic family is as follows: 1 UL = 50 A HIGH state = 1 mA LOW state Determine the fan-in and fan-out for a gate in this family that has the following parameters: IOH = 400 A IOL = 10mA IIH = 150 A IIL = 4 mA Solution: Fan-in = 150/50 = 3 UL or 4/1 = 4 UL Therefore fan-in = 3 or 3 UL Fan-out = 400/50 = 8 UL or 10/1 = 10 UL Therefore fan-out = 8 or 8 UL

Fan-out for CMOS Devices : 

Prepared by K.T. NG 22 Fan-out for CMOS Devices It is worth noting that fan-out is much higher for CMOS devices than for TTL devices IIL and IIH are extremely small for CMOS devices (< 1 A) Calculating fan-out as we did for TTL devices might yield a fan-out of 4000 for CMOS, compared to 10 for standard TTL However, the input capacitance of CMOS gates affects propagation delay, so increased fan-out results in increased delay

Timing Limits : 

Prepared by K.T. NG 23 Timing Limits Ideally changes to the inputs of a gate would be reflected at the output immediately, but in reality there is a slight delay In general, the delay may be different depending on whether the gate's output is going from low to high or from high to low Furthermore, the transitions themselves are not instantaneous, so they are defined as being at the 50% point of the voltage transitions

Propagation Delay : 

Prepared by K.T. NG 24 Propagation Delay Propagation delay is the time that it takes a gate to switch logic levels. Logic gates often have a different propagation delay switching from LOW to HIGH than from HIGH to LOW, so two types of delay are defined: tPLH = Propagation delay when the OUTPUT switches from LOW to HIGH tPHL = Propagation delay when the OUTPUT switches from HIGH to LOW The ‘lh’ (low to high) and the ‘hl’ (high to low) part refer to OUTPUT change, NOT input change Propagation delay:

Propagation Delay (Cont.) : 

Prepared by K.T. NG 25 Propagation Delay (Cont.) The propagation delay of a gate limits the frequency at which it can be operated The greater the propagation delay, the lower the maximum frequency Thus, a higher speed circuit is one that has a smaller propagation delay

Power Dissipation : 

Prepared by K.T. NG 26 Power Dissipation Generally, as propagation delays decrease (increased speed), the power consumption and related heat generation increase A logic gate draws current from the DC Supply voltage source When the gate is in the HIGH output state, an amount of current designated by ICCH is drawn In the LOW output state, a different amount of current, ICCL is drawn

Power Dissipation (Cont.) : 

Prepared by K.T. NG 27 Power Dissipation (Cont.) When a gate is pulsed, its output switches back and forth between HIGH and LOW and the amount of supply current varies between ICCH and ICCL The average power dissipation depends on the duty cycle and is usually specified for a duty cycle of 50% When the duty cycle is 50%, the output is HIGH half the time and LOW the other half The average supply current, ICC, is therefore ICC = (ICCH + ICCL)/2

Power Dissipation (Cont.) : 

Prepared by K.T. NG 28 Power Dissipation (Cont.) To determine the Average Power Dissipation PD of a gate the following equation is used: PD = VCCICC = VCC × (ICCH + ICCL)/2 Power Dissipation in a TTL circuit is essentially constant over its range of operating frequencies Power Dissipation in CMOS, however, is frequency dependent It’s extremely low under (dc) conditions and increases as the frequency increases

Example : 

Prepared by K.T. NG 29 Example A certain gate draws 2 mA when its output is HIGH and 3.6 mA when its output is LOW. What is its average power dissipation if VCC is 5 V and the gate is operated on a 50% duty cycle Solution: ICC = (ICCH + ICCL)/2 = (2 mA + 3.6 mA)/2 = 2.8 mA PD = VCC × ICC = 5 V * 2.8 mA = 14 mW

Speed Power Product : 

Prepared by K.T. NG 30 Speed Power Product The Speed Power Product provides a basis for the comparison of logic circuits when both propagation delay and power dissipation are important considerations in the selection of the type of logic to be used in a certain application The lower the speed power product, the better The unit of speed power product is the pico-joule (pJ) Example: HCMOS has a speed power product of 1.2pJ at 100KHz while the LS TTL is 22pJ

Interfacing Logic Families : 

Prepared by K.T. NG 31 Interfacing Logic Families To achieve optimum performance in a digital system, devices from more than one logic family can be used, taking advantages of the superior characteristics and function availability of each family for different parts of the system When interfacing logic families, several considerations must be made The output voltage level of one family must be high and low enough to meet the input requirements of the receiving family Also, the output current capability of the driving gate (IOL, IOH) must be high enough for the input draw of the receiving gate or gates (IIL, IIH)

Interfacing Logic Families (Cont.) : 

Prepared by K.T. NG 32 Interfacing Logic Families (Cont.) For such an arrangement to operate properly the following conditions are required to be satisfied: VOH (Driving)  VIH (Load) VOL (Driving)  VIL (Load) –IOH (Driving)  N × IIH (Load) IOL (Driving)  –N × IIL (Load)

Example : 

Prepared by K.T. NG 33 Example Find the number of low power 74-series TTL gates which can be driven from a 74 C-series CMOS gate. Given the specification are as follows:

Example (Cont.) : 

Prepared by K.T. NG 34 Example (Cont.) Solution: Since condition 1 & 2 are satisfied VOH (Driving)  VIH (Load)  VOH (CMOS) = 4.5 V  VIH (TTL) = 2.0 V VOL (Driving)  VIL (Load)  VOL (CMOS) = 0.5 V  VIL (TTL) = 0.7 V –IOH (Driving)  N × IIH (Load) –IOH (CMOS) = 100 A  N × IIH (TTL) = N × 10 A  N = 10 IOL (Driving)  –N × IIL (Load) IOL (CMOS) = 360 A  –N × IIL (TTL) = N × 180 A  N = 2. Therefore, a 74 C-series CMOS gate can drive only two 74-series low power TTL gates

Data Sheets : 

Prepared by K.T. NG 35 Data Sheets Different manufacturers prepare data sheets slightly differently, but the same types of information are found in all of them. In some form, most data sheets should contain the following information: Description What the device is Features How this device differs from other similar ones, by this manufacturer or others Pin Configuration How electrical connections are made to the chip

Data Sheet (Cont.) : 

Prepared by K.T. NG 36 Data Sheet (Cont.) Internal Schematic Functionally, how the inside appears (Physical appearance may be nothing like it) Absolute Maximum Ratings Limits of conditions under which the device can survive. (It may only function correctly over a much smaller range of conditions) Recommended Operating Conditions Limits of conditions under which the device can function correctly Electrical Characteristics Parameters for use when the chip is operating within normal limits Sample Circuits Examples of how the device might be hooked up in a circuit. Extremely useful

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