AgO Product Overview

Analog and RF Optimization : 

Analog and RF Optimization accelerating analog computing hillol.sarkar@ago-inc.com

Agenda : 

Agenda Company background Challenges in analog/RF design Introducing AnXplorer AnXplorer Optimization Conclusion

Company Background : 

Company Background Advanced generation Optimization for Analog and RF circuits (AgO) Founded by expert CAD developers Dr Partha Ray and Dr Tathagato Rai Dastidar in 2007 Founders previously in senior CAD development positions at National Semiconductor Strong track record in 8 patent awards and 15 research papers published Headquarters established in Silicon Valley under AgO brand in 2009 Worldwide sales channel established in Q1 2010

Agenda : 

Agenda Company background Challenges in analog/RF design Introducing AnXplorer AnXplorer Optimization Conclusion

Analog & RF ICs are Everywhere : 

Analog & RF ICs are Everywhere Analog and RF circuits are key to many systems Mobile communications (GSM, CDMA,WiMax, LTE) Short-range communications (WiFi, ZigBee) Automotive (sensors, Control systems) Consumer audio and video High speed I/O (Serdes, tranceivers, LVDS) Medical and Bio-informatics Analog mixed signal is growing at 13% CAGR Semiconductors as a whole only at 10%

EDA Market Forecast 2010-2015 : 

EDA Market Forecast 2010-2015 EDA Market Growth of 10 percent 2010-2011 Key driver for growth Wireless Broadband EDA is growing 9.7 CAGR 2009-2015 Increased demand for Analog tools Analog R&D is up by 6 percent from 2009 6 Source Frost & Sullivan 2009

Analog Design is Expensive : 

Analog Design is Expensive Analog circuits are ~2% of total transistor count 20% of total IC area 40% of total design effort Responsible for 50% of design respins Analog design requires specialist skills Analog designers are in short supply Design automation for analog lags that for digital design Tasks are labour intensive

…and worse in smaller process nodes : 

…and worse in smaller process nodes Costs of an analog design increase with finer geometries Design cost per IC cited as going from ~$4M with 0.18µm to ~$46M with 65 nm More complexity through algorithmic architectures ΣΔ and randomisation Auto calibration, correction and adaptation More digital controls More complexity because of complex modes End application modes Power saving modes Circuit operation modes Calibration and tuning for process variability Source: Jim Hogan, “Escape from analog Alcatraz”, DAC 2006 Interoperability Breakfast

Elimination of Re-spins is Key Challenge : 

Elimination of Re-spins is Key Challenge Source: Jim Hogan, “Escape from analog Alcatraz”, DAC 2006 Interoperability Breakfast 6-9 months 10-15 months 0 Time 1st TO 1 2 3 4 Final TO Respins Design to product specification coverage 100% gap Respins not only bring unbudgeted costs but can delay projects enough to lose profitability. Often only the 1st and 2nd to market are the only players to profit. 2nd challenge is to close the design gap faster

Agenda : 

Agenda Company background Challenges in analog/RF design Introducing AnXplorer AnXplorer Optimization Conclusion

Classic Analog Design Methodology : 

Classic Analog Design Methodology Design methodology has changed little over the years Manual, iterative design with many SPICE runs Define topology & resize devices Physical layout & adjust Extraction Layout verification Design specification & constraints Spice Spice

AgO Design Methodology : 

AgO Design Methodology Define topology Physical layout & adjust Extraction Layout verification Design specification & constraints Spice AnXplorer automates device resizing and SPICE runs

AnXplorer uses industry standard inputs : 

AnXplorer uses industry standard inputs AnXplorer Design objectives Definition of Design variables Sized and centered netlist Exploration database for tradeoff analysis Definition of Design variables Compatible with existing design flows Generates optimized and centred netlist that meets or exceeds objectives

Working with existing environments : 

Working with existing environments Supported simulators Cadence Spectre Synopsys HSpice Legend Design Technology MSim Mentor Eldo (Feb 2010) Operating systems Red Hat Enterprise Linux 4 Ubuntu 9.04

Optimization Approach : 

Optimization Approach Two stage optimisation approach Global optimisation using single corner Local centering using all corners Simulation- and equation-based optimisation supported Hierarchical design objectives Tradeoff analysis with exploration database Multi-threading support

Optimization Approach : 

Optimization Approach Device Rules are stored in a knowledge base Adaptive Algorithm takes corrective actions It is highly useful as design assistance Expert System allows users to design quickly 16

Cost Graph : 

Cost Graph Parameters are prioritized as per importance There is no need for weights Example settling time has high priority 17

AgO Optimisation Benefits : 

AgO Optimisation Benefits Productivity improvement Engineering efficiency should be improved by at least 5× Highly manual and iterative sizing of circuit elements is automated Enables experienced staff to focus on choosing circuit topologies Yield improvement/respin avoidance Robust centering of design to meet objectives Covers variation in process, temperature and voltage Simpler porting to new process nodes Circuit resizing is key element in porting an analog circuit Automation significantly reduces the time required

AgO Power Op Amp Test Case Optimization : 

19 AgO Power Op Amp Test Case Optimization Results in 9 Hours

High Gain OpAmp Test Case Summary : 

Increased DC Gain by 17.5 % Increased Unity Gain Bandwidth by 83 % Increased Phase Margin by 6.7 % Reduced Settling Time by 70 % Decreased Current Consumption by 28 % High Gain OpAmp Test Case Summary 20

Time Saved by AnXplorer : 

Time Saved by AnXplorer 21 10 Transistors manual optimization takes 40 Days AnXplorer takes 10 Hours Less Experienced Analog Engineers can design Analog Circuits

Equation Based Optimization : 

Equation Based Optimization 22 Special function support Rastrigin Function Griewangk Function Schwefel Function Michalewicz Function Easom Function Note: Gradient based optimization will not work for these functions Example Schwefel function

AgO DFM DFY : 

AgO optimizes for all process corners Circuit will function under any process variation Centered circuit has highest level of reliability AgO DFM DFY 23

AgO Data Base : 

GUI support Query language support Updated every 2 iterations GUI has 2 options Load global data base Load centered data base Query definition Data base results Wizard entry for optimization criteria AgO Data Base 24

Agenda : 

Agenda Company background Challenges in analog/RF design Introducing AnXplorer AnXplorer Optimization Conclusion

Conclusion : 

Conclusion Analog/RF design is rapidly growing Risk of respin remains high with predominantly manual design process AnXplorer can automate key manual optimization and simulation activities High performance optimizer produces designs meeting objectives and constraints Benefits Design team productivity Yield improvement Reduced respins

Analog and RF Optimization : 

Analog and RF Optimization accelerating analog computing hillol.sarkar@ago-inc..com