logging in or signing up Very Large Scale Integration aSGuest43958 Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINT lite Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: (To copy code, click on the text box) Embed: URL: Thumbnail: WordPress Embed Customize Embed The presentation is successfully added In Your Favorites. Views: 1561 Category: Education License: All Rights Reserved Like it (1) Dislike it (0) Added: May 02, 2010 This Presentation is Public Favorites: 1 Presentation Description for 4th sem bput students Comments Posting comment... By: venkatarakeshkumar (14 month(s) ago) hi, Can you mail me the above ppt plz. Saving..... Post Reply Close Saving..... Edit Comment Close Premium member Presentation Transcript Slide 1: VLSI Slide 2: What is VLSI? “Very Large Scale Integration” SSI – Small-Scale Integration (0-102)---1960 MSI – Medium-Scale Integration (102-103)---1967 LSI – Large-Scale Integration (103-105)---1972 VLSI – Very Large-Scale Integration (105-107)---1978 ULSI – Ultra Large-Scale Integration (>=107)---1989 GSI _ Giant Scale Integration (>=109)---2000 *Where these are given as no of transistors. Integration Level Trends : Integration Level Trends Obligatory historical Moore’s law plot Slide 5: Integrated Circuits/MEMs Hierarchy of various technology Semiconductor process Silicon GaAs Unipolar Bipolar Unipolar Bipolar ECL TTL NMOS PMOS CMOS Slide 6: Chips Integrated circuits consist of: A small square or rectangular “die”, < 1mm thick Small die: 1.5 mm x 1.5 mm => 2.25 mm2 Large die: 15 mm x 15 mm => 225 mm2 Larger die sizes mean: More logic, memory Less volume Less yield Dies are made from silicon (substrate) Substrate provides mechanical support and electrical common point Advancements over the years : Advancements over the years © Intel 4004 Processor Introduced in 1971 2300 Transistors 108 KHz Clock © Intel P4 Processor Introduced in 2000 40 Million Transistors 1.5GHz Clock System Design Pyramid : System Design Pyramid Slide 9: • Photo-litho-graphy: latin: light-stone-writing • Photolithography: an optical means for transferring patterns onto a substrate. • Patterns are first transferred to a photoresist layer. •Typically a wafer is about 8-10 inches in diameter. Individual ICs are placed inside it. Photolithography and Patterning Slide 10: Photoresist is a liquid film that is spread out onto a substrate, exposed with a desired pattern, and developed into a selectively placed layer for subsequent processing. • Photolithography is a binary pattern transfer: there is no gray-scale, color, nor depth to the image. Slide 14: Steps Photo resist Coating (covering) A light sensitive organic polymer (plastic) Mask/ Reticle formation Exposure to light (UV/X-RAY/E-BEAM) Slide 17: WHAT IS A PHOTOMASK? Photomasks are high precision plates containing microscopic images of electronic circuits. Photomasks are made from very flat pieces of quartz or glass with a layer of chrome on one side. Etched in the chrome is a portion of an electronic circuit design. This circuit design on the mask is also called geometry. Slide 18: The Resist The first step is to coat the Si/SiO2 wafer with a film of a light sensitive material, called a resist. A resist must also be capable of high fidelity recording of the pattern (resolution) and durable enough to survive later process steps Solvent Evaporates Slide 21: Photolithography Energy - causes (photo)chemical reactions that modify resist dissolution rate Mask - blocks energy transmission to some areas of the resist Aligner - aligns mask to previously exposed layers of the overall design Resist - records the masked pattern of energy Slide 22: Next Generation Lithography In 1996, five technology options were proposed for the 130 nm gate length technology: •X-ray proximity Lithography (XPL) •Extreme Ultraviolet (EUV) •Electron Projection Lithography (EPL) •Ion Projection Lithography (IPL) •Direct-write lithography (EBDW). These options were referred to as the next generation lithography. MOSFET Design Rules : MOSFET Design Rules Lambda based design Rule Micron Rule Minimum width and Spacing : Minimum width and Spacing Layer Value Poly 2L Active 3L N select 3L Metal 3L Slide 26: Stick Diagrams Slide 27: Wiring Tracks A wiring track is the space required for a wire 4 l width, 4 l spacing from neighbor = 8 l pitch Transistors also consume one wiring track Slide 28: Well spacing Wells must surround transistors by 6 l Implies 12 l between opposite transistor flavors Leaves room for one wire track Basic Circuit Layout : Basic Circuit Layout Stick Diagram Stick Diagrams Layout Diagrams : Layout Diagrams Stick Diagrams Slide 31: Example: Inverter MOSFET Arrays and AOI Gates : MOSFET Arrays and AOI Gates A B C y x y x A B C Parallel Connected MOS Patterning : Parallel Connected MOS Patterning x y A B X X X A B x y Alternate Layout Strategy : Alternate Layout Strategy A B x y X X X X x A B y MOSFET Arrays and AOI Gates NAND2 Layout : MOSFET Arrays and AOI Gates NAND2 Layout Vp Gnd NOR2 Layout : NOR2 Layout Vp Slide 37: Stick Diagrams Cells, Libraries, and Hierarchical Design : Cells, Libraries, and Hierarchical Design Creation of a Cell Library Gnd Slide 41: Cell Placement System Hierarchy (MOSFET-Gates-F/Fs-Registers-Networks-Systems) Floorplans and Interconnect Wiring Y= (# of Good Chips/Total No)*100% Y=Yield ‘Y’ depends on total area=A, and no of defects=D, Y=e *100% Interconnects : Interconnects Place and Route Algorithm. Wiring Delay td=kl2 l=length of inter connect. td You do not have the permission to view this presentation. In order to view it, please contact the author of the presentation.
Very Large Scale Integration aSGuest43958 Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINT lite Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: (To copy code, click on the text box) Embed: URL: Thumbnail: WordPress Embed Customize Embed The presentation is successfully added In Your Favorites. Views: 1561 Category: Education License: All Rights Reserved Like it (1) Dislike it (0) Added: May 02, 2010 This Presentation is Public Favorites: 1 Presentation Description for 4th sem bput students Comments Posting comment... By: venkatarakeshkumar (14 month(s) ago) hi, Can you mail me the above ppt plz. Saving..... Post Reply Close Saving..... Edit Comment Close Premium member Presentation Transcript Slide 1: VLSI Slide 2: What is VLSI? “Very Large Scale Integration” SSI – Small-Scale Integration (0-102)---1960 MSI – Medium-Scale Integration (102-103)---1967 LSI – Large-Scale Integration (103-105)---1972 VLSI – Very Large-Scale Integration (105-107)---1978 ULSI – Ultra Large-Scale Integration (>=107)---1989 GSI _ Giant Scale Integration (>=109)---2000 *Where these are given as no of transistors. Integration Level Trends : Integration Level Trends Obligatory historical Moore’s law plot Slide 5: Integrated Circuits/MEMs Hierarchy of various technology Semiconductor process Silicon GaAs Unipolar Bipolar Unipolar Bipolar ECL TTL NMOS PMOS CMOS Slide 6: Chips Integrated circuits consist of: A small square or rectangular “die”, < 1mm thick Small die: 1.5 mm x 1.5 mm => 2.25 mm2 Large die: 15 mm x 15 mm => 225 mm2 Larger die sizes mean: More logic, memory Less volume Less yield Dies are made from silicon (substrate) Substrate provides mechanical support and electrical common point Advancements over the years : Advancements over the years © Intel 4004 Processor Introduced in 1971 2300 Transistors 108 KHz Clock © Intel P4 Processor Introduced in 2000 40 Million Transistors 1.5GHz Clock System Design Pyramid : System Design Pyramid Slide 9: • Photo-litho-graphy: latin: light-stone-writing • Photolithography: an optical means for transferring patterns onto a substrate. • Patterns are first transferred to a photoresist layer. •Typically a wafer is about 8-10 inches in diameter. Individual ICs are placed inside it. Photolithography and Patterning Slide 10: Photoresist is a liquid film that is spread out onto a substrate, exposed with a desired pattern, and developed into a selectively placed layer for subsequent processing. • Photolithography is a binary pattern transfer: there is no gray-scale, color, nor depth to the image. Slide 14: Steps Photo resist Coating (covering) A light sensitive organic polymer (plastic) Mask/ Reticle formation Exposure to light (UV/X-RAY/E-BEAM) Slide 17: WHAT IS A PHOTOMASK? Photomasks are high precision plates containing microscopic images of electronic circuits. Photomasks are made from very flat pieces of quartz or glass with a layer of chrome on one side. Etched in the chrome is a portion of an electronic circuit design. This circuit design on the mask is also called geometry. Slide 18: The Resist The first step is to coat the Si/SiO2 wafer with a film of a light sensitive material, called a resist. A resist must also be capable of high fidelity recording of the pattern (resolution) and durable enough to survive later process steps Solvent Evaporates Slide 21: Photolithography Energy - causes (photo)chemical reactions that modify resist dissolution rate Mask - blocks energy transmission to some areas of the resist Aligner - aligns mask to previously exposed layers of the overall design Resist - records the masked pattern of energy Slide 22: Next Generation Lithography In 1996, five technology options were proposed for the 130 nm gate length technology: •X-ray proximity Lithography (XPL) •Extreme Ultraviolet (EUV) •Electron Projection Lithography (EPL) •Ion Projection Lithography (IPL) •Direct-write lithography (EBDW). These options were referred to as the next generation lithography. MOSFET Design Rules : MOSFET Design Rules Lambda based design Rule Micron Rule Minimum width and Spacing : Minimum width and Spacing Layer Value Poly 2L Active 3L N select 3L Metal 3L Slide 26: Stick Diagrams Slide 27: Wiring Tracks A wiring track is the space required for a wire 4 l width, 4 l spacing from neighbor = 8 l pitch Transistors also consume one wiring track Slide 28: Well spacing Wells must surround transistors by 6 l Implies 12 l between opposite transistor flavors Leaves room for one wire track Basic Circuit Layout : Basic Circuit Layout Stick Diagram Stick Diagrams Layout Diagrams : Layout Diagrams Stick Diagrams Slide 31: Example: Inverter MOSFET Arrays and AOI Gates : MOSFET Arrays and AOI Gates A B C y x y x A B C Parallel Connected MOS Patterning : Parallel Connected MOS Patterning x y A B X X X A B x y Alternate Layout Strategy : Alternate Layout Strategy A B x y X X X X x A B y MOSFET Arrays and AOI Gates NAND2 Layout : MOSFET Arrays and AOI Gates NAND2 Layout Vp Gnd NOR2 Layout : NOR2 Layout Vp Slide 37: Stick Diagrams Cells, Libraries, and Hierarchical Design : Cells, Libraries, and Hierarchical Design Creation of a Cell Library Gnd Slide 41: Cell Placement System Hierarchy (MOSFET-Gates-F/Fs-Registers-Networks-Systems) Floorplans and Interconnect Wiring Y= (# of Good Chips/Total No)*100% Y=Yield ‘Y’ depends on total area=A, and no of defects=D, Y=e *100% Interconnects : Interconnects Place and Route Algorithm. Wiring Delay td=kl2 l=length of inter connect. td