logging in or signing up FPGA mathewsubin3388 Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINT lite Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: Embed: Flash iPad Copy Does not support media & animations WordPress Embed Customize Embed URL: Copy Thumbnail: Copy The presentation is successfully added In Your Favorites. Views: 11805 Category: Science & Tech.. License: All Rights Reserved Like it (11) Dislike it (0) Added: September 29, 2009 This Presentation is Public Favorites: 8 Presentation Description Field programmable gate array. An introduction. Comments Posting comment... By: room115 (19 month(s) ago) ....... Saving..... Post Reply Close Saving..... Edit Comment Close By: dhruvraj (26 month(s) ago) its realy a nice presentation...........i like it.......... Saving..... Post Reply Close Saving..... Edit Comment Close By: lijagp (26 month(s) ago) thank you sir can u pls give me the pdf document of the ppt Saving..... Post Reply Close Saving..... Edit Comment Close By: hlsun (28 month(s) ago) hao! Saving..... Post Reply Close Saving..... Edit Comment Close By: cyber.aftab (30 month(s) ago) Thanks Sir Saving..... Post Reply Close Saving..... Edit Comment Close loading.... See all Premium member Presentation Transcript FPGA(Field Programmable Gate Array) : FPGA(Field Programmable Gate Array) Presented by : Subin Mathew RASET Cochin History : History Programmable Read Only Memory (PROM) fuse programming n- address i/p can implement n i/p logic fun. Problem: Area efficiency. Programmable Logic Array (PLA) Programmable AND plane followed by programmable or wired OR plane. Sum of product form Problem : Two level programming adds delay Next - : Next - Programmable Array Logic (PAL) Programmable AND plane and fixed OR plane. Flexible comparably. All these PLA and PAL are Simple Programmable Logic Devices (SPLD). Problem: Logic plane structure grows rapidly with number of inputs Next - : Next - To mitigate the problem Complex Programmable Logic Devices (CPLD) programmably interconnect multiple SPLDs. Problem : Extending to higher density difficult Less flexibility Comparison : Comparison FPGA : FPGA A Field Programmable Gate Array (FPGA) is a Programmable Logic Device(PLD) with higher densities and capable of implementing different functions in a short period of time. Topics covered:- FPGA Overview Logic Block FPGA Routing Techniques Programming Methodology FPGA Design Flow FPGA overview : FPGA overview 2-D array of logic blocks and flip-flops with programmable interconnections. Compact design User can configure Intersections between the logic blocks The function of each block World of Integrated Circuits : Full-Custom ASICs Semi-Custom ASICs User Programmable PLD FPGA World of Integrated Circuits Why do we need FPGAs? Which Way to Go? : Which Way to Go? Low development cost Short time to market Reprogrammable High performance ASICs FPGAs Low power Low cost in high volumes Other FPGA Advantages : Other FPGA Advantages Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower Mistakes not detected at design time have large impact on development time and cost FPGAs are perfect for rapid prototyping of digital circuits Easy upgrades like in case of software Unique applications Logic Blocks : Logic Blocks Purpose: to implement combinational and sequential logic functions. Logic blocks can be implemented by:- Transistor pairs Multiplexers Look up tables( LUT) Wide fan-in AND-OR structure. Granularity: is the hardware abstraction level. According to granularity, two types of Blocks : Fine Grain Logic Blocks Coarse Grain Logic Blocks Fine Grain : Fine Grain The Cross Point FPGA Transistors are interconnected. Logic block is implemented using transistor pair tiles. Slide 13: 2. Plessey FPGA :- 2-input NAND gate forms basic building block Static RAM programming technology Fine Grain : Fine Grain Advantage: Blocks are fully utilized. Disadvantage: Require large numbers of wire segments and programmable switches. Need more area. Coarse Grain Logic Blocks : Coarse Grain Logic Blocks Many types exists according to implementations Multiplexer Based and Look-up-Table Based are most common 1. The Xilinx Logic Block: A SRAM function as a LUT. Address line of SRAM as input Output of SRAM gives the logic output k-input logic function =2^k size SRAM K-i/p LUT gives 2^2^k logic functions Slide 16: Advantage: High functionality k inputs logic block can be implemented in no. of ways Disadvantage: Large no of memory cells required if i/p is large Slide 17: 2. Altera logic block:- Wide fan-in Up to 100 i/p AND gate fed into OR gate with 3-8 i/ps Advantage:- Few logic block can implement the entire functionality Less area required Disadvantage:- If i/ps are less, usage density of block will be low Pull up devices consume static power Effects of Granularity on FPGA Density and Performance : Effects of Granularity on FPGA Density and Performance Tradeoff Granularity increase -> Blocks less More Functional Blocks-> more area Area is normally measured by total number of bits needed to implement the design. So look the example Example : Example FPGA Routing Techniques : FPGA Routing Techniques Comprises of programmable switches and wires Provides connection between I/O blocks, logic blocks etc. Routing decides logic block density and area consumed Different routing techniques are:- Xilinx Routing architecture Actel routing methodology Altera routing methodology Slide 21: Xilinx Routing architecture connections are made through a connection block. SRAM is used to implement LUT. So connection sites are large Pass transistors for connecting output pins multiplexers for input pins. wire segments used are:- general purpose segments Direct interconnect long line clock lines Slide 22: Actel routing methodology more wire segments in horizontal direction. i/p & o/p vertical tracks can make connection with every horizontal track. Routing is flexible. Drawback:- more switches are required => more capacitive load. Slide 23: Altera routing methodology It has two level hierarchy. first level => 16 or 32 of the logicblocks are grouped into a Logic Array Block(LAB) connections are formed using EPROM Second level=> LABs are interconnected using Programmable Interconnect Array(PIA) Programming Methodology : Programming Methodology Electrically programmable switches are used to program FPGA Properties of programmable switch determine on- resistance, parasitic capacitance, volatility, reprogrammability, size etc. Various programming techniques are:- SRAM programming technology Floating Gate Programming Antifuse programming methodology Slide 25: SRAM programming technology Use Static RAM cells to control pass gates or multiplexers. 1= closed switch connection 0= open For mux, SRAM determines the mux input selection process. Advantage Fast re-programmability Standard IC fabrication Tech. is used Disadvantage SRAM volatile Requires large area Slide 26: Floating gate programming Tech used in EPROM and EEPROM devices is used Switch is disable by applying high voltage to gate-2 between gate-1 and drain. The charge is removed by UV light Advantage:-No external permanent memory is needed to program it at power-up Disadvantage:- Extra processing steps Static power loss due to pull up resistor and high on resistance Slide 27: Antifuse programming methodology 2 terminal device with an un programmed state present very high resistance. By applying high voltage create a low resistance link. Advantage:- Small size Low series resistance and low parasitic capacitance summary : summary Why better ? : Why better ? FPGA programmed using electrically programmable switches Routing architectures are complex. Logic is implemented using multiple levels of lower fan-in gates. Shorter time to market Ability to re-program in the field to fix bugs FPGA Disadvantage FPGAs are generally slower than their application-specific integrated circuit (ASIC) Can't handle as complex a design, and draw more power. Application : Application Reconfigurable computing. Applications of FPGAs include DSP, software-defined radio. The inherent parallelism of the logic resources on the FPGA allows for considerable compute throughput. FPGA Design and Programming : FPGA Design and Programming To define the behavior of the FPGA the user provides a hardware description language (HDL) or a schematic design. Then, using an electronic design automation tool, a technology-mapped net list is generated. The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route. The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. Once the design and validation process is complete, the binary file generated used to configure the FPGA. Slide 32: THANK YOU You do not have the permission to view this presentation. In order to view it, please contact the author of the presentation.