SV-scaling of MOS circuits

Scaling of MOS circuits by SURESHA V Professor,Dept. of E&C Visvesvaraya Technological University(VTU) Belgaum-590 014.karnataka State. INDIA e-mail: suresha.vee@gmail.com : 

1 Scaling of MOS circuits by SURESHA V Professor,Dept. of E&C Visvesvaraya Technological University(VTU) Belgaum-590 014.karnataka State. INDIA e-mail: suresha.vee@gmail.com Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Slide 2: 

2 Objectives: To know what is Scaling To know why scaling is required Figure(s) of Merit (FoM) for scaling Scaling models Scaling factors for device parameters Implications of scaling on design Limitations of scaling Learning outcomes: At the end of this module the students will be able understand what is scaling. Understand how to improve the performance of simple MOS circuits by scaling. Writing scaling Model for simple MOS device Understand the effect and limitation of scaling. Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Introduction: : 

3 Introduction: What is Scaling? Proportional adjustment of the dimensions of an electronic device while maintaining the electrical properties of the device, results in a device either larger or smaller than the un-scaled device. Then Which way do we scale the devices for VLSI? BIG and SLOW … or SMALL and FAST? What do we gain? Why Scaling?... Scale the devices and wires down, Make the chips ‘fatter’ – functionality, intelligence, memory – and – faster, Make more chips per wafer – increased yield, Make the end user Happy by giving more for less and therefore, make MORE MONEY!! Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

4 Contd… FoM for Scaling Impact of scaling is characterized in terms of several indicators: o Minimum feature size o Number of gates on one chip o Power dissipation o Maximum operational frequency o Die size o Production cost Many of the FoMs can be improved by shrinking the dimensions of transistors and interconnections. Shrinking the separation between features – transistors and wires Adjusting doping levels and supply voltages . Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

5 Contd… Technology Scaling Goals of scaling the dimensions by 30%: Reduce gate delay by 30% (increase operating frequency by 43%) Double transistor density Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency) Die size used to increase by 14% per generation Technology generation spans 2-3 years Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

6 Contd… Figure1: Illustrates the technology scaling in terms of minimum feature size. Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

7 Contd… Figure2 : illustrates the technology scaling in terms of transistor count . Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

8 Contd… Figure3: illustrates the technology scaling in terms of propagation delay Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

9 Contd… Figure4: illustrates the technology scaling in terms of power dissipation and density Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Slide 10: 

10 Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Scaling Models : 

11 Scaling Models Most commonly used Models are: Full Scaling (Constant Electrical Field): Ideal model – dimensions and voltage scale together by the same scale factor Fixed Voltage Scaling: Most common model until recently – only the dimensions scale, voltages remain constant General Scaling: Most realistic for today’s situation – voltages and dimensions scale with different factors Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Scaling Factors for Device Parameters : 

12 Scaling Factors for Device Parameters In our discussions we will consider two scaling factors, α and β 1/ β is the scaling factor for V DD and oxide thickness D 1/ α is scaling factor for all other linear dimensions We will assume electric field is kept constant Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

13 Contd… It is important that you understand how the following parameters are effected by scaling Gate Area Gate Capacitance per unit area Gate Capacitance Charge in Channel Channel Resistance Transistor Delay Maximum Operating Frequency Transistor Current Switching Energy Power Dissipation Per Gate (Static and Dynamic) Power Dissipation Per Unit Area Power - Speed Product Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

14 Contd… Example : Sacling of MOS tansistor Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Scaling Factors for Device Parameters : 

15 Scaling Factors for Device Parameters Gate area A g : Where L: Channel length and W: Channel width and both are scaled by 1/ α Thus A g is scaled up by 1/ α 2 2. Gate capacitance per unit area C o or C ox Where ε ox is permittivity of gate oxide(thin-ox)= ε ins ε o and D is the gate oxide thickness scaled by 1/ β Thus C ox is scaled up by Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

16 Contd… 3. Gate capacitance C g : Thus Cg is scaled up by β * 1/ α 2 = β / α 2 4. Parasitic capacitance C x C x is proportional to A x / d where d is the depletion width around source or drain and scaled by 1/ α A x is the area of the depletion region around source or drain, scaled by (1/ α 2 ). Thus Cx is scaled up by Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

17 Contd… 5.Carrier density in channel Q on where Q on is the average charge per unit area in the ‘on’ state. C o is scaled by β and V gs is scaled by 1/ β Thus Q on is scaled by 1 6.Channel Resistance R on Where μ = channel carrier mobility and assumed constant Thus R on is scaled by (1/ α * α * 1) = 1 Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

18 Contd… 7. Gate delay T d T d is proportional to R on * C g Thus Td is scaled by 8. Maximum operating frequency f o f o is inversely proportional to delay T d and is scaled by Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

19 Contd… 9.Saturation current I dss Both V gs and V t are scaled by (1/ β ). Therefore, Idss is scaled by 10. Current density J: J= I dss /A where A is cross sectional area of the Channel in the “on” state which is scaled by (1/ α 2 ) So, J is scaled by Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

20 Contd… 11.Switching energy per gate E g So Eg is scaled by 12. Power dissipation per gate P g P g comprises of two components: static component P gs and dynamic component P gd : Where, the static power component P gs is given by: Dynamic component P gd is given by: Since V DD scales by (1/ β ) and Ron scales by 1, Pgs scales by (1/ β 2 ). Since Eg scales by (1/ α 2 β ) and fo by ( α 2 / β ), Pgd also scales by (1/ β 2 ). Therefore, P g scales by (1/ β 2 ). Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

21 Contd… 13. Power dissipation per unit area P a 14. Power – speed product P T Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Summary of scaling effects: 

22 Summary of scaling effects Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Physical Limits: 

23 Physical Limits Will Moore’s Law run out of steam? Can’t build transistors smaller than an atom… Many reasons have been predicted for end of scaling Dynamic power Sub-threshold leakage, tunneling Short channel effects Fabrication costs Electro-migration Interconnect delay Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Limitations of Scaling: 

24 Limitations of Scaling Effects, as a result of scaling down- which eventually become severe enough to prevent further miniaturization. o Substrate doping o Depletion width o Limits of miniaturization o Limits of interconnect and contact resistance o Limits due to sub threshold currents o Limits on logic levels and supply voltage due to noise o Limits due to current density Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

25 Contd… Substrate doping Built-in(junction) potential V B depends on substrate doping level – can be neglected as long as V B is small compared to V DD . As length of a MOS transistor is reduced, the depletion region width –scaled down to prevent source and drain depletion region from meeting. The depletion region width d for the junctions is given by Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

26 Contd… V b built in potential and it given by Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

27 Contd… 2. Depletion width • N B is increased to reduce d, but this increases threshold voltage V t - against trends for scaling down. • Maximum value of N B (1.3*1019 cm -3 ) , at higher values, maximum electric field applied to gate is insufficient and no channel is formed. • N B maintained at satisfactory level in the channel region to reduce the above problem. • E max maximum electric field induced in the junction and it is given by Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

28 Contd… If N B is increased by α and if V a = 0 then Vb increased by ln α and d is decreased by Therefore Electric field across the depletion region is increased by Reach a critical level E crit with increasing N B Fig:5.2a shows the depletion width d as a function of N B and V dd .The dashed line indicates the maximum depletion width for Emax= Ecrit ,then d we have Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

29 Contd… Figure 5.1a: shows the relation between substrate concentration Vs depletion width , Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

30 Contd… Figure 5.1b: shows the relation between depletion width d and Electric field Vs , substrate doping N B Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

31 Contd… Figure 5.1c : Demonstrates the interconnect length Vs. propagation delay Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

32 Contd… Figure 5.1d : Demonstrates the oxide thickness Vs. thermal noise. Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

33 Contd… 3. Limits of miniaturization • Minimum size of transistor; process tech and physics of the device • Reduction of geometry; alignment accuracy and resolution • Size of transistor measured in terms of channel length L L = 2d (to prevent push through) • L determined by N B and V dd • Minimum transit time for an electron to travel from source to drain is • then the transit time t is given by Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

34 Contd… Maximum carrier drift velocity is approx. equals to V sat ,regardless of supply voltage. Therefore minimum transit time maybe assumed to occur for a minimum size transistor when Va is approx. 0 V Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

35 Contd… Fig 5.3 b : Relation for channel length L vs transit time t Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

36 Contd… 4 . Limits of interconnect and contact resistance Short distance interconnect- conductor length is scaled by 1/ α and resistance is increased by α For constant field scaling, I is scaled by 1/ α so that IR drop remains constant as a result of scaling.- driving capability/noise margin. Following graphs 5.6a and 5.6b shows the effect of interconnect and resistance Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

37 Contd… Figure5.6a : Demonstrates the length of interconnect L (mm) Vs propagation delay(sec). Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

38 Contd… Figure5.6 b : Demonstrates the length of interconnect L (mm) Vs propagation delay(sec). Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

39 Contd… 5. Limits due to subthreshold currents Major concern in scaling devices. I sub is directly proportional exp (V gs – V t ) q / KT As voltages are scaled down, ratio of V gs – V t to KT will reduce-so that threshold current increases. Therefore scaling V gs and V t together with V dd . Maximum electric field across a depletion region is Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

40 Contd… 6. Limits on supply voltage due to noise Decreased inter-feature spacing and greater switching speed –result in noise problems Fig5.7a : Relation for Thermal noise v/s oxide thickness Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

41 Contd… Fig5.7b : Relation for Thermal noise v/s substrate concentration Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

42 Contd… Figure 5.8 : relation for probability of total error v/s supply voltage Vdd Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Contd…: 

43 Contd… 7. Limits due to current density: Aluminum most commonly used material for forming interconnection in VLSI chips. However scalingdown dimension increase the current density in interconnections by the same factor. When the current density in Aluminum approaches 10 6 Amps/cm 2 , the interconnect are likely to be burned off owing to metal migration. The allowable current density in Aluminum are set below the limit of J= 1 to 2 mA /µm 2 Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

CONCLUSION: 

44 CONCLUSION Observation - Device scaling Gate capacitance per micron is nearly independent of process But ON resistance * micron improves with process Gates get faster with scaling ( good ) Dynamic power goes down with scaling ( good ) Current density goes up with scaling ( bad ) Velocity saturation makes lateral scaling unsustainable Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

CONCLUSION: 

45 CONCLUSION Observations – Interconnect scaling Capacitance per micron is remaining constant About 0.2 fF /mm Roughly 1/10 of gate capacitance Local wires are getting faster Not quite tracking transistor improvement But not a major problem Global wires are getting slower No longer possible to cross chip in one cycle Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

SUMMARY : 

46 SUMMARY Scaling allows people to build more complex machines That run faster too It does not to first order change the difficulty of module design Module wires will get worse, but only slowly You don’t think to rethink your wires in your adder, memory Or even your super-scalar processor core It does let you design more modules Continued scaling of uniprocessor performance is getting hard Machines using global resources run into wire limitations Machines will have to become more explicitly parallel Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Reference: 

47 Reference Basic VLSI design by Douglas A. Pucknel and Kamran Eshraghian, 3 rd edition PHI publication, India, year 2001( Page 123-144 ) Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Slide 48: 

48 THE END Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Slide 49: 

49 Any Question ? Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Slide 50: 

50 Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327

Slide 51: 

51 Scaling of MOS circuits Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia , D.K - 574 327 Any correction or suggestion please feedback to: e-mail : suresha.vee@gmail.com Mobile : +91 - 94485 24399