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Improved functional performance. Matched devices. Increased operating speeds. Reduction in power consumptionWhy should we designers know about fabrication?: Why should we designers know about fabrication? Design performance varies after fab . Due to process variations- Dimensions vary due to shifting of masks, Dopants diffusing beneath the masks, Etching deffects Hence MOS parameters like g m , W, L, I D varies . So we have to design with margins.Basic processes involved in fabricating Monolithic ICs: 4 Basic processes involved in fabricating Monolithic ICs 1. Silicon wafer (substrate) preparation 2. Epitaxial growth 3. Oxidation 4. Photolithography 5. Diffusion 6. Ion implantation 7. Isolation technique 8. Metallization 9. Assembly processing & packagingSilicon wafer (substrate) preparation: 5 Silicon wafer (substrate) preparation 1.Crystal growth &doping 2.Ingot trimming & grinding 3.Ingot slicing 4.Wafer policing & etching 5.Wafer cleaning Typical waferSlide 6: Silicon Wafer Preparation . The basic material required for making the substrate, i.e. silicon, is cut into thin sheets, or wafers. This step includes the substeps like crystal growth, doping, slicing into wafers, and polishing and cleaning the wafer. Silicon wafer preparation.Epitaxial growth: 7 Epitaxial growth Epitaxy means growing a single crystal silicon structure upon a original silicon substrate, so that the resulting layer is an extension of the substrate crystal structure. The basic chemical reaction in the epitaxial growth process of pure silicon is the hydrogen reduction of silicon tetrachloride. 1200 o C SiCl+ 2H <-----------> Si + 4 HClOxidation : 8 Oxidation WHY SiO 2 ? SiO 2 is an extremely hard protective coating & is unaffected by almost all reagents except by hydrochloric acid. Thus it stands against any contamination.Oxidation : 9 Oxidation The silicon wafers are stacked up in a quartz boat & then inserted into quartz furnace tube. The Si wafers are raised to a high temperature in the range of 950 to 1150 o C & Exposed to a gas containing O 2 or H 2 O or both. The chemical action is Si + 2HO-----------> Si O 2 + 2H2Oxidation: 10 Oxidation oxide thickness time, t Photolithography: 11 Photolithography The process of photolithography makes it possible to produce microscopically small circuit and device pattern on si wafer Two processes involved in photolithography a) Making a photographic mask b) Photo etching Photographic mask : 12 Photographic mask The development of photographic mask involves the preparation of initial artwork and its diffusion. reduction, decomposition of initial artwork or layout into several mask layers. Photo etching Photo etching is used for the removal of SiO 2 from desired regions so that the desired impurities can be diffusedPhotoresist Coating Processes: Photoresist Coating Processes Photoresists Negative Photoresist * Exposed areas remain insoluble & unexposed areas are etched Positive Photoresist * Exposed area becomes easily soluble in Developer & will be etched (removed)Slide 14: Characteristic Positive Negative Adhesion to silicon- fair excellent Relative cost- more less Developer base- aqueous organic Minimum- 0.5 μ m 2 μ m Step coverage- better lower Wet chemical resistance- fair excellentExposure Processes: Exposure Processes p- epi p+ substrate field oxide photoresist Expose Kr + F 2 (gas) * Inert Gases N 2Slide 16: After exposure, the wafer is removed and immersed in a Developer Solution . The wafer is then heated to harden the patterned resist so that it will withstand immersion into acids. A typical hardening bake is ~300C. Photo Lithography Exposure ToolDiffusion : 19 Diffusion The process of introducing impurities into selected regions of a silicon wafer is called diffusion. The rate at which various impurities diffuse into the silicon will be of the order of 1µm/hr at the temperature range of 900 0 C to 1100 0 C. The impurity atoms have the tendency to move from regions of higher concentrations to lower concentrationsIon implantation technique: 20 Ion implantation technique 1. It is performed at low temperature. Therefore, previously diffused regions have a lesser tendency for lateral spreading. 2. In diffusion process, temperature has to be controlled over a large area inside the oven, where as in ion implantation process, accelerating potential & beam content are dielectrically controlled from outside.Dielectric isolation : 21 Dielectric isolation In dielectric isolation, a layer of solid dielectric such as SiO 2 or ruby completely surrounds each components thereby producing isolation, both electrical & physical. This isolating dielectric layer is thick enough so that its associated capacitance is negligible. Also, it is possible to fabricate both N-channel & P-channel MOSFETs within the same silicon substrate.Metallization : 22 Metallization The process of producing a thin metal film layer that will serve to make interconnection of the various components on the chip is called metallization.Aluminium is preferred for metallization: 23 Aluminium is preferred for metallization It is a good conductor it is easy to deposit aluminium films using vacuum deposition. It makes good mechanical bonds with silicon It forms a low resistance contactIC packages available : 24 IC packages available Metal can package. Dual-in-line package. Ceramic flat package .CMOS Fabrication: Slide 25 CMOS Fabrication There are 4 types of CMOS Technology available: N-well process (N-tub) P-well process (P-tub) Twin tub process & Silicon on insulator (SOI) process.Slide 26: N-well: N-well is made in P-substrate. Where, N-well acts as substrate/ body for PMOS, NMOS uses the main P-substrate as it body(usual) P-well: P-well is made in N-substrate. Where, P-well acts as substrate/ body for NMOS, PMOS uses the main N-substrate as it body(usual) Twin tub: Two tubs (well) are used – both N-well and P-well. threshold voltage and body effect parameters can be individually optimized here. SOI: wells are not digged . Instead Islands are developed and various layers are Formed further. (field – inversion, latch up and body effect problems does’nt occur).Inverter Cross-section: Slide 27 Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistorsWell and Substrate Taps: Slide 28 Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / tapsInverter Mask Set: Slide 29 Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed lineDetailed Mask Views: Slide 30 Detailed Mask Views Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact MetalFabrication Steps: Slide 31 Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO 2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO 2Oxidation: Slide 32 Oxidation Grow SiO 2 on top of Si wafer 900 – 1200 C with H 2 O or O 2 in oxidation furnacePhotoresist: Slide 33 Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to lightLithography: Slide 34 Lithography Expose photoresist through n-well mask Strip off exposed photoresistEtch: Slide 35 Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposedStrip Photoresist: Slide 36 Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next stepn-well: Slide 37 n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO 2 , only enter exposed SiStrip Oxide: Slide 38 Strip Oxide Strip off the remaining oxide using HF Back to bare wafer but with n-wellPolysilicon: Slide 39 Polysilicon Deposit very thin layer of gate oxide Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH 4 ) Forms many small crystals called polysilicon Heavily doped to be good conductorPolysilicon Patterning: Slide 40 Polysilicon Patterning Use same lithography process to pattern polysiliconSelf-Aligned Process: Slide 41 Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contactN-diffusion: Slide 42 N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processingN-diffusion cont.: Slide 43 N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusionN-diffusion cont.: Slide 44 N-diffusion cont. Strip off oxide to complete patterning stepP-Diffusion: Slide 45 P-Diffusion Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contactContacts: Slide 46 Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are neededMetalization: Slide 47 Metalization formation of metal layer ( aluminium is widely used).Slide 48: Defective IC Individual integrated circuits are tested to distinguish good die from bad ones. n-well p-channel transistor p-well n-channel transistor p+ substrate bonding pad nitride Metal 2Die Cut and Assembly: Die Cut and Assembly Good chips are attached to a lead frame package.Die Attach and Wire Bonding: Die Attach and Wire Bonding lead frame wire bonding pad connecting pinFinal Test: Final Test Chips are electrically tested under varying environmental conditions.Layout: Slide 52 Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules: 53 Thank you You do not have the permission to view this presentation. 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