RapidIO technology2

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RapidIO Technology Applied in Multifunction Phased Array Radar (MPAR) (Introduction and literature Review)  :

RapidIO Technology Applied in Multifunction Phased Array Radar (MPAR) (Introduction and literature Review) Yu Sun Department of Electrical and Computer Engineering Radar Innovations Laboratory University of Oklahoma Final Presentation of ECE5990 031 Special Study Advisor: Dr. Yan Zhang

Slide 2:

RapidIO: High-speed Interconnect technology Other High-speed transaction technologies: Giga-bye Ethernet, PCI Express …… Question: Why RapidIO is preferred in Multifunction Phase Array Radar?

Future MPAR architecture:

Future MPAR architecture Transmit-Receive Elements (TR) --- partitioned into “sub-arrays” Overlapped Sub-Array Beamformer --- controlled by analog circuitry Digital Transceiver --- A/D conversion Digital Beamforming (DBF) --- all beams are computed concurrently ~1 Tera (10 12 ) operations per second Radar Signal processor --- Data analysis, processing

Multifunction Phased Array Radar (MPAR)’s needs on high-speed data transportation:

Estimated transportation throughput of the parallel DBF scheme: 1 Tera (10 12 ) operations per second. (level of 1 Giga-byte/s I/O bandwidth) significant challenge by using general-purpose programmable processors (e.g., DSPs) but tractable using field programmable gate arrays (FPGAs) Diagrams of fully parallel DBF design in MPAR Characters of MPAR data communication: complex network switches, high-speed transactions (Interconnection) Multifunction Phased Array Radar (MPAR)’s needs on high-speed data transportation

Interconnect Trends & Comparison:

Interconnect Trends & Comparison

Current high-speed interconnect technologies:

Current high-speed interconnect technologies Communication speed Successor to applications Gigabit Ethernet 1 Gbps 100Mbps Ethernet Initial: WAN,LAN Later: workstations, PCs and laptops PCI Express <10 Gbps PCI 2.3/PCI-X Initial: PCs and Servers Later: 3D graphics, 10GE NICs,Storage , PCI bridges RapidIO 1-10 Gbps Initially a processor interconnect technology Initial: embedded systems Later: Computing, defense, networking & CPU I/O

Advantage of RapidIO:

Advantage of RapidIO Protocol Efficiency comparison (RapidIO, Gigabit-Ethernet and PCI Express) Effective Bandwidth comparison

Slide 8:

Example RapidIO Architecture: interconnection between systems & devices

Our Current Plan: Applying High-Speed Serial I/O to Phased Array Radar :

Our Current Plan: Applying High-Speed Serial I/O to Phased Array Radar Multifunction Phase Array Radar signal processing diagram a. Acquire digital data from ADC ( in Phase Array Radar) b. Implement RapidIO on FPGA Use RapidIO to transfer data within & between FPGA boards Build RapidIO physical channel on PCB

Slide 10:

Overall design steps FPGA computer-aided system design design tools: Xilinx ISE 8.2 Modelsim challenges: understand, simulate and synthesize high-speed serial protocols RapidIO FPGA hardware realization FPGA board: Xilinx Virtex II – Pro with RocketIO transceivers challenges: Place & Route, hardware debugging RapidIO signal integrity design & Test Design tools: HFSS 10.1 Ansoft Designer 3.5 multi-layer PCB (OrCAD) challenges: design layout of differential pairs on PCB, minimize noise & crosstalks, optimize signal quality 1. 2. 3.

FPGA board: Xilinx Virtex II Pro:

FPGA board: Xilinx Virtex II Pro Virtex-II Pro Generic Architecture Overview Processor blocks: Xilinx Power PC CLB block: RAMs, LUT, MUX, ADDERs, Block Select RAMS, DCMs …… RocketIO blocks --- the basis of Xilinx's RapidIO technology & protocol --- 3.125 Gb/s maximum serial communication speed

Slide 12:

Xilinx Virtex-II Pro XC2VP20 FF1152 Kit P160 Prototype Module with I/O Header P160 Communications Module 2 P160 Analog Module Our FPGA development kits

Slide 13:

Xilinx RocketIO Transceiver Block Diagram Clock correction Channel bonding

Slide 14:

Xilinx RocketIO Transceiver Block Diagram 8B/10B encoder/decoder Digital Clock Management (DCM)

RapidIO signal integrity challenge: --- Gigabit transactions cause jitters, phase shift, cross-talk on wires --- difficult to layout communication wires on PCB :

RapidIO signal integrity challenge: --- Gigabit transactions cause jitters, phase shift, cross-talk on wires --- difficult to layout communication wires on PCB a. Jitter : Short-term variation of signal transaction from their ideal position. b. Noise spikes Eye diagram & mask

Differential Pairs Basis:

Differential Pairs Basis Differential pair carry complementary signals Advantage: less susceptible to noise, jitters, and cross-talks Better Signal Integrity EMI generation is greatly reduced. This becomes more important as edge rates increase and higher frequencies appear in I/O system. Transmit (TX) & Receive (RX) differential pair N & P nodes of differential pair

Differential pair’s effect on noise:

Outer Trace Width 5.25 mil Inner Trace Width 4.00 mil Differential Spacing 6.75 mil 50 ohm single-ended 100 ohm differential Example: Multi-layer PCB Stack-up Differential pair’s effect on noise If two pair routed very closely together: noise will affect both wires identically Receiving gate: Only interested in difference between two signals ---- less susceptible to noise

Slide 18:

Better eye diagram of Vertex II test platform differential channel with 2 feet of co-ax (Data Rate = 3.125 Gbps) Scope eye diagram of normal test stimulus by 10 inch using conventional twisted line

Slide 19:

Twisted differential line on multi-layer PCB Conventional Differential Pair wires: Coupled microstrip Coplanar strip Strip lines Still have problems: Crosstalk Radiated emission New differential pair technology: Twisted Differential Pair : Overcome Crosstalk, Radiated emission

Slide 20:

Twisted Differential Pair : Overcome Crosstalk, Radiated emission Measured radiated emission spectrum from the differential lines on a PCB. (a) Radiation from the conventional differential line (b) radiation from the proposed Twisted Differential Line. Comparison of the measured crosstalk voltage waveforms of the two differential line structures: Coulpled microstrip & TDL

Slide 21:

Black box of the left specific Differential Pair Differential output with different output capacitances Differential Pair Models & Simulation results Tools: Avnet Designer 3.5 HFSS 9.1

Slide 22:

Conclusion High-speed serial links are preferable in Phased Array Radar Large data flow rate in MPAR High-speed serial transceiver Save FPGA pin counts How to implement RapidIO FPGA Physical layer PCB Challenges in RapidIO design How to keep good signal integrity? Minimize noise, crosstalks, jitters…… Serial link technologies for RapidIO Clock Correction, 8B/10B converter, Channel Bonding……

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