Bath Tub Curve

CHARACTERISTICS OF BATH TUB CURVE WITH DIFFERENT PARAMETERS : 

CHARACTERISTICS OF BATH TUB CURVE WITH DIFFERENT PARAMETERS 1 IT,BHU M.TECH DTI(2009-2011) Trailokya Nath Sasamal Tarang Agarwal S.Goutam Kathik Jail Singh

BATH TUB CURVE : 

BATH TUB CURVE 2 λ(t) (t)

WEIBULL DISTRIBUTION: : 

WEIBULL DISTRIBUTION: where β is the shape parameter, also known as the Weibull slope η is the scale parameter γ is the location parameter (generally 0) A BATHTUB CURVE is a mixed Weibull distribution with one subpopulation with β < 1, one subpopulation with β = 1 and one subpopulation with β > 1 3

Slide 4: 

CDF of WEIBULL DISTRIBUTION is So PDF As we know that Hazard or Failure Rate λ (t) = S (t) no. Of surviving components For normalized standard we can take S(t) = 1 – F(t) 4

Slide 5: 

λ (t) = = Clearly when β = 1: λ (t) = = When β < 1: λ (t) is decreasing function with increase in t When β > 1: λ (t) is increasing function with increment in t Calculation of Failure Rate: 5

Slide 6: 

NOW Reliability : R (t) = 1 – F(t) So R (t) = M.T.B.F = M.T.B.F = η = 6

Source of Electronic Systems Failures : 

Source of Electronic Systems Failures Faulty fabrication process Faulty material Wrong specifications Wrong design Wrong interpretation of a requirement Wrong test All these faults manifest to electrical and timing failures, which might cause disasters. 7

Product Realization Process : 

Product Realization Process Requirements Specifications Design and Test Fabrication Faulty Product ? Production Test Failure Analysis Bin To the Client Burn-In-Test Acceptance Test Manifacturer Client 8

Testing Principle : 

Testing Principle The test engine employs test specifications to generate test stimuli and decides whether or not the device under test (DUT) passes the test. ATE Or Test Engineer Or Design Engineer VLSI Chip Or PCB Or System Test Stimuli Responses Test Engine DUT ATE : Automatic Test Equipement 9

BATH-TUB CURVE : 

BATH-TUB CURVE Hazard functions hazard rate is the limits of the number of risk events per unit time Characteristics of failure rate Provides the form of operations, properties and event failures Reliability of system(component) System can run consistently without complete failure 10

Infant Mortality : 

Infant Mortality Eliminating Early failure period Burn-in or Debugging testing For Screening defective components Environment Stress Screening Required Environment conditions Quality Control Quality of sub systems(component) Product Reliability Acceptance Test With in the acceptable range of failure 11

Wear Out Period : 

Wear Out Period Identify and Quantify failures Replacement of sub-systems (components) Preventive maintenance 12

ACCELERATED STRESS TESTING WITH THREE PHASES : 

ACCELERATED STRESS TESTING WITH THREE PHASES 13

Accelerated Stress Testing : 

Accelerated Stress Testing HALT (Highly Accelerated life test) Used to characterize the Equipment under test and to Identify the Equipment’s Safe operating limits. Step by step cycles of Environmental Variables (e.g. Temperature, Vibration, Acceleration, Shock etc.) Until Failures Occurs. HASS( Highly accelerated stress test ) 100% Screening of Product using HALT stresses. 14

TYPICAL FAILURES BY STRESS : 

TYPICAL FAILURES BY STRESS FAILURES DURING COLD STEP STRESS Circuit design issue Intermittent component FAILURES DURING HOT STEP STRESS Failed component Circuit design issue Degraded component FAILURES DURING VIBRATION STEP STRESS Broken component Shorted component Connector breaks from board 15

Thermal Step Stressing Cold : 

Thermal Step Stressing Cold Begin at ambient Use caution as fundamental limit is approached Approximate dwell time of 10 minutes at each temperature Allow sufficient time to run functional tests Find and fix failures Continue until fundamental limit of technology is reached Practice continuous failure monitoring 16

ABNORMALITIES : 

ABNORMALITIES At -60˚C Data Corrupted from Flash Memory. Temperature raised to -55˚C Problem remained. Non recover Failure mode. Lower Operating Limit (LOL): -55˚C Lower Destruct Limit (LDL):-60˚C 17

Thermal Step Stressing Hot : 

Thermal Step Stressing Hot Begin at ambient Step up in 10°C increments Use caution as fundamental limit is approached Approximate dwell time of 10 minutes at each temperature Allow sufficient time to run functional tests Find and fix failures Continue until fundamental limit of technology is reached Practice continuous failure monitoring 18

ABNORMALITIES : 

ABNORMALITIES At +120°C, both serial and Ethernet communications were lost with other devices. At +115°C, after recycling the input power , device communicates with other devices. Upper Operating Limit (UOL): +110°C Upper Destruct Limit (UDL): +>120°C 19

Vibration Step Stress : 

Vibration Step Stress Vibration is stepped-up in increments, 3-5 Grams on the product Dwell time at each level 10 minutes Allow sufficient time to run functional tests Continue until operational or destruct limit is found Find and fix failures 20

ABNORMALITIES : 

ABNORMALITIES At 10 Grms and 20 Grms, UUTs(unit under test) reboot by themselves .This may have been due to the vibration affecting the power supply connector at the PCB. At 30 Grms and higher, failures are related to USB communication. Vibration Operating Limit (VOL): 25 Grms Vibration Destruct Limit (VDL): >30 Grms 21

Lessons Learned : 

Lessons Learned Initially, at low vibration levels the UUTs kept rebooting. The problem was due to the intermittent power connections at the PCB/PS connector interface. The upper temperature limit was +110C – Communication with other devices lost. When the temperature dropped back to +100°C, communication reestablished .Root cause of this problem needs to be investigated. 22

Slide 23: 

HOW TO PERFORM BURN IN TEST 23

REDUCTION OF EARLY LIFE FAILURE : 

REDUCTION OF EARLY LIFE FAILURE Burn-In Test To weed out defective parts before shipping them to customers. Electronic test performed under elevated temperatures. Range of elevated temperatures depends on type of IC and its application area. eg : Thermotron industries =>ambient temp to 177 deg 24

STEPS INVOLVED IN BURN-IN TEST : 

STEPS INVOLVED IN BURN-IN TEST DUT’S (Device Under Test) are placed onto Burn-in Load Boards. Test is executed inside Burn-in chamber. 25

TYPES OF BURN-IN TEST : 

TYPES OF BURN-IN TEST STATIC TEST: DUT (Device under test) is stressed at elevated constant temperatures. IC is supplied with power supply (Vcc). No input signals are applied. Functionality is evaluated in final stage (DC parametric test etc). 26

Slide 27: 

DYNAMIC TEST: Similar to static test. Test vectors are applied to IC inputs Functionality of IC is evaluated in Final Stage i.e, DC parametric test 27

Slide 28: 

MONITORED TEST: Similar to Dynamic Burn-in. Output is monitored up to limited point. Identifies failing device in the burn-in process itself. Comprehensive evaluation is done at final stage. 28

Slide 29: 

TEST-IN BURN-IN: Combination of functional testing and burn-in testing. Functional input patterns are applied. Output responses are compared with reference values corresponding to fault free operation. More costly than other burn-in tests. 29

EXAMPLE OF BURN-IN TEST : 

EXAMPLE OF BURN-IN TEST Microcontroller Test signals are programmed into RAM of DUT itself. eg: write cycle Pass/fail result for each test is stored in EEPROM. Stored results are compared with reference values. Passed DUTs are sent to Final stage. 30

STANDARD OF BURN-IN TEST : 

STANDARD OF BURN-IN TEST MIL-STD-883: Standard for testing microelectronic devices. Environmental tests eg: Burn-in test 31

: 

BURN IN TESTING ON DUAL IN MEMORY MODULE 32

Slide 33: 

CST Inc, calls the test method - "ABT" or “Accelerated Burn-in Technology.” Memory Burn-in Strategy: Static Burn-in(70 to 80’c) Low Frequency Burn-in Dynamic burn-in(Full frequency operation) DIMM Memory Stress Test Dual In Memory module 33

Slide 34: 

Memory modules to be subjected to near "Boiling-point" . Under influence of Heat-Stress in a controlled Heater Box. Adding voltage bouncing on the memory bus voltages. Overclocking the memory bus by 10% over its recommended speed. 34

: 

Clock Testing : DDR3 DIMM data rate(800 MHZ to 1333 MHZ ) DDR2 DIMM data rate(400,533,667,800MHZ) DDR1 DIMM data rate (200,33,400,500MHZ) Functional Test: Multiple user Defined test patterns to detect shorts and opens. DC-Parametric Test(detect minute leakage current ) SPD Programming(serial presence detect) 35

Premature component failure : 

Premature component failure Infant mortality decreasing failure rate wear-out increasing failure rate 36

Slide 37: 

Two Rapid Heat Chamber: Burn-In Heater box having Halogen Lamps for rapid temperature ramp up(90 deg.).  Thermonics forced air system put forced heated air onto the memory module under test 37

Slide 38: 

Method of testing memory in large quantity  :Using PC Motherboard and Memory Diagnostic Software(MEMTEST86+).  Memory Application Tester(MAT), built with an actual Intel Motherboard, integrated video, keyboard, USB port. MAT quickly boots-up and displays the memory size, CPU Clock and Memory frequency. 38

“Memory Application Tester" :pin-point bad error bits location very accurately. :An optional Heater Box . : 

“Memory Application Tester" :pin-point bad error bits location very accurately. :An optional Heater Box . 39

Slide 40: 

DIM modules SODIM module DIMM slot Small Outline Dual inline Memory module 40

REFERENCES: : 

REFERENCES: http://www.ieee.org www.wikipedia.org http://www.weibull.com/hotwire/issue14/relbasics14.htm http://www.siliconfareast.com/lifedist4.htm http://www.bm.nsysu.edu.tw/tutorial/iylu/conferance%20paper/B035.pdf 41

Slide 42: 

http://www.weibull.com/LifeDataWeb/weibull_probability_density_function.htm H.J .Perlstein ,J.W .Littlefield ,I . Bazovsky “The quantification of environmental stress screening” proceeding institute of environmental sciences . R.K.Reddy . D.L.Dietrich, “A 2 Level Environmental stress screen model (ESS) model: a Mixed Distribution approach”. Thermotron Industries. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=04547315 http://en.wikipedia.org/wiki/MIL-STD-883#Environmental_tests.2C_methods_1001-1034 42

Slide 43: 

D. Kececioglu and F.-B. Sun, Burn-in Testing: Its Quantification and Optimization, DEStech Publications Inc., UK (1997). R.-P. Vollertsen, "Burn-In", IEEE International Integrated Reliability Workshop, USA, pp 167-173 (1999). dataPOWER. The Complete Yield Management Solution. PDF Solutions Inc., USA http:Hdp.pdfcom/site/products/dpc.html 43