logging in or signing up 464 Fab Slides Ch07 Teobaldo Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINTLite Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: (To copy code, click on the text box) Embed: URL: Thumbnail: WordPress Embed Customize Embed The presentation is successfully added In Your Favorites. Views: 679 Category: Entertainment License: All Rights Reserved Like it (1) Dislike it (0) Added: February 18, 2008 This Presentation is Public Favorites: 0 Presentation Description No description available. Comments Posting comment... Premium member Presentation Transcript Introduction toMicroelectronic Fabrication by Richard C. JaegerDistinguished University ProfessorECE DepartmentAuburn University : Introduction to Microelectronic Fabrication by Richard C. Jaeger Distinguished University Professor ECE Department Auburn University Chapter 7 Interconnections and Contacts Copyright Notice: Copyright Notice © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1.Interconnections and ContactsMOS Logic Circuit: Interconnections and Contacts MOS Logic Circuit 3 Basic Interconnection Levels n+ diffusion Polysilicon Aluminum Metallization Contacts Al-n+ Al-Polysilicon Al-p Substrate Contact Not Shown Figure 7.1 Portion of MOS integrated circuit (a) Top view (b) Cross sectionInterconnectionsResistivity of Metals: Interconnections Resistivity of Metals Commonly Used Metals Aluminum Titanium Tungsten Copper Less Frequently Utilized Nickel Platinum PaladiumContactsOhmic Contact Formation: Contacts Ohmic Contact Formation Ideal Ohmic Contact Rectifying Contact (similar to diode) Practical Nonlinear “Ohmic” ContactContactsOhmic Contact Formation: Contacts Ohmic Contact Formation Figure 7.3 Aluminum to p-type silicon forms an ohmic contact similar to Fig. 7.2(a) [Remember Al is p-type dopant] Aluminum to n-type silicon can form a rectifying contact (Schottky barrier diode) similar to Fig. 7.3(b) Aluminum to n+ silicon yields a contact similar to Fig. 7.3c Figure 7.2ContactsAluminum-Silicon Phase Diagram: Contacts Aluminum-Silicon Phase Diagram Aluminum-Silicon Eutectic Point 577o CContactsAluminum Spiking and Junction Penetration: Contacts Aluminum Spiking and Junction Penetration Silicon absorption into the aluminum results in aluminum spikes Spikes can short junctions or cause excess leakage Barrier metal deposited prior to metallization Sputter deposition of Al - 1% SiContactsAlloying of Contacts: Contacts Alloying of ContactsContactsContact Resistance: Contacts Contact ResistanceInterconnectionsElectromigration: Interconnections Electromigration (a) (b) High current density causes voids to form in interconnections “Electron wind” causes movement of metal atomsInterconnectionsElectromigration: Interconnections Electromigration Copper added to aluminum to improve lifetime (Al, 4% Cu, 1% Si) Heavier metals (e. g. Cu) have lower activation energyInterconnectionsDiffused Interconnections: Interconnections Diffused Interconnections n- and p-type diffusions can be used for local interconnections pn-junction diode must be kept in its reverse-biased (non-conducting) state All interconnections have a series resistance R and shunt capacitance C per unit length The RC time constant limits operating frequency n+ and polysilicon lines RS ≥ 30 W/square Figure 7.9 Lumped RC model for a small section of an n+ diffusionInterconnectionsDiffused Interconnection: Interconnections Diffused Interconnection Diffused interconnection in NMOS OR gate. Merged source and drain regions used to interconnect devices Multiple contacts used to reduce overall contact resistance Figure 7.10InterconnectionsBuried and Butted Contacts: Interconnections Buried and Butted Contacts Techniques for interconnecting polysilicon and n+ diffusion Standard metal level link Buried contact with polysilicon in contact with diffusion (requires additional mask step to place n+ under polysilicon Butted contact with aluminum overlap Figure 7.11InterconnectionsSilicides/Polycides/Salicides : Interconnections Silicides/Polycides/Salicides Silicides of noble and refractory metals can be used to reduce sheet resistance of polisilicon and diffused interconnections Provide shunting layer in parallel with original inteconnection Figure 7.12InterconnectionsProperties of Various Silicides: Interconnections Properties of Various SilicidesInterconnectionsSalicide: Interconnections Salicide Self-Aligned Silicide on silicon and polysilicon Often termed “Salicide”ContactsSilicide Contacts in Devices: Contacts Silicide Contacts in DevicesInterconnectionsLiftoff Process: Interconnections Liftoff Process Subtractive etching process Additive metal liftoff process Figure 7.15InterconnectionsMultilevel Metallization: Interconnections Multilevel Metallization Two level metal processes Silicon dioxide, polyimide or silicon nitride dielectrics Vias formed to connect between metal levels Vias can be filled (b)to improve planarization Figure 7.16InterconnectionsMultilevel Metallization: Interconnections Multilevel Metallization Example of multilevel aluminum metallization with tungsten via plugs Planarity achieved through Chemical Mechanical Polishing (CMP) Figure 7.17 Multilevel aluminum metallization with tungsten plugs. Copyright 1998 IEEE. Reprinted with permission from Ref. [7].InterconnectionsPlated Copper: Interconnections Plated Copper Copper deposited using “standard” plating processes adapted to microelectronics Seed layer deposited Mask layer deposited and patterned Copper plated up Mask layer removed Seed layer etched awayInterconnectionsCopper Damascene Process: Interconnections Copper Damascene Process Damascene process used to obtain highly planar surfaces Dielectric layer (insulator) deposited and patterned Seed layer deposited Copper plated Surface polished mechanical & chemicalInterconnectionsDual Damascene Process: Interconnections Dual Damascene ProcessInterconnectionsDual Damascene Process (cont.): Interconnections Dual Damascene Process (cont.)Multilevel MetallizationExamples: Multilevel Metallization Examples Figure 7.20 Dual Damascene copper combined with aluminum-copper and tungsten plugs on the lower levels. Copyright 1997 IEEE. Reprinted with permission from Ref. [6]. (b) Dual Damsascene Copper. Courtesy of Motorola Inc. Note planarity of both structures. (a) (b)Interconnections and ContactsReferences: Interconnections and Contacts ReferencesEnd of Chapter 7: End of Chapter 7 You do not have the permission to view this presentation. In order to view it, please contact the author of the presentation.
464 Fab Slides Ch07 Teobaldo Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINTLite Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: (To copy code, click on the text box) Embed: URL: Thumbnail: WordPress Embed Customize Embed The presentation is successfully added In Your Favorites. Views: 679 Category: Entertainment License: All Rights Reserved Like it (1) Dislike it (0) Added: February 18, 2008 This Presentation is Public Favorites: 0 Presentation Description No description available. Comments Posting comment... Premium member Presentation Transcript Introduction toMicroelectronic Fabrication by Richard C. JaegerDistinguished University ProfessorECE DepartmentAuburn University : Introduction to Microelectronic Fabrication by Richard C. Jaeger Distinguished University Professor ECE Department Auburn University Chapter 7 Interconnections and Contacts Copyright Notice: Copyright Notice © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1.Interconnections and ContactsMOS Logic Circuit: Interconnections and Contacts MOS Logic Circuit 3 Basic Interconnection Levels n+ diffusion Polysilicon Aluminum Metallization Contacts Al-n+ Al-Polysilicon Al-p Substrate Contact Not Shown Figure 7.1 Portion of MOS integrated circuit (a) Top view (b) Cross sectionInterconnectionsResistivity of Metals: Interconnections Resistivity of Metals Commonly Used Metals Aluminum Titanium Tungsten Copper Less Frequently Utilized Nickel Platinum PaladiumContactsOhmic Contact Formation: Contacts Ohmic Contact Formation Ideal Ohmic Contact Rectifying Contact (similar to diode) Practical Nonlinear “Ohmic” ContactContactsOhmic Contact Formation: Contacts Ohmic Contact Formation Figure 7.3 Aluminum to p-type silicon forms an ohmic contact similar to Fig. 7.2(a) [Remember Al is p-type dopant] Aluminum to n-type silicon can form a rectifying contact (Schottky barrier diode) similar to Fig. 7.3(b) Aluminum to n+ silicon yields a contact similar to Fig. 7.3c Figure 7.2ContactsAluminum-Silicon Phase Diagram: Contacts Aluminum-Silicon Phase Diagram Aluminum-Silicon Eutectic Point 577o CContactsAluminum Spiking and Junction Penetration: Contacts Aluminum Spiking and Junction Penetration Silicon absorption into the aluminum results in aluminum spikes Spikes can short junctions or cause excess leakage Barrier metal deposited prior to metallization Sputter deposition of Al - 1% SiContactsAlloying of Contacts: Contacts Alloying of ContactsContactsContact Resistance: Contacts Contact ResistanceInterconnectionsElectromigration: Interconnections Electromigration (a) (b) High current density causes voids to form in interconnections “Electron wind” causes movement of metal atomsInterconnectionsElectromigration: Interconnections Electromigration Copper added to aluminum to improve lifetime (Al, 4% Cu, 1% Si) Heavier metals (e. g. Cu) have lower activation energyInterconnectionsDiffused Interconnections: Interconnections Diffused Interconnections n- and p-type diffusions can be used for local interconnections pn-junction diode must be kept in its reverse-biased (non-conducting) state All interconnections have a series resistance R and shunt capacitance C per unit length The RC time constant limits operating frequency n+ and polysilicon lines RS ≥ 30 W/square Figure 7.9 Lumped RC model for a small section of an n+ diffusionInterconnectionsDiffused Interconnection: Interconnections Diffused Interconnection Diffused interconnection in NMOS OR gate. Merged source and drain regions used to interconnect devices Multiple contacts used to reduce overall contact resistance Figure 7.10InterconnectionsBuried and Butted Contacts: Interconnections Buried and Butted Contacts Techniques for interconnecting polysilicon and n+ diffusion Standard metal level link Buried contact with polysilicon in contact with diffusion (requires additional mask step to place n+ under polysilicon Butted contact with aluminum overlap Figure 7.11InterconnectionsSilicides/Polycides/Salicides : Interconnections Silicides/Polycides/Salicides Silicides of noble and refractory metals can be used to reduce sheet resistance of polisilicon and diffused interconnections Provide shunting layer in parallel with original inteconnection Figure 7.12InterconnectionsProperties of Various Silicides: Interconnections Properties of Various SilicidesInterconnectionsSalicide: Interconnections Salicide Self-Aligned Silicide on silicon and polysilicon Often termed “Salicide”ContactsSilicide Contacts in Devices: Contacts Silicide Contacts in DevicesInterconnectionsLiftoff Process: Interconnections Liftoff Process Subtractive etching process Additive metal liftoff process Figure 7.15InterconnectionsMultilevel Metallization: Interconnections Multilevel Metallization Two level metal processes Silicon dioxide, polyimide or silicon nitride dielectrics Vias formed to connect between metal levels Vias can be filled (b)to improve planarization Figure 7.16InterconnectionsMultilevel Metallization: Interconnections Multilevel Metallization Example of multilevel aluminum metallization with tungsten via plugs Planarity achieved through Chemical Mechanical Polishing (CMP) Figure 7.17 Multilevel aluminum metallization with tungsten plugs. Copyright 1998 IEEE. Reprinted with permission from Ref. [7].InterconnectionsPlated Copper: Interconnections Plated Copper Copper deposited using “standard” plating processes adapted to microelectronics Seed layer deposited Mask layer deposited and patterned Copper plated up Mask layer removed Seed layer etched awayInterconnectionsCopper Damascene Process: Interconnections Copper Damascene Process Damascene process used to obtain highly planar surfaces Dielectric layer (insulator) deposited and patterned Seed layer deposited Copper plated Surface polished mechanical & chemicalInterconnectionsDual Damascene Process: Interconnections Dual Damascene ProcessInterconnectionsDual Damascene Process (cont.): Interconnections Dual Damascene Process (cont.)Multilevel MetallizationExamples: Multilevel Metallization Examples Figure 7.20 Dual Damascene copper combined with aluminum-copper and tungsten plugs on the lower levels. Copyright 1997 IEEE. Reprinted with permission from Ref. [6]. (b) Dual Damsascene Copper. Courtesy of Motorola Inc. Note planarity of both structures. (a) (b)Interconnections and ContactsReferences: Interconnections and Contacts ReferencesEnd of Chapter 7: End of Chapter 7